“60° LAGGING BUS CLAMPING IN SPACE VECTOR

PULSE WIDTH MODULATION

Department of Electrical and Electronics Engineering

NIT Tiruchirappalli

BY:
INDRAJEET BHANU
207223008
CONTENT

 INTRODUCTION
 SIGNIFICANCE OF 60º BUS CLAMPING
 SVPWM BASICS
 IMPLEMENTATION TO 60º BUS CLAMPING
 WAVEFORMS
 ADVANTAGE OF BUS CLAMPING
 CONCLUSIONS
INTRODUCTION
 Digital control techniques of AC motors, such as the space vector pulse width modulation
(SVPWM), have been developed with wide range industrial applications. The SVPWM
was brought forward in specifically for the frequency varying and speed regulation of AC
motors. It controls the motor based on the switching of space voltage vectors, by which an
approximate circular rotary magnetic field is obtained.
 Compared to traditional methods like Sinusoidal Pulse Width Modulation (SPWM), SVM
allows for higher modulation indexes, enabling more efficient control of the motor.
Moreover, SVM techniques are easy to implement in digital processors, making them
practical and widely used in modern industrial applications.
SIGNIFICANCE OF 60º BUS CLAMPING

 There is a class of PWM techniques where every phase remains clamped for a
duration of 60º in every half cycle with only the other two phases switching during
the said duration. The 60º clamping duration can be anywhere within the middle 120º
of the given half cycle. Such techniques are called 'bus-clamped PWM techniques.
This PWM techniques can be used to reduce one or more of the following :
 It achieves the wide linear modulation range associated with PWM third –harmonic
injection automatically with out the need for distorted modulation.
 It has lower base band harmonics then regular PWM or other sine based modulation
methods, or otherwise optimizes harmonics.
 It is fast and convenient to compute.
 SVPWM BASICS
In the SVPWM technique, the reference voltage is provided by a revolving reference
vector which is sampled once in every sub cycles Ts. The reference vector is realized by
the nearest four space vectors (two active vectors and two zero vectors), as shown in fig

for sector I based on the volt - second balance principle

Ts = T 1+ T 2+ T3
 IMPLEMENTATION OF 60º BUS CLAMPING.
There are two popular approaches to real-time PWM, namely the
triangle-comparison approach and space vector approach. Bus-
clamped PWM generation is possible with both the approaches.
While using the space vector approach, the modulating waves
corresponding to four types of clamping are as shown in Figs
 In Type-I clamping, every phase remains clamped during the middle 60º duration of every
half cycle, i.e. between 60º and 120º in the positive half cycle, and between 240º and
300º in the negative half cycle as shown in Fig a.
 In Type-II, the clamping is between 30º and 90º in the positive half cycle, and between
210º and 270º in the negative half cycle as shown in Fig b.
 b. In Type-III, the clamping is done between 90º and 150º in the positive half cycle, and
between 270º and 330º in the negative half cycle as in Fig c
 In Type-IV, every phase is clamped during the middle 30º of every quarter cycle of its
fundamental voltage as shown in Fig d
These modulating waves can be generated by adding suitable zero-sequence triplen
frequency components to the 3-phase sinusoidal waves. The zero-sequence component
required can be obtained from the 3-phase sinusoids themselves. Comparison of such 3-
phase modulating waves against a common triangular carrier gives the PWM patterns
required.
 60º degree lagging bus clamping implementation

 The clamping is done between 90ºand 150º in the positive half cycle, and between 270º and 330º in the
negative half cycle
 only two phases switch within the given sub cycle and the third remains clamped to one of the DC buses.
If the zero state --- (0) is avoided, then R-phase remains clamped to the positive bus. If the zero state +++
(7) is avoided, then the B-phase remains clamped to the negative bus. Such sequences can be termed as
'clamping sequences'.
 In bus-clamped PWM techniques, clamping sequences using only one zero state are used to generate the
samples. The zero state is changed at the sector boundaries. The zero state is changed at the sector
boundaries
• A voltage source inverter and the voltage vectors produced by it are shown in Figs.1a and b repectively.

In the space vector approach, the reference is provided as a revolving space vector as shown in Fig.1b.
 We Will Completed calculation for R phase
(1) R phase will be clamped between 90ºand 150º in the positive half cycle, and
between 270º and 330º in the negative half cycle
(2) S1 and S1’, S2 and S2’, S3 and S3’ is complementary switches.
For Sector 1: For Sector 1:
Switch State: 111 101 100 Switch State: 000 110 010
S1 conduct for Time Ta= t1+t2+(to/2) S1 conduct for Time Ta= t1
S2 conduct for Time Tb= t2+(to/2) S2 conduct for Time Tb= t2+t1
S3 conduct for Time Tc= (to/2) S3 conduct for Time Tc= 0
For Sector 3:
Switch State: 111 010 011
S1 conduct for Time Ta= (to/2)
S2 conduct for Time Tb= t1+t2+(to/2)
S3 conduct for Time Tc= t2+ (to/2)
For sector 5:
Switch State: 111 001 101
S1 conduct for Time Ta= (to/2}+t2
S2 conduct for Time Tb= to/2
S3 conduct for Time Tc= t1+t2+ (to/2}
For Sector 4:
switch state: 000 011 001
S1 conduct for Time Ta= 0
S2 conduct for Time Tb= t1
S3 conduct for Time Tc= t1+t2
For sector 6:
Switch State: 000 001 100
S1 conduct for Time Ta= t1+t2
S2 conduct for Time Tb= 0
S3 conduct for Time Tc= t1
 SECTOR GENRATION
 MODULATING SIGNAL
 GATE PULSE GENRATED WAVEFORM
 OUTPUT VOLTAGE WAVEFORM
Advantage
(1) Bus-clamped PWM techniques at high switching frequencies is useful.
(2) For a given carrier frequency or sampling frequency, reduction in switching
frequency is the most obvious of the benefits of using bus-clamped PWM
techniques.
(3) Reduction in harmonic distortion
(4) For a given N, use of clamping sequences instead of conventional sequences
leads to reduction in the pulse number (P)
 OUTPUT CURRENT WAVEFORM
CONCLUSION:
 If switching frequency and switching losses are dominant, bus-clamped PWM
techniques can be used to reduce them.
 If the harmonic distortion is to be reduced subject to a given switching frequency
or pulse number, as the case may be, such techniques can once again be used to
reduce the distortion.
 At very high switching frequencies where the time available for computation is
very low, bus-clamped techniques result in a reduction of the computational
burden as well.
Thank You