21ec503 Vlsi Design Unit 1

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R.M.D ENGINEERING COLLEGE
DEPARTMENT OF ELECTRONICS AND COMMUNICATION
ENGINEERING
21EC503 - VLSI DESIGN (Lab Integrated)
Department :Electronics and Communication

Engineering
Batch/Year :2021-2025/III
Created by :Ms.P.Santhoshini
:Ms.S.Gayathri Priya
Date :05.08.2023
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TABLE OF CONTENTS
S.NO CONTENTS PAGE
NUMBER
1 COURSE OBJECTIVES 7
2 PRE REQUISITES 8
3 SYLLABUS 9
4 COURSE OUTCOMES 10
5 CO- PO/PSO MAPPING 11
UNIT 1 – INTRODUCTION TO MOS TRANSISTOR 15

6
6.1 Lecture Plan 16
6.2 Activity based learning 17
6.3 Lecture Notes 18
6.3.1 MOS Transistor 18
6.3.2 Long Channel I-V Characteristics 30
6.3.3 CV Characteristics of MOSFET 43
6.3.4 CMOS Inverter DC Transfer Characteristics 48
6.3.5 Non Linear I-V Characteristics: (or) Non Ideal I-V 56

effects
6.3.6 Pass Transistor and Transmission Gate Logics 62
6.3.7 CMOS Scaling and its limitations 64
6.3.8 Propagation delay of CMOS Inverter 67
6.3.9 Linear Delay Model-Logical effort 70
6.3.10 Stick Diagrams 76
6.3.11 Layout 79
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S.NO CONTENTS PAGE
NUMBER
6.4 Assignments 90
6.5 Part A Question & Answer 91
6.6 Part B Questions 102
6.7 Supportive online Certification courses 104
6.8 Real time Applications in day to day life and to 105

Industry
6.9 Content beyond the Syllabus 106
7 Assessment Schedule 111
8 Prescribed Text Books & Reference Books 112
9 Mini Project suggestions 113
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1. COURSE OBJECTIVE
OBJECTIVES:
❖ To study the fundamentals of CMOS circuits and its characteristics.
❖ To learn the design and realization of combinational & sequential digital

circuits.
❖ To study the Architectural choices and performance tradeoffs involved in
designing and realizing the circuits in CMOS technology are discussed.
❖ To learn the different FPGA architectures and testability of VLSI circuits.
❖ To learn Hardware Descriptive Language (Verilog / VHDL) and to
familiarize fusing of logical modules on FPGAs.
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2. PRE REQUISITES
1.21EC303 - DIGITAL ELECTRONICS

By learning this course,the student will have a thorough knowledge
about designing combinational and sequential circuits.
2. 21EC404 – LINEAR INTEGRATED CIRCUITS

By learning this course,the student will have deep insight in fabrication
and designing ICs
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3. SYLLABUS
Subject Code Subject Name L T P C
21EC503 VLSI Design (Lab 3 0 2 4

Integrated)
UNIT I INTRODUCTION TO MOS TRANSISTOR 15

MOS Transistor, CMOS logic, Inverter, Layout Design Rules, Gate Layouts, Stick
Diagrams, Long-Channel I-V Characteristics, C-V Characteristics, Non ideal I-V
Effects, DC Transfer characteristics, RC Delay Model, Elmore Delay, Linear Delay
Model, Logical effort, Parasitic Delay, Delay in Logic Gate, Scaling.
LIST OF EXPERIMENTS
1. Design of inverter using LT-SPICE
2. Layout verification of CMOS inverter, NOR and NAND gates
UNIT II COMBINATIONAL MOS LOGIC CIRCUITS 15

Circuit Families: Static CMOS, Ratioed Circuits, Cascode Voltage Switch Logic,
Dynamic Circuits, Pass Transistor Logic, Transmission Gates, Domino, Dual Rail
Domino, CPL, DCVSPG, DPL, CMOS Power Dissipation. Design of combinational
circuits using Verilog.
LIST OF EXPERIMENTS
1. Design of adder and subtractor
2. Design of multiplexer and demultiplexer
UNIT III SEQUENTIAL CIRCUIT DESIGN 15

Static latches and Registers, Dynamic latches and Registers, Pulse Registers,
Pipelining, Schmitt Trigger, Monostable Sequential Circuits, Astable Sequential
Circuits. Timing Issues: Timing Classification of Digital System, Synchronous Design,
Design of sequential circuits using Verilog.
LIST OF EXPERIMENTS
1.Design of Flipflops
2.Design of counter
3. Design of
universal shift
register
4. Design of Mealy
and Moore State
Machines
5. Design of random
Access Memory 9
UNIT IV DESIGN OF ARITHMETIC BUILDING BLOCKS AND
SUBSYSTEM
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Arithmetic Building Blocks: Data Paths, Adders, Multipliers, Shifters, ALUs, power
and speed tradeoffs, Designing Memory and Array structures: Memory Architectures
and Building Blocks, Memory Core, Memory Peripheral Circuitry.
LIST OF EXPERIMENTS
1.Design of Arithmetic Logic Unit
2.Design of Ripple Carry Adder
3.Design of Carry Select Adder
4.Design of Multiplier
UNIT V
IMPLEMENTATION
STRATEGIES AND
TESTING
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FPGA Building Block Architectures, FPGA Interconnect Routing Procedures. Design
for Testability: Ad Hoc Testing, Scan Design, BIST, IDDQ Testing, Boundary Scan.
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4. COURSE OUTCOMES
After successful completion of the course, the students should be

able to
Highest
Course Outcomes Cognitive
Level
Understand the fundamental principles of VLSI circuit design in
CO1 K2
digital domain
CO2 Realize the combinational circuits using different logic families K3
Understand the memory design in sequential logic circuits K3

CO3
Analyze the architectural choice and performance tradeoff

CO4 K3
involved in data path unit design
Understand the different FPGA architectures and its testing K2

CO5
Design, Simulate to verify the functionality of logic modules

CO6 using EDA tools and familiarize fusing of logical modules on K2
FPGA
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Program Outcomes(PO)
Program Engineering Graduates will be able to
Outcome
Engineering Apply the knowledge of mathematics,science,engineering
PO1 fundamentals, and an engineering specialization to the solution of
complex engineering problems.
Knowledge
Identify, formulate, review research literature, and analyze complex
Problem
PO2 engineering problems reaching substantiated conclusions using first
principles of mathematics, natural sciences, and engineering sciences
Analysis
Design solutions for complex engineering problems and design

Design/
system components or processes that meet the specified needs with
PO3 Development
appropriate consideration for the public health and safety, and the
of Solutions
cultural, societal, and environmental considerations.
Conduct
Use research-based knowledge and research methods including
Investigations
PO4 design of experiments, analysis and interpretation of data, and
of Complex
synthesis of the information to provide valid conclusions.
Problems
Create, select, and apply appropriate techniques, resources, and

Modern Tool modern engineering and IT tools including prediction and modeling to
PO5 Usage complex engineering activities with an understanding of
the limitations.
Apply reasoning informed by the contextual knowledge to assess

The Engineer
PO6 societal, health, safety, legal and cultural issues and the consequent
and Society
responsibilities relevant to the professional engineering practice.
Environment Understand the impact of the professional engineering solutions in

and societal and environmental contexts, and demonstrate the knowledge
PO7
Sustainability of, and need for sustainable development.
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Program Outcomes(PO)
Program Engineering Graduates will be able to
Outcome
Ethics Apply ethical principles and commit to professional ethics and
PO8
responsibilities and norms of the engineering practice
Individual and Function effectively as an individual, and as a member or leader in
PO9 Team Work diverse teams, and in multidisciplinary settings
Communicate effectively on complex engineering activities with the

engineering community and with society at large, such as, being able
Communication
PO10 to comprehend and write effective reports and design
documentation, make effective presentations, and give and receive
clear instructions
Project Demonstrate knowledge and understanding of the engineering and
management principles and apply these to one’s own work, as a
PO11 Management member and leader in a team, to manage projects and
and Finance
in multidisciplinary environments
Lifelong Recognize the need for, and have the preparation and ability to
PO12 Learning engage in independent and life-long learning in the broadest context
of technological change.
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Program Specific Outcomes(PSO)
Program
Specific Electronics and Communication Engineering Graduates will be
Outcomes able to
To analyze, design and develop solutions by applying

PSO1 foundational concepts of Electronics and Communication
Engineering.
PSO2 To apply design principles and best practices for developing

quality products for scientific and business applications
To adapt to emerging information and communication

PSO3 technologies (ICT) to innovate ideas and solutions to
existing/novel problems.
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5. CO- PO/PSO Mapping
Course Level
Program
Outcom of Program Outcomes Specific
es CO Outcomes
K3,K5
K K4 K4 K5 A3 A2 A3 A3 A3 A3 A2 K6 K5 K3
,K6
3
P
PO-
O- PO-2 PO-3 PO-4 PO-7 PO-8
PO-5 PO-6 9 PO-10 PO-11 PO-12 PSO-1 PSO-2 PSO-3
1
CO1 K2 2 1 1 - - - - - - - - - - 1 1
CO2 K3 1 2 - - - - - - - - - - - 2 1
CO3 K3 2 1 2 - - - - - - - - - - 1 1
CO4 K3 1 2 1 - - - - - - - - - - 1 2
CO5 K3 1 2 - - - - - - - - - - - 1 2
CO6 K2 2 1 1 - - - - - - - - - - 1 1
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6. UNIT I INTRODUCTION TO MOS
TRANSISTOR
MOS Transistor, CMOS logic, Inverter, Layout Design Rules, Gate Layouts,
Stick Diagrams, Long-Channel I-V Characteristics, C-V Charters tics, Non ideal
I-V Effects, DC Transfer characteristics, RC Delay Model, Elmore Delay,
Linear Delay Model, Logical effort, Parasitic Delay, Delay in Logic Gate,
Scaling.
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6.1 LECTURE PLAN
UNIT I - INTRODUCTION TO MOS TRANSISTOR
S. No. Propose Ac Per Reaso
of d Date tu tai Taxonom Mode of n for
N Per al y level Devia
o Topic nin Delivery tion
iod Da g
s te CO
CMOS logic, Inverter, K2 Chalk &

1 1 CO1 -
Understand Talk
K1
Layout Design Rules CO1 Chalk &
2 1 Remember -
Talk
K1
Gate Layouts, Stick CO1
3 1 Remember PPT -
Diagrams
Long-Channel I-V K2
CO1 Chalk &
4 Charters tics, C- 1 Understand -
Talk
V Characteristics
K2
CO1 Chalk &
5 Non ideal I-V Effects 1 Understand -
Talk
K1
DC Transfer CO1 Chalk &
6 1 Remember -
characteristics Talk
K2
RC Delay Model, CO1 Chalk &
7 1 Understand -
Elmore Delay Talk
K4
Linear Delay Model, CO1 Chalk &
8 1 Analyze -
Logical effort Talk
Parasitic Delay, K3
CO1 Chalk &
9 Delay in Logic Gate, 1 Apply -
Talk
Scaling.
Total No. of Periods : 9

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6.2 ACTIVITY BASED LEARNING
1.Group Discussion:
A group of 6 students are given with the below mentioned topic and facilitated
a group discussion in which the advent of technology was discussed.
Future of VLSI in the AI Era
2.Role Play:
A group of 6 students are given the following topic and instructed to
demonstrate a role play.
Layout Design Rules
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6.3 LECTURE NOTES
UNIT I INTRODUCTION TO MOS TRANSISTOR
INTRODUCTION
6.3.1. MOS Transistor
Introduction
A metal–oxide–semiconductor field-effect transistor (MOSFET, MOS-FET, or
MOSFET)
is a field-effect transistor (FET with an insulated gate) where the voltage determines the
conductivity of the device. It is used for switching or amplifying signals. The ability to
change conductivity with the amount of applied voltage can be used for amplifying or
switching electronic signals. MOSFETs are now even more common than BJTs (bipolar
junction transistors) in digital and analog circuits.
Fig 1. MOSFET Structure
MOSFET structure
A MOSFET is by far the most common transistor in digital circuits, as hundreds of
thousands or millions of them may be included in a memory chip or microprocessor. Since
they can be made with either p-type or n-type semiconductors, complementary pairs of
MOS transistors can be used to make switching circuits with very low power consumption,
in the form of CMOS logic.
Why MOSFET?
MOSFETs are particularly useful in amplifiers due to their input impedance being
nearly infinite which allows the amplifier to capture almost all the incoming signal.
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(ii) Depletion Mode
A small positive voltage is applied to the gate, resulting in some positive charge on
the gate. The holes in the body are repelled from the region directly beneath the
gate, resulting in a depletion region forming below the gate.
(iii) Inversion Mode

A higher positive potential exceeding a critical threshold voltage V t is applied,
attracting more positive charge to the gate. The holes are repelled further and some free
electrons in the body are attracted to the region beneath the gate. This conductive layer of
electrons in the p-type body is called the inversion layer.
■ Accumulation mode (Vgs << 0)
■ Depletion mode (0<Vgs<Vt)
■ Inversion mode (Vgs > Vt)
Electrically an MOS device can be considered as a voltage-controlled switch that

conducts when Vgs >Vt (given Vds>0). An MOS device can be considered as a voltage-
controlled resistor.
Some fundamental physical parameters that describe a MOSFET device:
These parameters include:
■ Process Transconductance Parameter K=µCox
■ Channel Aspect Ratio L
W/
on the
The Process Transconductance Parameter k ′ is a constant that depends
process technology used to fabricate an integrated circuit. Therefore, all the transistors on a
given substrate will typically have the same value of this parameter.The Channel Aspect
Ratio W/L is simply the ratio of channel width W to channel length L. This is the MOSFET
device parameter that can be altered and modified by the circuit designer to satisfy the
requirements of the given circuit or transistor.
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Effective gate voltage (Vgs-Vt)
Effective gate voltage is defined as the voltage which results in the flow of drain to
source current.Now, the controlling of source to gate voltage is responsible for the conduction
of current between the source and the drain. If the gate voltage exceeds a given value, called
the threshold voltage only then the conduction begins.
In general, any MOSFET is seen to exhibit three operating regions viz.,

(i) Cut-Off Region (Ids=0, Vgs< Vt)
Cut-off region is a region in which the MOSFET will be OFF as there will be no current
flow through it. In this region, MOSFET behaves like an open switch and is thus used when
they are required to function as electronic switches.
(ii)Ohmic or Linear Region or Active Region or Non Saturated Region (Vgs> Vt
and Vds< Vgs-Vt)
Ids=(µCoxW/L)[((Vgs-Vt)Vds-Vds2)/2] , Ids=β[(Vgs-Vt)Vds-Vds ^2 /2]
Where
β= µCoxW/L; K=µCox=> Process transconductance parameter Where,
µn = Mobility of the electrons = Capacitance of the oxide layer
Cox
W = Width of the gate area L = Length of the channel
Vgs =Gate to Source voltage Vt = Threshold voltage Vds = Drain to Source voltage
Ohmic or linear region is a region where in the current Ids increases with an increase in the
value of Vds. Ids depend on Vgs and Vds. When MOSFETs are made to operate in this region,
they can be used as amplifiers.
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(ii)Saturation Region: Vgs> Vt and Vds>Vgs-Vt
Ids=(µCoxW/L)[Vgs-Vt]^2/2,
Ids=β [Vgs-Vt]^2/2
In Saturation, when Vds>Vgs-Vt, => Vd>Vg-Vt, that
is when Vg is not big enough,
then the channel no longer reaches the drain. The Horizontal electric field created by drain,
Vds is stronger than the vertical field created by the gate, Vgs. So the channel gets pinched
off. Now Ids is ideally independent of Vds and can be controlled only by Vgs.In saturation
region, the MOSFETs have their IDS constant inspite of an increase in VDS and occurs once
VDS exceeds the value of pinch-off voltage VP. Under this condition, the device will act like
a closed switch through which a saturated value of IDS flows. As a result, this operating
region is chosen whenever MOSFETs are required to perform switching operations. Having
known this, let us now analyze the biasing conditions at which these regions are
experienced for each kind of MOSFET.
n-channel Enhancement-type MOSFET
Figure 7a shows the transfer characteristics (drain-to-source current IDS versus
gate-to-source voltage VGS) of n-channel Enhancement-type MOSFETs. From this, it is
evident that the current through the device will be zero until the VGS exceeds the value of
threshold voltage VT. This is because under this state, the device will be void of channel
which will be connecting the drain and the source terminals. Under this condition, even an
increase in VDS will result in no current flow as indicated by the corresponding output
characteristics (IDS versus VDS) shown by Figure 1b. As a result this state represents nothing
but the cut-off region of MOSFET's operation.

Next, once VGS crosses VT, the current through the device increases with an
increase in IDS initially (Ohmic region) and then saturates to a value as determined by the
VGS (saturation region of operation) i.e. as VGS increases, even the saturation current
than IDSS1 as VGS2 > VGS1, IDSS3 is greater than > VGS2, so on and so forth.
IDSS2 as VGS3
flowing through the device also increases. This is evident by Figure 7b where IDSS2 is greater
Further, Figure 1b also shows the locus of pinch-off voltage (black discontinuous curve),
from which VP is seen to increase with an increase in VGS
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Fig. 7 n-channel Enhancement-type MOSFET
(a) Transfer Characteristics (b) Output Characteristics.
p-channel Enhancement-type MOSFET

Figure 8a shows the transfer characteristics of p-type
enhancement
MOSFETs from which it is evident that IDS remains zero (cutoff state) untill VGS becomes
equal to -VT. This is because, only then the channel will be formed to connect the drain
terminal of the device with its source terminal. After this, the IDS is seen to increase in
reverse direction (meaning an increase in ISD, signifying an increase in the device current
which will flow from source to drain) with the decrease in the value of VDS. This means
that the device is functioning in its ohmic region wherein the current through the device
increases with an increase in the applied voltage (which will be VSD).
However as VDS becomes equal to –VP, the device enters into saturation during which
a saturated amount of current (IDSS) flows through the device, as decided by the value of
VGS. Further it is to be noted that the value of saturation current flowing through the device
is seen to increase as the VGS becomes more and more negative i.e. saturation current for
VGS3 is greater than that for VGS2 and that in the case of VGS4 is much greater than both of
them as VGS3 is more negative than VGS2 while VGS4 is much more negative when compared
to either of them (Figure 8b).
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In addition, from the locus of the pinch-off voltage it is also clear that as VGS
becomes more and more negative, even the negativity of VP also increases.
Fig. 8 p-channel Enhancement-type MOSFET

n-channel Depletion-type MOSFET

The transfer characteristics of n-channel depletion MOSFET shown by
Figure9a
indicate that the device has a current flowing through it even when VGS is 0V. This indicates
that these devices conduct even when the gate terminal is left unbiased, which is further
emphasized by the VGS0 curve of Figure 9b. Under this condition, the current through the
MOSFET is seen to increase with an increase in the value of VDS (Ohmic region) untill VDS
becomes equal to pinch-off voltage VP. After this, IDS will get saturated to a particular level
IDSS (saturation region of operation) which increases with an increase in VGS i.e. I DSS3
> IDSS2
> IDSS1, as VGS3 > VGS2 > VGS1.
Further, the locus of the pinch-off voltage also shows that V P increases
with an
increase in VGS. However it is to be noted that, if one needs to operate these devices
in cut-off state, then it is required to make VGS negative and once it becomes
equal to -VT, the conduction through the device stops (I DS = 0) as it gets deprived of
its n-type channel (Figure 9a).
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Fig. 9 n-channel Depletion-type MOSFET
p-channel Depletion-type MOSFET

The transfer characteristics of p-channel depletion mode MOSFETs (Figure
4a) show that these devices will be normally ON, and thus conduct even in the absence of
VGS. This is because they are characterized by the presence of a channel in their default
state due to which they have non-zero IDS for VGS = 0V, as indicated by the VGS0 curve
of Figure 4b. Although the value of such a current increases with an increase in VDS
initially (ohmic region of operation), it is seen to saturate once the VDS exceeds
VP
(saturation region of operation). The value of this saturation current is determined by the
VGS, and is seen to increase in negative direction as VGS becomes more and more
negative. For example, the saturation current for VGS3 is greater than that for VGS2 which
is however greater when compared to that for VGS1. This is because VGS2 is more
negative when compared to VGS1, and VGS3 is much more negative when compared to
either of them. Next, one can also note from the locus of pinch-off point that even VP
starts to become more and more negative as the negativity associated with the VGS
increases.
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Lastly, it is evident from Figure 10a that in order to switch these devices OFF, one
needs to increase VGS such that it becomes equal to or greater than that of the threshold
voltage VT. This is because, when done so, these devices will be deprived of their p- type
channel, which further drives the MOSFETs into their cut-off region of operation.
Fig. 10. p-channel Depletion-type MOSFET

The explanation provided above can be summarized in the form of a following table
Kind of MOSFET Region of Operation
Cut-Off Ohmic/Linear Saturation
n-channel
Enhancement-
VGS < VT VGS > VT and VDS < VP VGS > VT and VDS > VP
type
p-channel
Enhancement- VGS < -VT and VDS > VGS < -VT and VDS <
type VGS > -VT -VP -VP
n-channel
Depletion-type VGS < -VT VGS > -VT and VDS < VP VGS > -VT and VDS > VP
p-channel VGS < VT and VDS > VGS < VT and VDS <
Depletion-type VGS > VT -VP -VP
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Avalanche Breakdown/Punchthrough:
When the drain source voltage become very high, then punchthrough
occurs and Ids will be independent of Vds as well as Vgs.
Factors on which Ids id dependent on (for fixed Vgs and

Vds) :
1.Distance between drain and source=> Length of Channel,L.
2.Channel Width, W
3.Threshold Voltage, Vt
4.Thickness of gate oxide, tox
5.Dielectric constant of gate oxide, εox
6.Carrier Mobility, µ
6.3.2 Long-Channel I-V Characteristics :

MOS transistors have three regions of operation:
❑ Cutoff or subthreshold region
❑ Linear region
❑ Saturation region
Let us derive a model relating the current and voltage (I-V) for an nMOS
transistor
in each of these regions. This model is variously known as the long-channel, ideal, first-
order, or Shockley model. The long-channel model assumes that the current through an
OFF transistor is 0.Cut off region VGS = 0,VDS =0 and ID=0.
When a transistor turns ON (Vgs > Vt), the gate attracts carriers (electrons) to form
a channel. The electrons drift from source to drain at a rate proportional to the electric
field between these regions. We can compute currents if we know the amount of charge in
the channel and the rate at which it moves.
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We know that the charge on each plate of a capacitor is Q = CV. ------(1)
Thus, the charge in the channel Q channel is Q channel =Cg ( Vgc- Vt ) -----(2)
Average gate to channel potential:
Vgc = (Vgs + Vgd)/2 = Vgs – Vds/2 ----(3)
Fig 11. Average gate to channel voltage
We can model the gate as a parallel plate capacitor with capacitance proportional to
area over thickness. If the gate has length L and width W and the oxide thickness is tox.
shown in the figure 12
The capacitance is -------- -(4) -
where ε0 is the permittivity of free space, 8.85 × 10^–14 F/cm, and the permittivity
of SiO2 is kox = 3.9 ,εox/tox term is called Cox, the capacitance per unit area of the gate
oxide.
Fig 12. Transistor Dimensions
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Each carrier in the channel is accelerated to an average velocity, v, proportional to the
lateral electric field, i.e., the field between source and drain. The constant of
proportionality μ is called the mobility.
v = μ E -------- (5)
The electric field E is the voltage difference between drain and source Vds divided by the
channel length
E=Vds / L
------------- (6)
The time required for carriers to cross the channel is the channel length divided by
the carrier velocity: L/v. Therefore, the current between source and drain is the total
amount of charge in the channel divided by the time required to cross
𝐼𝐷𝑆 = 𝑄 𝐶ℎ𝑎𝑛𝑛𝑒𝑙 --------- (7)
𝐿
𝑉
𝐶𝐺 (𝑉 − 𝑉𝐷𝑆2 −𝑉𝑇)
𝐼𝐷𝑆 = 𝐺𝑆 𝐿 -----------(8)
µ𝑉
𝐷𝑆/𝐿
For Linear Region
𝐼 𝐷𝑆 = 𝜇𝐶0𝑋𝐿 𝑊
(𝑉𝐺𝑆 − 𝑉 𝑇 − 2𝑉𝐷𝑆)𝑉 -----
Where VDS< VGS-VT , For Linear (9) 𝐷𝑆
Region.
Where β =μC0X W/L
𝐼 = 𝛽 (𝑉 − 𝑉 − 𝑉𝐷𝑆)𝑉 -----------(10)
𝐷𝑆 𝐺𝑆 𝑇 2 𝐷𝑆
If Vds > Vdsat = (VGS-VT), the channel is no longer inverted in the vicinity of the drain; We
say it is pinched off. Beyond this point, called the drain saturation voltage, increasing the
drain voltage has no further effect on current. Substituting
Vds = Vdsat in Eq (10) at this point of maximum current
𝐼𝐷𝑆 = 𝛽 (𝑉 − 𝑉 )^2--------------(11)
𝐺𝑆 2 𝑇
For Saturation Region Vds>

(VGS-VT),
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Summary of IDS for NMOS
Transistor
Substitute the different values of VGS as a constant and obtain graph between VDS and ID,
We will get NMOS I-V Characteristics
Fig 13. NMOS I-V Characteristics
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However, these holes cannot contribute to the drain current since thereversed-
biased p-n diode between the drain and the substrate blocks any flow of holes into the
drain. Instead the current reaches its maximum value and maintains that value for higher
drain-to-source voltages. A depletion layer located at the drain end of the gate
accommodates the additional drain-to-source voltage. This behavior is referred to as drain
current saturation.
Drain current saturation therefore occurs when the drain-to-source voltage equals
the gate-to-source voltage minus the threshold voltage. The value of the saturated drain
current, ID,sat. is then given by the following equation:
ID,Sat=μCox.(W/L).(VGs-Vt)2/2 for VDS>VGS-VT
The quadratic model explains the typical current-voltage characteristics of a

MOSFET, which are normally plotted for different gate-to-source voltages. The saturation
occurs to the right of the dotted line which is given by ID = m Cox W/L V 2DS
.
Fig 14. : Current-Voltage characteristics of an n-type MOSFET as obtained with the quadratic
model.
The dotted line separates the quadratic region of operation on the left from the
saturation region on the right.
For negative drain-source voltages, the transistor is in the quadratic regime and is
described. However, it is possible to forward bias the drain-bulk p-n junction. A complete
circuit model should therefore also include the p-n diodes between the source, the drain
and the substrate.
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For negative drain-source voltages, the transistor is in the quadratic regime. However, it is
possible to forward bias the drain-bulk p-n junction. A complete circuit model should
therefore also include the p-n diodes between the source, the drain and the substrate.
SMALL SIGNAL AC CHARACTERISTICS

We now use the quadratic model used to calculate some of the small signal
parameters, namely the transconductance, gm and the output conductance, gd. The
transconductance quantifies the drain current variation with a gate-source voltage
variation while keeping the drain-source voltage constant, or:
(1)
The transconductance in the quadratic region is given by:
(2)
which is proportional to the drain-source voltage for VDS < VGS - VT. In saturation, the
transconductance is constant and equals:
(3)
The output conductance quantifies the drain current variation with a drain-source
voltage variation while keeping the gate-source voltage constant, or:
(4)
The output conductance in the quadratic region decreases with increasing drain- source
voltage:
(5)
and becomes zero as the device is operated in the

saturated region:
(6)
32
Example Calculate the drain current of a silicon nMOSFET with VT = 1 V, W
1 = 10 mm, L = 1 mm and tox = 20 nm. The device is biased with
VGS = 3 V and VDS = 5 V. Use the quadratic model, a surface
obility of 300 cm2/V-s and set VBS = 0 V.Also calculate the
transconductance at VGS = 3 V and VDS = 5 V and compare it to
the output conductance at VGS = 3 V and VDS
= 0 V.
Solution The MOSFET is biased in saturation since VDS > VGS - VT.
Therefore the drain current equals:
The transconductance equals:
and the output conductance equals:
33
6.3.3 C V CHARACTERISTICS OF MOSFET:
Fig 15. C–V profile for a bulk MOSFET with different oxide thickness.
The leftmost part of the curve corresponds to accumulation. The valley in the middle
corresponds to depletion. The curve on the right corresponds to inversion.
Derivation of MOSFET Threshold Voltage from the MOS Capacitor

Threshold voltage is the voltage applied between gate and source of a MOSFET that
is needed to turn the device on for linear and saturation regions of operation. The
following analysis is for determining the threshold voltage of an N- channel MOSFET (also
called an N-MOSFET). The analysis is performed with a MOS capacitor like the one shown
below.
Fig 16. Structure of MOS Capacitor

Top layer is N-type polysilicon or metal. For this derivation we will assume it is heavily
doped N-type polysilicon with doping ND • S1O2 (oxide) insulation sandwiched
between two conductors • The bottom layer is P-type semiconductor of doping NA

Vt=Vt-mos +Vfb
34
Vt-mos is the ideal threshold voltage (no work function difference between the gate and
substrate materials) and Vfb is the flatband voltage.
Vt-mos=2Φb+Qb/Cox where Cox= eox/tox
Φb=kT/q ln(NA/ni) where kT/q=.26mV at room temperature (300οK) k=1.38x10-23

J/οK Boltzmann‘s constant T is the temperature in kelvins
q=1.602x10-19 Coulombs, the electron charge
NA=density of doped carriers (given)
ni=1.45x1010cm3 carriers in intrinsic silicon
eox=3.9x8.85x10-14 F/cm2, tox is given Vsb
is substrate bias (given) Qb=√(2*esi *q*
NA*(2*Φb+|Vsb|))
where esi=1.06x10-12 F/cm permittivity of silicon The
complete formula so far where Vsb = 0:
Vt-mos=2 kT/q ln(NA/ni) + √(2esiqNA2 Φb)*1/(eox/tox) (this is Vt0 in formula 2.30 3rd
ed. Also, this γ is Qb/Cox and Φs=2Φb)
Note: Vt-mos is positive for nMOS and negative for pMOS.
The flat band formulas:

Vfb=Φms-Qfc/Cox where,
Φms is work function difference ‗twn gate and wafer Qfc
is a fixed charge for surface states (given)
Φms=-(Eg/2±Φb) where, sign is determine by the following rule:

+ if device is an nMOS
- if device is a pMOS
Eg is band gap energy of silicon… 1.1eV or…
Eg=(1.16-.704x10-3(T2/(T+1108)) (for silicon band gap energy at other than room
temp)
35
Complete flatband formula:
Vfb= -((1.16-.704x10-3(T2/(T+1108)))/2± kT/q ln(NA/ni))-Qfc/(eox/tox)
The entire Vt formula:
Vt=2 kT/q ln(NA/ni) + √(2esiqNA2 Φb)/(eox/tox)-((1.16-.704x10-
3(T2/(T+1108)))/2± kT/q ln(NA/ni))-Qfc/(eox/tox)
Threshold voltage calculation

The threshold voltage equals the sum of the flatband
voltage, twice the bulk
potential and the voltage across the oxide due to the depletion layer
charge, or:
(1)
where the flat band voltage, VFB, is given by:
(2)
With
(
3
)
And
The threshold voltage of a p-type MOSFET with an n-type substrate is obtained using the
following equations:
(4)
where the flatband voltage, VFB, is given by:
(5)
With
(6)
36
And
The threshold voltage dependence on the doping density is illustrated with for
both n-type and p-type MOSFETs with an aluminum gate metal.
Fig 17. Threshold voltage of n-type (upper curve) and p-type (lower curve)
MOSFETs versus substrate doping density.
The threshold of both types of devices is slightly negative at low doping
densities and differs by 4 times the absolute value of the bulk potential. The threshold of
nMOSFETs increases with doping while the threshold of pMOSFETs decreases with doping
in the same way. A variation of the flatband voltage due to oxide charge will cause a
reduction of both threshold voltages if the charge is positive and an increase if the charge
is negative.
The substrate bias effect

The voltage applied to the back contact affects the threshold voltage of a
MOSFET. The voltage difference between the source and the bulk, VBS changes the width
of the depletion layer and therefore also the voltage across the oxide due to the change of
the charge in the depletion region. This results in a modified expression for the threshold
voltage, as given by:
(8)
The threshold difference due to an applied source-bulk voltage can

therefore be expressed by:
(9)
Where g is the body effect parameter given by:
(10)
37
The variation of the threshold voltage with the applied bulk-to-source voltage
can be observed by plotting the transfer curve for different bulk-to-source voltages. The
expected characteristics, as calculated using the quadratic model and the variable depletion
layer model
Figure 18. Square root of ID versus the gate-source voltage as calculated using the quadratic model
(upper curves) and the variable depletion layer model (lower curves).
First, we observe that the threshold shift is the same for both models. For a
device biased at the threshold voltage, drain saturation is obtained at zero drain- to-source
voltage so that the depletion layer width is constant along the channel. As the drain-source
voltage at saturation is increased, there is an increasing difference between the drain
current as calculated with each model. The difference however reduces as a more negative
bulk-source voltage is applied. This is due to the larger depletion layer width, which reduces
the relative variation of the depletion layer charge along the channel.
Figure 19. Schematic of a CMOS inverter as processed on a

p-type silicon substrate.
38
Example 2
Calculate the threshold voltage of a silicon nMOSFET when applying a substrate
voltage, VBS = 0, -2.5, -5, -7.5 and -10 V. The capacitor has a substrate doping Na
= 1017 cm-3, a 20 nm thick oxide (eox = 3.9 e0) and an aluminum gate (FM = 4.1
V). Assume there is no fixed charge in the oxide or at the oxide-silicon interface.
Solution
The threshold voltage at VBS = -2.5 V equals:
Where the flatband voltage without substrate bias, VT0, The body effect parameter was
obtained from:
The threshold voltages for the different substrate voltages are listed in the table below.
3. C V CHARACTERISTICS OF MOSFET:
The gate of an MOS transistor is a good capacitor. Indeed, its capacitance is necessary to
attract charge to invert the channel. So high gate capacitance is required to obtain high
Ids. The gate capacitor can be viewed as a parallel plate capacitor with the gate on top and
channel on bottom with the thin oxide dielectric between. Therefore, the capacitance is
Cg=Cox W L
The bottom plate of the capacitor is the channel, which is not one of the transistor‘s
terminals. When the transistor is on, the channel extends from the source
39
Thus, we often approximate the gate capacitance as terminating at the source and call the
capacitance Cgs. Most transistors used in logic are of minimum manufacturable length
because this results in greatest speed and lowest dynamic power consumption. Thus,
taking this minimum L as a constant for a particular process, we can define
Cg= C permicron W
Where C permicron = COX L = (εox/ tox )L
In addition to the gate, the source and drain also have capacitances. These
capacitances are not fundamental to operation of the devices, but do impact circuit
performance and hence are called parasitic capacitors. The source and drain capacitances
arise from the p–n junctions between the source or drain diffusion and the body and hence
are also called diffusion capacitance Csb and Cdb .
A depletion region with no free carriers forms along the junction. The depletion
region acts as an insulator between the conducting p- and n-type regions, creating
capacitance across the junction. The capacitance of these junctions depends on the area
and perimeter of the source and drain diffusion, the depth of the diffusion, the doping
levels, and the voltage.
Fig 20. MOS Capacitance Model
40
Detailed MOS Gate Capacitance Model:
The MOS gate sits above the channel and may partially overlap the source and drain
diffusion areas. Therefore, the gate capacitance has two components: the intrinsic
capacitance Cgc (over the channel) and the overlap capacitances Cgol (to the source and
drain).
The intrinsic capacitance was approximated as a simple parallel plate in with

capacitance C0 = WLCox. However, the bottom plate of the capacitor depends on the mode
of operation of the transistor. The intrinsic capacitance has three components representing
the different terminals connected to the bottom plate: Cgb (gate-to- body), Cgs (gate-to-
source), and Cgd (gate-to-drain). Figure 2.9(a) plots capacitance vs. Vgs in the cutoff region
and for small Vds, while 2.9(b) plots capacitance vs. Vds in the linear and saturation regions
Fig 21. (a) C vs Vgs at Cutoff (b) C vs Vgs at Linear and

saturation
Cutoff region: When the transistor is OFF (Vgs < Vt), the channel is not inverted and
charge on the gate is matched with opposite charge from the body. This is called Cgb, the
gate-to-body capacitance. For negative Vgs, the transistor is in accumulation and Cgb =
C0.
Linear: When Vgs > Vt, the channel inverts and again serves as a good conductive
bottom plate. However, the channel is connected to the source and drain, rather than the
body, so Cgb drops to 0. At low values of Vds, the channel charge is roughly shared
between source and drain, so Cgs = Cgd = C0/2.
41
Saturation. At Vds > Vdsat, the transistor saturates and the channel pinches off. At this
point, all the intrinsic capacitance is to the source. Because of pinchoff, the capacitance in
saturation reduces to Cgs = 2/3 C0 for an ideal transistor.
Table: Approximation for intrinsic MOS gate capacitance
Overlap capacitance:
The gate overlaps the source and drain in a real device and also has fringing fields
terminating on the source and drain. This leads to additional overlap capacitances. These
capacitances are proportional to the width of the transistor. They should be added to the
intrinsic gate capacitance to find the total.
C =C W
gsol (overlap ) gsol Cgdol
(overlap ) =C gdol W
Detailed MOS Diffusion Capacitance Model:

The p–n junction between the source diffusion and the body contributes parasitic
capacitance across the depletion region.
The capacitance depends on both the area AS and sidewall perimeter PS of
the
source diffusion region.
The area is AS
PS = 2W +2D.
= WD. The
perimeter is
Fig 22. Diffusion Region Geometry
42
42
The total source parasitic capacitance is Csb =AS ×C
jbs + PS × C jbssw
Because the depletion region thickness depends on the bias conditions, these parasitics are
nonlinear. The area junction capacitance term is
CJ is the junction capacitance at zero bias MJ

is the junction grading coefficient
Ψ0 = built-in potential that depends on
doping levels.
The built-in potential that depends on doping

levels.
VT is the thermal voltage It has a value equal to kT/q (26 mV at room temperature), where
k = 1.380 × 10^–23 J/K is Boltzmann‘s constant, T is absolute temperature (300 K at room
temperature), and q = 1.602 × 10^–19 C is the charge of an electron. NA and ND are the
doping levels of the body and source diffusion region. ni is the intrinsic carrier
concentration in undoped silicon and has a value of 1.45 × 10^10 cm^–3 at 300 K.
The sidewall capacitance term is of a similar form but uses different coefficients.
43
43
6.3.4. CMOS Inverter DC Transfer Characteristics
Voltage Transfer Characteristics
The voltage transfer characteristic (VTC) gives the response of the inverter
circuit, Vout, to specific input voltages, Vin. It is a figure of merit for the static behavior of
the inverter. The gate-source voltage, Vgs of the n-channel MOSFET is equal to ,
Vin => Vgsn=Vin

while the gate-source voltage of the p-
channel MOSFET calculates as
Vgsp=Vin-Vdd
and the drain-source voltage, Vdsn of
the nMOSFET can be expressed as
Vdsn=Vout and
that of the pMOSFET can be expressed
as
Vdsp=Vout-Vdd
The drain currents of both transistors must be equal. Therefore, the

intersection of the output characteristics of both transistors for each input voltage, Vin give
the output voltage, Vout. The circles mark five points of the voltage transfer characteristics.
Table: Relationship between voltages for the three regions of operation of a CMOS
inverter
44
Fig 23. CMOS Inverter
A complementary CMOS inverter is implemented as the series connection of a

p-device and an n-device, as shown in Figure 18. Note that the source and the substrate
(body) of the p -device is tied to the VDD rail, while the source and the substrate of the n-
device are connected to the ground bus. Thus, the devices do not suffer from any body
effect. To derive the DC transfer characteristics for the CMOS inverter, which depicts the
variation of the output voltage (Vout) as a function of the input voltage (Vin), one can
identify five following regions of operation for the n -transistor and p -transistor.
Fig 24. A CMOS inverter shown with substrate Connections
45
Vtn and Vtp denote the threshold voltages of the n and p-devices respectively. The
following voltages at the gate and the drain of the two devices (relative to their respective
sources) are all referred with respect to the ground (or VSS), which is the substrate voltage
of the n -device, namely
Vgsn =Vin , Vdsn =Vout, Vgsp =Vin -VDD , and Vdsp =Vout -VDD .
The voltage transfer characteristic of the CMOS inverter is now derived with reference to
the following five regions of operation :
Fig 25. VTC characteristics of CMOS Inverter
Region 1(A) : the input voltage is in the range . In this condition, the n -transistor is off,
while the p -transistor is in linear region (as-VDD< Vgsp < Vtn).
No actual current flows until Vin crosses Vtn. The operating point of the p -transistor
moves from higher to lower values of currents in linear zone. The output voltage is
given by , Vout=VDD.
46
Region 2 (B): the input voltage is in the
range Vtn ≤ Vin ≤ Vinv . The upper limit of
Vin is Vinv , the logic threshold voltage of
the inverter. The logic threshold voltage or
the switching point voltage of an inverter
denotes the boundary of "logic 1" and "logic
0". It is the output voltage at which Vin =
Vout . In this region, the n-transistor moves
into saturation, while the p- transistor
remains in linear region. The total current
through the inverter increases, and the
output voltage tends to drop fast. Fig 26
Region 3 (C): In this region, Vin =Vinv Both the transistors are in saturation, the drain
current attains a maximum value, and the output voltage falls rapidly. The inverter
exhibits gain. But this region is inherently unstable. As both the transistors are in
saturation, equating their currents, one gets (as Vgsn=Vinv, Vgsp=Vinv-VDD)
Solving for the logic threshold voltage Vinv , one gets`
47
Note that if βn= βp and Vin=-Vtp , then Vinv =0.5 VDD or (VDD/2).
Region 4 (D): In this region, Vinv < Vin≤ VDD-|Vtp| . As the input voltage Vin is increased
beyond Vinv , the n -transistor leaves saturation region and enters linear region, while the
p -transistor continues in saturation. The magnitude of both the drain current and the
output voltage drops.
Region 5 (E): In this region, VDD-|Vtp| ≤ Vin ≤ VDD . At this point, the p -transistor
is turned off, and the n -transistor is in linear region, drawing a small current, which falls to
zero as Vin increases beyond VDD -| Vtp|, since the p -transistor turns off the current path.
The output in this region is Vout=0.
.
As may be seen from the transfer curve in Figure19, the transition from "logic 1" state
(represented by regions 1 and 2) to ―logic 0ǁ state (represented by regions 4 and 5) is
quite steep. This characteristic guarantees maximum noise immunity.
Table: Summary of CMOS inverter operation
48
β ratio Effects:
□ We have seen that for βp = βn, the inverter threshold voltage Vinv is VDD/2.
□ Inverters with different beta ratios r = βp / βn are called skewed inverters. If r > 1,
the inverter is HI-skewed. If r < 1, the inverter is LO-skewed. If r = 1, the inverter

has normal skew or is unskewed.
🡪A HI-skew inverter has a stronger pMOS transistor. Therefore, if the input is VDD
/2, we
would expect the output will be greater than VDD /2. (Higher Switching Threshold)
🡪A LO-skew inverter has a weaker pMOS transistor and thus a lower switching
threshold.
Fig 27. Transfer characteristics of Skewed Inverter
□ As the beta ratio is changed, the switching threshold moves.

□ However, the output voltage transition remains sharp.
□ Gates are usually skewed by adjusting the widths of transistors while maintaining
minimum length for speed.
49
Noise margin:
🡪Noise margin is closely related to the DC voltage characteristics . This parameter allows
you to determine the allowable noise voltage on the input of a gate so that the output will
not be corrupted.
🡪The specification most commonly used to describe noise margin (or noise immunity) uses
two parameters:
□ The LOW noise margin, NML, and the HIGH noise margin, NMH.
🡪NML is defined as the difference in maximum LOW input voltage recognized by the
receiving gate and the maximum LOW output voltage produced by the driving gate.
NML =VIL –VOL NMH

=VOH –VIH
Fig 28. Noise Margin Definitions
where
VIH = minimum HIGH input voltage VIL = maximum LOW input
voltage VOH= minimum HIGH output voltage VOL = maximum LOW
output voltage
50
Figure 22 illustrates the above four definitions. Ideally, if one desires to have VIH
=VIL , and VOL =VOH in the middle of the logic swing, then the switching of states should
be abtrupt, which in turn requires very high gain in the transition region. To calculate VIL ,
the inverter is supposed to be in region 2 (referring to Figure 2.12) of operation, where the
p -transistor is in linear zone while the n -transistor is in saturation. The parameter VIL is
found out by considering the unity gain point on the inverter transfer characteristic where
the output makes a transition from VOH . Similarly, the parameter VIH is found by
considering the unity gain point at the VOL end of the characteristic.
If the noise margins NMH or NML are reduced to a low value, then the gate
may be susceptible to switching noise that may be present at the inputs. The net effect of
noise sources and noise margins on cascaded gates must be considered in
estimating the overall noise immunity of a particular system. Not infrequently,
noise margins are compromised to improve speed.
CMOS inverter as an amplifier : In the region 3 (referring to Figure 2.12) of operation,
the inverter actually acts as an analog amplifier where both the transistors are in
saturation. The input-output behaviour of the inverter in this region is given by Vout = AVin
where A is the stage gain given by

A = (gmn + gmp ) (rdsn || rdsp )
51
Note that the small-signal characteristics, namely transconductance gm is defined as
and the output resistance rds is given by
Note that the gain A is dependent on the process and the transistors used in the circuit. It
can be increased by increasing the length of the transistors to improve the output
resistance. However, speed and bandwidth of the amplifier suffer as a result.
6.3.5. NON LINEAR I-V CHARACTERISTICS:

(or) NON IDEAL I-V EFFECTS
As the technology scaling reaches channel
lengths less than a micron (L<1µ),
second order effects, that were ignored in devices with long channel length (L>1µ),
become very important. MOSFET‗s owning those dimensions are called ―short channel
devicesǁ. The main second order effects are: Velocity Saturation, Channel
length
modulation, Body effect/Threshold Voltage Variations, sub-threshold leakage, Hot Carrier
Effects, etc.,
5.1 Channel length modulation

Channel length modulation in a MOSFET is caused by the increase of the
depletion layer width at the drain as the drain voltage is increased. This leads to a shorter
channel length and an increased drain current. Ideally, Ids is independent of Vds for a
transistor in saturation, making the transistor a perfect current source.
The p–n junction between the drain and body forms a depletion region with a width Ld that
increases with Vdb. The depletion region effectively shortens the channel length to Leff= L-
Ld
Fig 29. Leakage Current Path
52
To avoid introducing the body voltage into our calculations, assume the source voltage is
close to the body voltage so Vdb = Vds. Hence, increasing Vds decreases the effective
channel length. Shorter channel length results in higher current; thus, Ids increases with
Vds in saturation. Saturation region Ids equation can be multiplying with by a factor of (1 +
Vds / VA), where VA is called the Early voltage
Channel length modulation is very important to analog designers because it reduces the
gain of amplifiers. It is generally unimportant for qualitatively understanding the behavior
of digital circuits.
2. Drain induced barrier lowering

The drain voltage Vds creates an electric field that affects the threshold
voltage. This drain-induced barrier lowering (DIBL) effect is especially pronounced in short-
channel transistors. It can be modeled as
Vt=Vt0-ƞVds
where ƞ is the DIBL coefficient
Drain-induced barrier lowering causes Ids to increase with Vds in saturation, in much
the same way as channel length modulation does.
3. Punch through
Punch through in a MOSFET is an extreme case of channel length
modulation
where the depletion layers around the drain and source regions merge into a single
depletion region. The field underneath the gate then becomes strongly dependent on the
drain-source voltage, as is the drain current. Punch through causes a rapidly increasing
current with increasing drain-source voltage. This effect is undesirable as it increases the
output conductance and limits the maximum operating voltage of the device.
53
5.4 Subthreshold Leakage Current
When the gate voltage is high, the transistor is strongly ON. When the gate falls below Vt ,
the exponential decline in current appears as a straight line on the logarithmic scale. This
regime of Vgs < Vt is called weak inversion. The subthreshold leakage current increases
significantly with Vds because of drain-induced barrier lowering.
Fig 30. I-V characteristics of a 65 nm nMOS transistor
The inverse of the slope of this line is called the subthreshold slope,
S
n is a process-dependent term range of 1.3–1.7 for CMOS processes
54
5.5 Avalanche breakdown and parasitic bipolar action/Hot Electrons/Impact
Ionization
During the last decades transistors dimensions were scaled down, but not the
power supply. The resulting increase in the electric field strength causes an increasing
energy of the electrons. Some electrons are able to leave the silicon and tunnel into the
gate oxide. Such electrons are called ―Hot carriersǁ. Electrons trapped in the oxide change
the VT of the transistors. This leads to a long term reliability problem. For an electron to
become hot an electric field of 104 V/cm is necessary. This condition is easily met with
channel lengths below 1µm.
As the electric field in the channel is increased, avalanche breakdown occurs
in the channel at the drain. This avalanche breakdown increases the current as in a p-n
diode. In addition, there is parasitic bipolar action taking place. Holes
generated by the avalanche breakdown move from drain to source
underneath the inversion layer. This hole current forward biases the source-bulk p-n diode
so that now also electrons are injected as minority carriers into the p-type substrate
underneath the inversion layer. These electrons arrive at the drain and again create more
electron-hole pairs through avalanche multiplication. The positive feedback between the
avalanche breakdown and the parasitic bipolar action results in breakdown at lower drain
voltage.
5.6 Velocity saturation and Mobility Degradation:

Each carrier in the channel is accelerated to an average velocity v,
proportional to the
lateral electric field, i.e., the field between source and drain. The constant of
proportionality μ is called the mobility.
v = μE
Lateral electric field Elat = Vds /L between source and drain.
Mobility degradation can be modeled by replacing μ with a smaller μeff that is
a function of Vgs. At low fields, the velocity increases linearly with the field. The slope is
the mobility, μeff. At fields above a critical level, Ec , the velocity levels out at vsat, which is
approximately 10^7 cm/s for electrons and 8 × 10^6 cm/s for holes.
55
Fig 31a. velocity vs. electric field at 300 K
Reasonably well with the following expression
where, by continuity, the critical electric field

is
The critical voltage Vc is the drain-source voltage at which the critical effective field
is reached: Vc = Ec L.
56
5.7 Oxide Breakdown/Gate Tunneling
As the gate-oxide is scaled down, breakdown of the oxide and oxide reliability
becomes more of a concern. Higher fields in the oxide increase the tunneling of carriers
from the channel into the oxide. These carriers slowly degrade the quality of the oxide and
lead over time to failure of the oxide. This effect is referred to as time dependent
destructive breakdown (TDDB).
A simple reduction of the power supply voltage has been used to eliminate
this effect. However as gate oxides approach a thickness of 1.5 - 3 nm, carrier tunneling
becomes less dependent on the applied electric field so that this Oxides other than silicon
dioxide have been considered as alternate oxides and are typically referred to as high-k
dielectrics. These oxides have a larger dielectric constant so that the same gate
capacitance can be obtained with a thicker oxide. The challenge is to obtain the same
stability, reliability and breakdown voltage as silicon dioxide. Oxides of interest include
Al2O3, ZrO and TiO.
70
57
5.8 Body Effect/Threshold Voltage Variations
For a long channel N-MOS transistor the threshold Voltage is given for:
Eq. states that the threshold Voltage is only a function of the technology and
applied body bias V SB. If VSB =0, then VT = VT0 🡪 ideal threshold voltage. As devices are
stacked one on top of the other, VSB ≠ 0. For short channel devices this model becomes
inaccurate and threshold voltage becomes function of L, W and VDS. This is modeled by
the body effect parameter γ.
Fig 31c) Threshold Variations
6.3.6. Pass Transistor and transmission gate logics
A conceptually simple approach for implementing logic functions utilizes series and
parallel combinations of switches that are controlled by input logic variables to connect the
input and output nodes. Each of the switches can be implemented either by a single NMOS
transistor or by a pair of complementary MOS transistors connected in what is known as
the CMOS transmission-gate configuration The pass transistor logic reduces the number of
transistors required to implement the logic. NMOS transistors pass a strong 0 but a weak
1(threshold voltage drop. High =Vdd-Vtn) and PMOS transistors pass a strong 1 but a weak
0(threshold voltage drop. Low= Vtp)
Fig 32. a) Pass Transistor b) Transmission Gate
58
Fig 32. c) Pass Transistor of pull up and pull down network
Great improvements in static and dynamic performance are obtained when the
switches implemented with CMOS transmission gates. The transmission gate utilizes a pair
of complementary transistors connected in parallel. It acts as an excellent switch, providing
bidirectional current flow (Fig. 32d ), and it exhibits an on resistance that remains almost
constant for wide ranges of input voltage. These characteristics make the transmission gate
not only an excellent switch in digital applications but also an excellent analog switch in
such applications data converters and switched-capacitor filters.
Fig 32. d) Transmission gate as switch
59
In the transmission gate shown, when C is high, both NMOS and PMOS are
conducting hence switch is closed. Therefore, conduction path between left and right sides
exist.When C is low, then the MOSFETs are cutoff and switch is open. Therefore, there is
no direct relationship between A and B. Output is in high impedance state, Z .Figure below
shows the symbol of transmission gate controlled by switching signals X and X* that are
applied to the gates of NMOS and PMOS respectively.
Fig 32. e) Transmission gate symbol f)Transmission Gate function table
6.3.7. CMOS SCALING AND ITS LIMITATIONS:

CMOS transistors have been scaling exponentially in the past two decades and the
intrinsic device performance has followed a commensurate scaling trend. Prior to the
90-nm node, mere shrinking of the device dimensions, following Dennard‘s scaling theory,
was sufficient to guarantee increased device performance; beyond the 90-nm node, new
innovations were necessary to continue the historical performance scaling trend.
SCALING RULES
We in general want to simultaneously reduce gate delays, decrease power
dissipation, and increase packing density, while not exceeding a certain power density. The
place we start is with a reduction of the gate length, but we quickly find we must do more
than that or we get into trouble. For example, as the gate length is reduced, the oxide
thicknesses and the junction depths (of the sources and drains) must be reduced
proportionally to obtain good transistor characteristics. One is essentially maintaining a
long, thin geometry consistent with the gradual channel approximation, and this turns out
to be just what is needed to get good saturation (flat curves; small go) of the device output
(iD vs vDS) characteristics.Thus, if we reduce the minimum gate length, Lmin, by a factor of
s, we will also want to reduce the gate oxide, tox, by the same factor.
60
To increase the packing density further, we also reduce the gate width, W, by the
same factor: Lmin → Lmin/s W → W/s tox → tox/s With these changes we find that our
gate delay, average power, device density, and power density change as follows: τ GD
→
τGD/s2
Pave → s Pave
Device Density → s2 Device Density
Clearly this is a formula Pdensity max → s3 because

for disaster Pdensity max the power density will increase
dramatically if we only scale dimensions. We either have to develop much better ways to
get the heat out of an IC chip and package, so we can tolerate a higher power density, or
we have to change more than the dimensions. Packaging and heat sinking have been
improved, to be sure, but the big gain comes from scaling the voltages as well as the
dimensions. If we scale the supply and threshold voltages as follows:
VDD → VDD/s VT → VT/s then we find: τGD → τGD/s Pave → Pave/s2 Device
Density
→ s2 Device Density Pdensity max → Pdensity max
This is clearly a much better situation. At the same time it must be noted that it
is not as easy to scale the voltages as it might at first seem and it has taken longer to do
so than it has to reduce dimensions because of a number of factors. The control over the
threshold voltage must be improved which places more demands on the process line, and
the noise margins decrease by a factor 1/s so noise sources on the chip must be reduced.
Also, supply voltages are not totally arbitrary since they must be tied to standard battery
cells, which come in increments of roughly 1 Volt (they range from 1.1 to 0.9 V over their
useful lifetime). Early bipolar and MOSFET logic used VDD's of 5 V, but this has recently
been reduced to 3, 2, and, even, 1 V.
Fig 33. MOSFET after Scaling
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Table: Types of Scaling
Full Scaling (Constant Electrical Field Scaling):
■ In this ideal model, voltages and dimensions are scaled by the same factor S.
■ The goal is to keep the electrical field patterns in the scaled device identical to
those in the original device. Keeping the electrical fields constant ensures the
physical integrity of the device and avoids breakdown or other secondary
effects.
■ This scaling leads to greater device density (Area), higher performance
(Intrinsic Delay), and reduced power consumption (P).
Fixed-Voltage Scaling:
■ Voltages have not been scaled down along with feature sizes, and designers
adhere to well-defined standards for supply voltages and signal levels.
■ 5 V was the de facto standard for all digital components up to the
early 1990s, and a fixed-voltage scaling model was followed.

■ Only with the introduction of the 0.5 mm CMOS technology did new standards
such as 3.3 V and 2.5 V make an inroad.
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General Scaling:
● General scaling model is needed, where dimensions and voltages are scaled
independently.
● Device dimensions are scaled by a factor S, while voltages are reduced by a factor
● U. When the voltage is held constant, U = 1, and the scaling model reduces to the
fixed-voltage model.
8. Propagation Delay of CMOS inverter

The propagation delay of a logic gate e.g. inverter is the difference in
time
(calculated at 50% of input-output transition), when output switches, after application of
input.
Fig 34. propagation delay
■Propagation delay time, tpd = maximum time from the input crossing 50% to the
output crossing 50%.

■Contamination delay time, tcd = minimum time from the input crossing 50% to the
output crossing 50%.

■Rise time, tr = time for a waveform to rise from 20% to 80% of its steady-state
value.
■Fall time, tf = time for a waveform to fall from 80% to 20% of its steady-state
value.
■Edge rate, trf = (tr + tf )/2
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Now, in order to find the propagation delay, we need a model that matches the delay
of inverter. As we have seen above, the switching behaviour of CMOS inverter could be
modeled as a resistance Ron with a capacitor CL, a simple first order analysis of RC network
will help us to model the propagation delay.

First order RC network
Consider the following RC network to which we apply a step input.
Fig 36.a RC network b) Transient response
Our aim is to find ‗t‘ at Vdd / 2.

Vout = (1-e-t/τ) Vdd, where τ = RC = time constant.
Substituting ‗Vout‘ equal to Vdd/2, and ‗t‘ equal to ‗tp‘ in above equation, we get the
following :
Vdd/2 = (1-e-tp/τ) Vdd Therefore, tp
= ln(2) τ = 0.69τ
Hence, tp = 0.69RC
Hence, a CMOS inverter can be modeled as an RC network, where R =
Average ‗ON‘ resistance of transistor
C = Output Capacitance
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RC Delay Model
RC delay models approximate the nonlinear transistor I-V and C-V characteristics
with an average resistance and capacitance over the switching range of the gate.
Effective Resistance: The RC delay model treats a transistor as a switch in series with a
resistor. The effective resistance is the ratio of Vds to Ids averaged across the switching
interval of interest.
A unit nMOS transistor is defined to have effective resistance R.An nMOS transistor
of k times unit width has resistance R/k.The pMOS transistor has approximately twice the
resistance of the nMOS transistor because holes have lower mobility than electrons.
Each transistor also has gate and diffusion capacitance. We define C to be the gate
capacitance of a unit transistor of either flavor. A transistor of k times unit width has
capacitance kC.
Fig 37. Equivalent RC Network for nMoS ,pMoS transistor
Our aim is to find ‗t‘ at Vdd / 2
Vout = (1-e-t/τ) Vdd, where τ = RC = time constant.
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Elmore Delay Model :
As we know that simple RC model provides general approximation of timing
behavior of digital integrated circuits. In order to improve accuracy of RC model, Elmore
delay model is used. Here, the RC segments made up of series resistance RN and a
capacitance CN are created.
Consider RC network shown in Figure below connected in the form of RC segments.
Fig 38. RC Tree Network
Now, here the Elmore delay at node 7 is calculated as,

D7τ= R1 C1 + R1 C2 + R1 C3 + R1 C4 + R1 C5 + (R1 + R6) C6 + (R1 + R6 + R7) C7
+ (R1 + R6 + R7) C8
In the same manner, the Elmore delay at node 5 is calculated as,

D5τ= R1 C1 + (R1 + R2) C2 + (R1 + R2) C3 + (R1 + R2 + R4) C4 + (R1 + R2 + R4
+ R5) C5 + R1 C6 + R1 C7 +
R1 C8
ELMORE DELAY FOR RC LADDER NETWORK
Delay from node i to node m
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Fig 39. Switch Delay Model
For an invertor, rise delay,tr=0.69RpC (pmos on) ; Fall delay,tf=0.69RnC (nmos on)
For a 2-input NAND gate, rise delay, tr=0.69([Rp.Rp]/[Rp+Rp])C (since 2 pmos in parallel🡪
2 Rp in parallel =0.69[Rp2/2Rp]C =0.69(Rp/2)C

Fall delay, tf=0.69(Rn+Rn)C=0.69(2Rn)C (since 2 nmos are in series🡪 2Rn are in series)
For a 2-input NOR gate,
rise delay, tr=0.69(Rp+Rp)C =0.69(2Rp)C (since 2 pmos in series🡪 2 Rp in series)
Fall delay, tf=0.69(Rn2/2Rn)C =0.69(Rn/2)C (since 2 nmos are in parallel🡪 2Rn
are in parallel)
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6.3.8. LINEAR DELAY MODEL-LOGICAL EFFORT
The method of logical effort, a term coined by Ivan Sutherland and Bob
Sproull in 1991, is a straightforward technique used to estimate delay in a CMOS circuit.
Used properly, it can aid in selection of gates for a given function (including the number of
stages necessary) and sizing gates to achieve the minimum delay possible for a circuit.
Derivation of delay in a logic gate

Delay is expressed in terms of a basic delay unit, τ = 3RC, the delay of an
inverter driving an identical inverter with no parasitic capacitance; the unitless number
associated with this is known as the normalized delay. (Some authors prefer define the
basic delay unit as the fan out of 4 delay—the delay of one inverter driving 4 identical
inverters). The absolute delay is then simply defined as the product of the
delay of the gate, d, and τ: normalized
d abs= d ⋅τ
In a typical 600-nm process τ is about 50 ps. For a 250-nm process,
τ is
about 20 ps. In modern 45 nm processes the delay is approximately 4 to 5 ps. The
normalized delay in a logic gate can be expressed as a summation of two primary terms:
normalized paraistic delay, p (which is an intrinsic delay of the gate and can be found by
considering the gate driving no load), and stage effort, f (which is dependent on the load
as described below). Consequently,
d=f+p
The stage effort is divided into two components: a logical effort, g, which is
the ratio of the input capacitance of a given gate to that of an inverter capable of
delivering the same output current (and hence is a constant for a particular class of gate
and can be described as capturing the intrinsic properties of the gate), and an electrical
effort, h, which is the ratio of the input capacitance of the load to that of the gate. Note
that "logical effort" does not take the load into account and hence we have the term
"electrical effort" which takes the load into account. The stage effort is then simply:
f=gh
Combining these equations yields a basic equation that models the
normalized delay through a single logic gate:
d=gh+p
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Procedure for calculating the logical effort of a single stage
CMOS inverters along the critical path are typically designed with a gamma equal to
2. In other words, the pmos of the inverter is designed with twice the width (and therefore
twice the capacitance) as the nmos of the inverter, in order to get roughly the same pmos
resistance as nmos resistance, in order to get roughly equal pull-up current and pull-down
current. Choose sizes for all transistors such that the output drive of the gate is equal to
the output drive of an inverter built from a size-2 PMOS and a size-1 NMOS.
The output drive of a gate is equal to the minimum – over all possible combinations
of inputs – of the output drive of the gate for that input.The output drive of a gate for a
given input is equal to the drive at its output node. The drive at a node is equal to the sum
of the drives of all transistors which are enabled and whose source or drain is in contact
with the node in question. A PMOS transistor is enabled when its gate voltage is 0. An
NMOS transistor is enabled when its gate voltage is 1.
Once sizes have been chosen, the logical effort of the output of the gate is the sum
of the widths of all transistors whose source or drain is in contact with the output node.
The logical effort of each input to the gate is the sum of the widths of all transistors whose
gate is in contact with that input node. The logical effort of the entire gate is the ratio of
its output logical effort to the sum of its input logical efforts.
Multistage logic networks

A major advantage of the method of logical effort is that it can quickly be extended
to circuits composed of multiple stages. The total normalized path delay D can be
expressed in terms of an overall path effort, F, and the path parasitic delay P (which is the
sum of the individual parasitic delays):
D=NF1/N+P
The path effort is expressed in terms of the path logical effort G (the product of the
individual logical efforts of the gates), and the path electrical effort H (the ratio of the
load of the path to its input capacitance).
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For paths where each gate drives only one additional gate (i.e. the next gate in the
path),However, for circuits that branch, an additional branching effort, b, needs to be taken
into account; it is the ratio of total capacitance being driven by the gate to the capacitance
on the path of interest: F=GH
This yields a path branching effort B which is the product of the individual
stage branching efforts; the total path effort is then
It can be seen that b = 1 for gates driving only one additional gate, fixing B = 1 and
causing the formula to reduce to the earlier non-branching version.
Minimum delay
It can be shown that in multistage logic networks, the minimum possible delay
along
a particular path can be achieved by designing the circuit such that the stage efforts
are equal. For a given combination of gates and a known load, B, G, and H are all fixed
causing F to be fixed; hence the individual gates should be sized such that the individual
stage efforts are
where N is the number of stages in the

circuit. Examples:Delay in an inverter
A CMOS inverter circuit.

By definition, the logical effort g of
an inverter is 1. If the inverter drives
an
equivalent inverter, the electrical effort h is also 1. The parasitic delay p of an
inverter is also 1 (this can be found by considering the Elmore Delay model of the inverter).
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Therefore, the total normalized delay of an inverter driving an equivalent
inverter is
Fig 40. a) Simple inverter b) 2 input NAND Gate c) The number indicates the transistor width
Delay in NAND and NOR gates

The logical effort of a two-input NAND gate is calculated to be g = 4/3 because a
NAND gate with input capacitance 4 can drive the same current as the inverter can, with
input capacitance 3. Similarly, the logical effort of a two-input NOR gate can be found to be
g = 5/3. Due to the lower logical effort, NAND gates are typically preferred to NOR gates.
For larger gates, the logical effort is as follows: Logical effort for inputs of static CMOS
gates, with gamma = 2
The normalised parasitic delay of NAND and NOR gates is equal to the number of inputs.
Therefore, the normalised delay of a two-input NAND gate driving an identical copy of
itself (such that the electrical effort is 1) is
and for a two-input NOR gate, the delay is
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6.3.9. Stick Diagrams
A transistor exists where a polysilicon stick crosses either an N
diffusion
stick (NMOS transistor) or a P diffusion stick (PMOS transistor).
Note that there is no difference in the construction of a transistor source and a

transistor drain. The source is determined as the source of conductors (electrons for
NMOS / holes for PMOS) when current flows through the channel. In some pass transistor
circuits, the source and drain may swap over during use.
Stick Diagram Colour Code
Yellow/Br
P diffusion : Metal1 : Blue
own
Magenta/
N Green Metal2 : Purple
diffusion :
Cyan/
Polysilicon : Red Metal3 : Turquoise
Contacts &
Taps : Black
VLSI design aims to translate circuit concepts onto silicon. Stick diagrams are a
means of capturing topography and layer information using simple diagrams.
diagrams convey layer information through colour codes (or monochromeStick
encoding). It
acts as an interface between symbolic circuit and the actual layout. It shows all
components/vias. It shows relative placement of components. It goes one step closer to
the layout. It helps plan the layout and routing. A stick diagram is a cartoon of a layout.
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Does not show
• Exact placement of components
• Transistor sizes
• Wire lengths, wire widths, tub boundaries.
• Any other low level details such as parasitics.
Rule 1. When two or more sticks‘ of the same type cross or touch each other that
represents electrical contact.
Rule 2. When two or more ‗sticks‘ of different type cross or touch each other
there is no electrical contact. (If electrical contact is needed we have to show
the connection explicitly).
Rule 3. When a poly crosses diffusion it represents a transistor.
Rule 4. In CMOS a demarcation line is drawn to avoid touching of p-diff with n-

diff. All pMOS must lie on one side of the line and all nMOS will have to be on the
other side.
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STICK DIAGRAM OF CMOS INVERTER
STICK DIAGRAM OF CMOS NOR GATE
2 Input NAND Gate :
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STICK DIAGRAM OF AN EXAMPLE FUNCTION
6.3.10. LAYOUT
Layout Design Rules
In VLSI design, as processes become more and more complex, need for the
designer to understand the intricacies of the fabrication process and interpret the
relations between the different photo masks is really troublesome. Therefore, a set of
layout rules, also called design rules, has been defined. They act as an interface or
communication link between the circuit designer and the process engineer during the
manufacturing phase.
The objective associated with layout rules is to obtain a circuit with optimum yield
(functional circuits versus non-functional circuits) in as small as area possible without
compromising reliability of the circuit. In addition, Design rules can be conservative or
aggressive, depending on whether yield or performance is desired. Generally, they are a
compromise between the two. Manufacturing processes have their inherent limitations in
accuracy. So the need of design rules arises due to manufacturing problems like
Photoresist shrinkage, tearing. Variations in material deposition, temperature and oxide
thickness. (a) Impurities. (b ) Variations across a wafer.
These lead to various problems like :

Transistor problems:
(i) Variations in threshold voltage: This may occur due to variations in oxide
thickness, ion-implantation and poly layer. Changes in source/drain diffusion overlap.
Variations in substrate.
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(ii)Wiring problems: Diffusion: There is variation in doping which results in variations in
resistance, capacitance. Poly, metal: Variations in height, width resulting in variations in
resistance, capacitance. Shorts and opens.
(iii )Oxide
problems:
(iv)Via problems:
Variations in height. Lack of planarity.
Via may not be cut all the way through. Undersize via has too much resistance. Via
may be too large and create short.To reduce these problems, the design rules specify to
the designer certain geometric constraints on the layout artwork so that the patterns on
the processed wafers will preserve the topology and geometry of the designs. This
consists of minimum-width and minimum-spacing constraints and requirements between
objects on the same or different layers. Apart from following a definite set of rules, design
rules also come by experience.
Types of Design Rules

The design rules primary address two
issues:
1.The geometrical reproduction of features that can be reproduced by the mask
making and lithographic process ,and
2. The interaction between different layers.
Thereare primarily two approaches in describing the design
rules. (i). Linear scaling is possible only over a
(ii). Scalable design rules are conservative .This results in over dimensioned and less
limited range of dimensions.
dense design.
(iii). This rule is not used in real life.
(i)Scalable Design Rules (e.g. SCMOS, λ-based design rules): In this approach, all
rules are defined in terms of a single parameter λ. The rules are so chosen that a design
can be easily ported over a cross section of industrial process ,making the layout portable
.Scaling can be easily done by simply changing the value of λ. The key disadvantages of
this approach are: maximum minimization is difficult.
(ii)Absolute Design Rules (e.g. μ-based design rules ) : In this approach, the design
rules are expressed in absolute dimensions (e.g. 0.75μm) and therefore can exploit the
features of a given process to a maximum degree. Here, scaling and porting is more
demanding, and has to be performed either manually or using CAD tools .Also, these rules
tend to be more complex especially for deep submicron.
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The fundamental unity in the definition of a set of design rules is the minimum line
width .It stands for the minimum mask dimension that can be safely transferred to the
semiconductor material .Even for the same minimum dimension, design rules tend to differ
from company to company, and from process to process. Now, CAD tools allow designs to
migrate between compatible processes.
Layer Representations
With increase of complexity in the CMOS processes, the visualization of all the mask
levels that are used in the actual fabrication process becomes inhibited. The layer concept
translates these masks to a set of conceptual layout levels that are easier to visualize by
the circuit designer. From the designer's viewpoint, all CMOS designs have the following
entities:
Two different substrates and/or wells : which are p-type for NMOS and n-type for
PMOS.
Diffusion regions (p+ and n+): which defines the area where transistors can be
formed. These regions are also called active areas. Diffusion of an inverse type is needed to
implement contacts to the well or to substrate.These are called select regions. • Transistor
gate electrodes : Polysilicon layer • Metal interconnect layers • Interlayer contacts and via
layers.The layers for typical CMOS processes are represented in various figures in terms
of: • A color scheme (Mead-Conway colors).
• Other color schemes designed to differentiate CMOS structures.
• Varying stipple patterns
• Varying line styles
An example of layer representations for CMOS inverter using above design
rules is shown
Fig 41. CMOS Inverter Layout

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Lambda(λ) Design Rules:
A conservative but easy-to-use set of design rules for layouts with two metal
layers in an n-well process is as follows:
□ Metal and diffusion have minimum width and spacing of 4 λ .
□ Contacts are 2 λ × 2 λ and must be surrounded by 1 below.
□ Polysilicon uses a width of 2 λ.
□ Polysilicon overlaps diffusion by 2 λ where a transistor is desired and has a
spacing of 1 λ away where no transistor is desired.
□ Polysilicon and contacts have a spacing of 3 λ from other polysilicon or contacts.

□ N-well surrounds pMOS transistors by 6 λ and avoids nMOS transistors by 6 λ.
Fig 42. Simplified Layout Design Rules
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Stick Layout
Another popular method of symbolic design is "Sticks" layout. In this, the
designer draws a freehand sketch of a layout, using colored lines to represent the various
process layers such as diffusion, metal and polysilicon .Where polysilicon crosses diffusion,
transistors are created and where metal wires join diffusion or polysilicon, contacts are
formed.
This notation indicates only the relative positioning of the various design
components. The absolute coordinates of these elements are determined automatically by
the editor using a compactor. The compactor translates the design rules into a set of
constraints on the component positions, and solve a constrained optimization problem that
attempts to minimize the area or cost function.
The advantage of this symbolic approach is that the designer does not have
to worry about design rules, because the compactor ensures that the final layout is
physically correct. The disadvantage of the symbolic approach is that the outcome of the
compaction phase is often unpredictable. The resulting layout can be less dense than
what is obtained with the manual approach. In addition, it does not show exact
placement, transistor sizes, wire lengths, wire widths, tub boundaries.
EXAMPLE LAYOUTS:
Inverter Layout :
The schematic diagram of the inverter is as shown in Figure.
Fig 43 b) Inverter-Layout
Fig 43. a)Inverter
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Here, the most important point to note is that as we change the placing of the
components in the schematic the stick diagram and hence, the layout of the circuit will
change accordingly. For example, if we place the components vertically the stick diagram
will be vertical and if we place the components horizontally the stick diagram will be
horizontal. Figure below shows the physical layout of inverter which is drawn in tanner
tool.
Fig 43 c)
Inverter-Layout
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VIDEO LINKS
S.NO TOPIC LINK

1 CMoS Inverter design using
https://youtu.be/wGAo-XqRxBI
tanner V16
Stick Diagram-a short revisit
https://youtu.be/GFkPCtUNT6w
2 part 1
Stick Diagram-a short revisit
https://youtu.be/4OSaVPARMeQ
3 part 2
4 MOS Transistor Basic-II
https://www.youtube.com/watch?v=-AW9zksRuRE&list=PL
Ly_2iUCG87Bdulp9brz9AcvW_TnFCUmM&index=3
5 CMOS Inverter basics https://www.youtube.com/watch?v=ZwD1kNvzO_g&list=
PLLy_2iUCG87Bdulp9brz9AcvW_TnFCUmM&index=6
6 NMOS and PMOS transistor in https://www.youtube.com/watch?v=oSrUsM0hoPs
CMOS inverter
7 Stick diagram of CMOS
https://www.youtube.com/watch?v=uoCkoEcbB9Q
inverter
8 Effort delay ,logical
https://www.youtube.com/watch?v=_KJM43nHO-o&lis
effort-know-how
t=PLS3FbwW7PEokm_HaZ711P7IlEMd2ojXsf&index=3
3
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6.4 ASSIGNMENT
Assignments ( For higher level learning and Evaluation -
Examples: Case study, Comprehensive design, etc.,)
UNIT I
CO BT
S.No Questions Level Level
1 Using spice based circuit simulation, estimate the delay of a CO1 K3
half adder and a full adder, when loaded with 4 inverters. Also
evaluate the delay of a mux loaded with 4 inverters to be used
in a carry select adder. (The full adder should not optimize
carry generation at the cost of delaying the sum output).
2 Simulate the design of a Wallace and a Dadda multiplier for CO1 K3
unsigned multiplication of two 8 bit numbers, generating a 16
bit product. Use a carry select architecture for the final adder
with square root stacking. You can use VHDL or verilog for
simulating the circuit. Your description should be synthesizable.
3 Now back annotate the delays of half adders and full adders CO1 K2
from the circuit simulation done earlier.
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6.5 UNIT 1 – PART A QUESTION AND ANSWERS
CO BT
S.No Questions
Level Level
What are the two types of design rules?
1 a. Micron rules CO1 K1
b. Lambda rules
What is body effect?

The resultant effect increases the channel substrate junction
2 potential. This increases the rate-channel voltage drop. The CO1 K1
overall effect is an increase in threshold voltage. This effort is
called body effect.
What is body effect coefficient?

The potential difference between the source and body affects
the threshold voltage. The threshold voltage can be modeled
3 as CO1 K1
Vt=Vt0+ϒ(√((Φs+Vsb) )-√Φs)
Where, Φs= surface potential at threshold γ= body effect
coefficient
What are the static properties of complementary

CMOS Gates?
They exhibit rails-to-rail swing with VOH = VDD and VOL = GND.
The circuits have no static power dissipation, since the circuits
4 are designed such that the pull-down and pull-up networks CO1 K2
are mutually exclusive.
The analysis of the DC voltage transfer characteristics and the
noise margins is more complicated than for the inverter, as
these parameters depend upon the data input patterns
applied to the gate.
Define Threshold voltage.

The threshold voltage Vt for a MOS transistor can be defined
5 as the voltage between the gate and the source terminals CO1 K1
below which the drain to source current effectively drops to
zero.
Define body effect or substrate bias effect.

The threshold voltage Vt is not a constant with respect to the
6 voltage difference between the substrate and the source of CO1 K1
the MOS transistor. This effect is called the body effect or
substrate bias effect
87
CO BT
S.No Questions
Level Level
Define body effect or substrate bias effect.
The threshold voltage Vt is not a constant with respect to the
7 voltage difference between the substrate and the source of CO1 K1
the MOS transistor. This effect is called the body effect or
substrate bias effect.
Give the different modes of operation of MOS
8 transistor CO1 K1
Cut off mode Linear mode Saturation mode
What are the different regions of operation of a MOS
transistor?
Cut off region: Here the current flow is essentially zero
(accumulation mode)
Linear region: It is also called weak inversion region where the
9 drain current is CO1 K1
dependent on the gate and the drain voltage w. r. to the
substrate.
Saturation region: Channel is strongly inverted and the drain
current flow is ideally independent of the drain-source voltage
(strong-inversion region).
Define accumulation mode.
The initial distribution of mobile positive holes in a p type
10 CO1 K1
silicon substrate of a mos transistor for a voltage much less
than the threshold voltage
Plot the current-voltage characteristics of a nMOS

transistor
11 CO1 K2
What are the secondary effects of MOS transistor?

• Threshold voltage variations
• Source to drain resistance
12 CO1 K2
• Variation in I-V characteristics
• Subthreshold conduction
• CMOS latch up
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CO BT
S.No Questions
Level Level
What is CMOS latch up? How it can be prevented?
The MOS technology contains a number of intrinsic bipolar
transistors. These are especially troublesome in CMOS
processes, where the combination of wells and substrates
results in the formation of p-n-p-n structures. Triggering
these thyristor like devices leads to a shorting of VDD & VSS
13 lines, usually resulting in a destruction of the chip. CO1 K1
The remedies for the latch-up problem include:

a. An increase in substrate doping levels with a consequent
drop in the value of Rp subs.
b. Reducing Rn well by control of fabrication parameters and
ensuring a low contact resistance to VDD.
c. By introducing guard rings.
What is diffusion process? What are doping
impurities?
14 Diffusion is a process in which impurities are diffused in to CO1 K1
the silicon chip at 10000C temperature. B2O3 and P2O5 are
used as impurities.
What is the influence of voltage scaling on power and
delay? Constant voltage scaling increased the electric field in
devices. By the 1μm generation velocity saturation was
15 severe enough that decreasing feature size no longer CO1 K1
improved device current. Aggressive process achieve delays
in the short end of the range by building transistors with
effective channel length.
Why the tunneling current is higher for NMOS

transistor than PMOS transistor with silica gate?
Tunneling current is an order of magnitude higher for nMos
16 CO1 K1
than PMos transistor with Sio2 gate dielectrics because the
electrons tunnel from the conduction band while the holes
tunnel from the valance band.
Why does interconnect increase the circuit delay?

a. The wire capacitance adds loading to each gate.
17 b. The long wire contributes RC delay or flight time. CO1 K1
c. Circuit delay can be increased by interconnect
89
CO BT
S.No Questions
Level Level
Determine whether an nMos transistor with a

threshold voltage of 0.7v is operating in the
saturation region if Vgs=2V and Vds=3V?
18 Vt=0.7 Vgs=2V Vd=3V CO1 K2
nMos transistor is in saturation region if Vds > Vgs-Vt
3V > 2V-0.7V
3V > 1.3V
It is in saturation region
What is the objective of layout rules?
Layout design rule is examined and a scale parameter
lambda is defined as the half width of a minimum width line
19 CO1 K1
or as a multiple of standard deviation of a process. Designing
layouts in terms of lambda allows for future scaling makes
the layout portable.
What are the advantages of CMOS technology ?
a. Low power consumption.
b. High performance.
20 CO1 K1
c. Scalable threshold voltage.
d. High noise margin.
e. Low output drive current.
Compare NMOS and PMOS ?
21 CO1 K1
What is Stick Diagram?

22 It is used to convey information through the use of color CO1 K1
code. Also it is the cartoon of a chip layout.
90
CO BT
S.No Questions
Level Level
Give the various color coding used in stick diagram?
a. Green – n-diffusion
b. Red- polysilicon
23 CO1 K2
c. Blue –metal
d. Yellow- implant
e. Black-contact areas.
What is Body effect?
The threshold voltage VT is not a constant with respect to
24 the voltage difference between the substrate and the source CO1 K1
of MOS transistor. This effect is called substrate-bias effect
or body effect.
What is Channel-length modulation?
The current between drain and source terminals is constant
and independent of the applied voltage over the terminals.
This is not entirely correct. The effective length of the
25 CO1 K1
conductive channel is actually modulated by the applied VDS,
increasing VDS causes the depletion region at the drain
junction to grow, reducing the length of the effective
channel.
Define Rise time.

26 Rise time, Tr is the time taken for a waveform to rise from CO1 K1
10% to 90% of its steady state value.
Define Fall time.

27 Fall time, Tf is the time taken for a waveform to fall from CO1 K1
90% to 10% of its steady state value.
Define Delay time.

Delay time, Td is the time difference between input transition
28 CO1 K1
(50%) and the 50% output level. This is the time taken for
a logic transition to pass from input to output.
Discuss the need of design rules.

Design rules specify geometry of masks which will provide
29 reasonable yields. Design rules are determined by CO1 K1
experience. Photoresist shrinkage, tearing. Variations in
material deposition.
91
CO BT
S.No Questions
Level Level
Compare between CMOS and bipolar technologies
30 CO1 K2
Explain the hot carrier effect.

When carriers (electrons or holes) gain high kinetic energy
31 due to the presence of high electric field within a CO1 K1
semiconductor device. Hot electrons are more probable than
hot holes since they have higher mobility to begin with.
Give the basic inverter circuit.
32 CO1 K1
What is Logic effort?

Logical effort is the ratio of the input capacitance of a gate to
33 CO1 K1
the input capacitance of an inverter delivering the same
output current.
What is parasitic delay?

Parasitic delay of the gate, is the delay when the gate drives
34 zero load. It is comfortable to use the term of normalized CO1 K1
parasitic delay, which is the ratio of diffusion capacitance to
the gate capacitance of certain process.
92
CO BT
S.No Questions
Level Level
What is Lambda design rule?

Lambda rule specify the layout constraints such as minimum
35 feature sizes and minimum allowable feature separations are K2
CO1 stated in terms of a single parameter (λ) and thus allow
linear, proportional scaling of all geometrical constraints
What is DRC?
Design Rule Check program looks for design rule violations in
36 the layout. It checks for minimum spacing and minimum size CO1 K1
and ensures that combinations of layers from legal
components.
Give the CMOS inverter DC transfer characteristics
and operating regions.
37 CO1 K2
Mention MOS transistor characteristics?

Metal Oxide Semiconductor is a three terminal device
having source, drain and gate.
a.The resistance path between the drain and the source is
38 CO1 K2
controlled by applying a voltage to the gate.
b.The Normal conduction characteristics of an MOS transistor
can be categorized as cutoff region non saturated region and
saturated region.
Define Elmore delay model?
It is an analytical method used to estimate the RC delay in
a network. Elmore delay model estimates the delay
of a RC K2
39 ladder as the sum over each node in the ladder of the
CO1 resistance Rn-1 between that node and a supply multiplied by
the capacitor on the nodes.
93
CO BT
S.No Questions
Level Level
What are the general properties of Elmore delay

model?
40 a. Single input node CO1 K1
b. All the capacitors are between a node and ground
c. Network does not contain any resistive loop
What is pass transistor?
It is a MOS transistor, in which gate is driven by a control
signal the source (out), the
drain of the transistor is called constant or variable voltage
41 CO1 K1
potential(in) when the control signal is high, input is passed
to the output and when the control signal is low, the output
is floating topology such topology circuits is called pass
transistor.
What is transmission gate?
The circuit constructed with the parallel connection of PMOS
and NMOS with shorted drain and source terminals. The
42 gate terminal uses two select signals s and s, when s is high CO1 K1
than the transmission gates passes the signal on the input.
The main advantage of transmission gate is that it
eliminates the threshold voltage drop.
List the advantages of pass transistor?
a.Pass transistor logic (PTL) circuits are often superior to
standard CMOS circuits in terms of layout density, circuit
43 CO1 K1
delay and power consumption.
b.They do not have path VDD to GND and do not dissipate
standby power (static power dissipation).
Why nMOS transistor is selected as pull down
transistor.
When high voltage is given at the input nMOS is turned ON.
44 So the output is pulled down to Vss. An NMOS device pulls CO1 K1
the output all the way down to GND, while a PMOS lowers
the output no further than |VTp| — the PMOS turns off at
that point, and stops contributing dis-charge current.
Define Micron design rule.
Micron rules specify the layout constraints such as minimum
45 feature sizes and minimum allowable feature separations CO1 K1
are stated in terms of absolute dimensions in micrometers.
94
CO BT
S.No Questions
Level Level
Define propagation delay of CMOS Inverter.

The inverter propagation delay (tP) is defined as the average
of the low-to-high (tPLH) and the high to low (tPHL)
propagation delays:
46 CO1 K1
tp=( tPLH+ tPHL)/2
Propagation delays tPLH and tPHL are defined as the times
required for output voltage to reach the middle between the
low and high logic levels, i.e. 50 % of VDD in our case of
CMOS logic.
What are the parameters affected by scaling.
a. Gate Area, Gate Capacitance per unit area,
Gate Capacitance
b. Charge in Channel, Channel Resistance
47 c. Transistor Delay, Maximum Operating Frequency CO1 K1
d. Transistor Current, Switching Energy
e. Power Dissipation Per Gate (Static and Dynamic)
f. Power Dissipation Per Unit Area
g. Power - Speed Product
Define scaling.
Proportional adjustment of the dimensions of an electronic
device while maintaining the electrical properties of the
device, results in a device either larger or smaller than the
48 unscaled device. CO1 K1
Types of scaling:
a. Full scaling (or) constant field scaling
b. Fixed voltage scaling
c. General scaling (or) Lateral scaling
What are the logic efforts of common gates?
49 CO1 K1
95
CO BT
S.No Questions
Level Level
What are the uses of transmission gate?
a. Electronic switch
50 b. Analog multiplexer CO1 K1
c. Logic circuits
d. Negative voltages
Write down the equation for describing the channel

length modulation effect in nMos transistor
Ideally Ids is independent of Vds in saturation.

a. The reverse biased p-n junction between the drain and
body forms a depletion region with a width Ld that
51 CO1 K1
increases with Vdb.
b. The depletion region effectively shortens the channel
length to Leff =L-Ld.
c. Imagine that the source voltage is close to the body
voltage. Increasing Vds decreases the effective channel
length.
Ids=β(Vgs-Vt)2/2
What are the uses of Stick diagram?
It can be drawn much easier and faster than a complex
52 layout. CO1 K1
These are especially important tools for layout built from
large cells.
What is tunneling in non IV ideal characteristics?

Based on quantum mechanics, we see that the is a finite
probability that carriers will tunnel through the gate
oxide. This results in gate leakage current flowing into the
gate.
The probability of tunneling drops off exponentially with oxide
thickness.
53 a. Large tunneling currents impact not only dynamic CO1 K1
nodes but also quiescent power consumption and thus
may limit oxide thickness tor.
b. Tunneling can purposely be used to create electrically
erasable memory devices.
c. Different dielectrics may have different tunneling
properties.
96
CO BT
S.No Questions
Level Level
Draw the stick diagram and layout for CMOS Inverter.
Stick diagram for CMOS Inverter:
54 layout for CMOS Inverter CO1 K2
Why NMOS devices conducts strong zero and weak

one?
Strong one means Vdd and strong 0 means passing ground to
the output.While passing a 1 , Vdd from a NMOS, as soon as
the output becomes Vdd-Vt,the transistor stops conducting as
now Vgs becomes less than Vt[Vgs-(Vdd-(Voutput)] hence
55 the output can no way go beyond Vdd-Vt,hence the output CO1
can no way now go beyond Vdd-Vt,hence we say that it has
passed weak 1.But in case of passing 0 ,no such problem
occurs as now the input terminal is source and output can
reach complete Gnd voltage and passes strong 0.Same
reasoning applies to pMOS where Gnd must be applied to
gate to switch it ON.
97
6.6 UNIT 1 PART B QUESTIONS
CO BT
S.No Questions
Level Level
Draw the standard CMOS logic, stick diagram and layout
1 diagram for the expression CO1 K4
Y= (A+B+C+D)’.
A ring oscillator is constructed from an odd number of
inverters, as shown in figure. Also find the frequency of 31-
stage ring oscillator in a 65 nm process that has г = 3ps
CO1 K4
2
Estimate the frequency of an N-stage ring oscillator

Derive drain current of MOS devices in different operating
3 regions and with the processing steps involved. Explain CO1 K5
copper dual damascene interconnect.
Discuss the CV Characteristics and DC transfer characteristics
4 CO1 K4
of the CMOS.
Briefly discuss about the layout design rules and explain the
5 CO1 K3
electrical properties of MOS transistor in detail
Derive an expression for Vin of a CMOS inverter to achieve the
CO1 K5
6 condition Vin = Vout, What should be the relation for βn =
βp.
Explain in detail about the ideal I-V characteristics and
7 CO1 K2
non-ideal I-V characteristics of a NMOS and PMOS devices
Explain in detail about the body effect and its effect in NMOS
8 and PMOS devices. Write the conditions for the different CO1 K2
regions of operation.
Write a short note on a) Oxide related capacitance b) Junction
9 CO1 K2
Capacitance
Discuss in detail with a neat layout, the design rules for a
10 CO1 K2
CMOS inverter
Discuss the origin of latch-up problems in CMOS circuits with
11 CO1 K2
necessary diagrams.
Explain the working of an enhancement type NMOS transistor
12 CO1 K2
with a neat sketch.
98
CO BT
S.No Questions
Level Level
13 Derive the MOS device equation various regions of operation CO1 K4
Derive the final expression and explain path logical effort,

14 CO1 K4
path electrical effort Path effort and path branching effort
Derive an expression for the rise time, fall time
15 CO1 K4
and propagation delay of a CMOS inverter
16 Explain detail about the scaling concept and reliability concept. CO1 K2
Describe in detail about the resistive and capacitive delay

17 CO1 K2
estimation of a CMOS Inverter circuit.
Explain in detail about
a. Channel length modulation.
18 CO1 K2
b. Constant field scaling.
c. Constant voltage scaling.
Explain the different factor that affects the reliability of CMOS
19 CO1 K2
chip
Explain the effect of temperature, supply voltage and process
20 CO1 K2
variation over behavior of CMOS systems.
What are the techniques used to size the transistor? Explain
21 CO1 K2
briefly
Sketch a 3-input NAND gate with transistor widths chosen to
achieve effective rise and fall resistance equal to that of a unit
inverter (R). Annotate the gate with its gate and diffusion
22 CO1 K3
capacitances. Assume all diffusion nodes are contacted. Then
sketch equivalent circuits for the falling output transition and
for the worst-case rising output transition.
99
6.7 SUPPORTIVE ONLINE CERTIFICATION COURSES
(NPTEL, SWAYAM, COURSERA, UDEMY, ETC.,) FOR
21EC503
S. Name of Name ofVLSI
theDESIGN
Duratio Link
the No online n
Course platform
https://onlinecourses.npt
Power management
1 NPTEL Swayam 12 Weeks
integrated circuits
el.ac.in/noc23_ee13/pre
view
https://www.coursera.or
2 VLSI CAD Part 1:logic Coursera 23 hours
g/learn/vlsi-cad-logic
https://www.coursera.or
3 VLSI CAD Part 2:logic Coursera 24 hours
g/learn/vlsi-cad-layout
https://www.cours
4
MOS Transistor Coursera 18 hours era.org/learn/mosf et
https://onlinecours
5 CMOS Digital VLSI
NPTEL 8 weeks
Design es.nptel.ac.in/noc2
1_ee09/preview
https://www.udem
y.com/course/vlsi-
6 4.5
academy-custom-
VSD Custom Layout Udemy hours
layout/
https://www.udem
y.com/course/vlsi-
7 VSD Physical Design
Udemy 5 hours academy-physical-
Flow
design-flow/
10
0
6.8 REAL TIME APPLICATIONS IN DAY TO DAY LIFE
AND INDUSTRY
A video gaming console comprising a housing, the housing incorporating a receptacle

for receiving detachable Storage means, the detachable Storage means containing a
computer gaming program, the housing including: communication means for receiving
interaction data from at least one control device operable by a user; processing means for
executing Said computer gaming program at least partially in reliance upon the interaction
data, thereby to generate display image data and one or more gaming images, a display
output terminating in a connector configured to enable connection of the Video gaming
console to a television or computer monitor, the display image data being output via the
display output for display on the television of computer monitor; and a printer apparatus
including a color printhead, a print media feed mechanism, an ink Supply unit and print
media Supply, Said printer apparatus being operatively associated with Said processing
means to print the one or more gaming images onto print media in response to execution of
Said computer gaming program.
10
1
6.9 CONTENTS BEYOND THE
SYLLABUS
FinFET
A FinFET is a transistor. Being a transistor, it is an amplifier and a switch. Its
applications include home computers, laptops, tablets, smartphones, wearables, high-
end networks, automotive, and more.FinFET stands for a fin-shaped field-effect
transistor. Fin because it has a fin-shaped body – the silicon fin that forms the
transistor’s main body distinguishes it.
Field-effect because an electric field controls the conductivity of the material.A

FinFET is a non-planar device, i.e., not constrained to a single plane. It is also called 3D
for having a third dimension.To avoid confusion, it is essential to understand that
different literature uses different labels when referring to FinFET devices.Choosing
FinFET devices instead of traditional MOSFETs happens for a variety of
reasons.Increasing computational power implies increasing computational density. More
transistors are required to achieve this, which leads to larger chips.
However, for practical reasons, it is crucial to keep the area about the same.As
previously stated, one way of achieving more computational power is by shrinking the
transistor’s size. But as the transistor’s dimensions decrease, the proximity between the
drain and the source lessens the gate electrode’s ability to control the flow of current in
the channel region. Because of this, planar MOSFETs display objectionable short-
channel effects.Shrinking the gate length (Lg) below 90 nm produces a significant
leakage current, and below 28 nm, the leakage is excessive, rendering the transistor
useless. So, as the gate length is scaled down, suppressing the off‐state leakage is
vital.Another way to increase computational power is by changing the materials used
for manufacturing the chips, but it may not be suitable from an economic standpoint.
In short, FinFET devices display superior short-channel behavior, have

considerably lower switching times, and higher current density than conventional
MOSFET technology.
10
2
SYLLABUS
FinFET
The channel (fin) of the FinFET is vertical. This device requires keeping in mind
specific dimensions. Evoking Max Planck’s “quanta,” the FinFET exhibits a property known as
width quantization: its width is a multiple of its height. Random widths are not possible.The
fin thickness is a crucial parameter because it controls the short-channel behavior and the
device’s subthreshold swing. The subthreshold swing measures the efficiency of a transistor.
It is the variation in gate voltage that increases the drain current one order of magnitude.
Figure 1 shows FinFET’s dimensions, where:
● Lg = gate length
● T = fin thickness
● Hfin = fin height
● W = transistor width (single fin)
● Weff = effective transistor width (multiple fins
10
3
SYLLABUS
FinFET
For double-gate: W = 2 ∙ Hfin
For tri-gate: W = 2 ∙ Hfin +
Multiple fins will increase the transistor widt.
Weff = n ∙ W
Where n = number of fins
Advantages:
● Better control over the channel
● Suppressed short-channel effects
● Lower static leakage current
● Faster switching speed
● Higher drain current (More drive-current per footprint)
● Lower switching voltage
● Low power consumption
Disadvantages:
● Difficult to control dynamic Vth

● Quantized device-width. It is impossible to make fractions of the fins, whereby
designers can only specify the devices’ dimensions in multiples of whole fins.
● Higher parasitics due to 3-D profile
● Very high capacitances
● Corner effect: electric field at the corner is always amplified compared to the
electric field at the sidewall. This can be minimized using a nitrate layer in
corners.
10
4
SYLLABUS
FinFET
Evolution
The foundation of modern electronics is the CMOS transistor. In the last

17 years, CMOS technology has made significant steps in terms of the materials
used in manufacture and architecture.The first great leap was the introduction of
strain engineering at the 90 nm technology node. Subsequent steps were the
metal gate with a high-k dielectric at 45 nm, and the FinFET architecture at the
22 nm node.
The year 2012 marked the birth of the first commercial 22nm
FinFET.
Subsequent improvements to the FinFET architecture allowed for improved
performance and reduced area. The 3D nature of the FinFET has many
advantages, like increasing the fin height to get a higher drive current at the
same footprint.Figure 2 shows the evolution of MOSFET structures: double-gate,
tri-gate, pi-gate, omega-gate, and gate-all-around.
Double-gate and tri-gate FinFETs are common due to their simple

structure and ease of fabrication.Although the GAA device was proposed before
the FinFET, the latter was more comfortable for executing production.
The problem with the GAA FinFET is more about fabrication than leakage. It
might help for a couple of nodes, which could mean more than a decade of additional
usage. Still, the loss of continuity in manufacturing processes might be significant
and expensive.
10
5
SYLLABUS
FinFET
Evolution
Future of FinFEt
FinFET will not be useful beyond 5nm, as it will not have enough electrostatic
control, requiring new architectures for the transistors. However, as technology
nodes advance, some companies may decide, for economic reasons, to stay with the
same node for longer. Other companies, due to the nature of their processes, will be
forced to adopt new technologies.
The gate-all-around (GAA) transistor emerges as the successor to FinFET for

significantly scaled process nodes. The GAA structure provides the most significant
capacitive coupling between the gate and the channel.
10
6
7. ASSESSMENT SCHEDULE
ASSESSMENT PROPOSED DATE ACTUAL DATE

Unit 1 Assignment
Assessment
Unit Test 1
Unit 2 Assignment
Assessment
Internal Assessment 1
Retest for IA 1
Unit 3 Assignment
Assessment
Unit Test 2
Unit 4 Assignment
Assessment
Internal Assessment 2
Retest for IA 2
Unit 5 Assignment
Assessment
Revision Test 1
Revision Test 2
Model Exam
Remodel Exam
University Exam
10
7
8.Prescribed Text Books & Reference Books
TEXT BOOKS:
1.Neil H.E. Weste, David Money Harris ―CMOS VLSI Design: A Circuits and Systems
Perspectiveǁ, 4th Edition, Pearson , 2017
2.Jan M. Rabaey ,Anantha Chandrakasan, Borivoje. Nikolic, Digital Integrated
Circuits:A Design perspectiveǁ, Second Edition , Pearson ,2016.
REFERENCES :
3. M.J. Smith, ―Application Specific Integrated Circuitsǁ, Addisson Wesley, 1997
4.Sung-Mo kang, Yusuf leblebici, Chulwoo Kim ―CMOS Digital Integrated Circuits:
Analysis & Designǁ,4th edition McGraw Hill Education,2013
5. Wayne Wolf, ―Modern VLSI Design: System On Chipǁ, Pearson Education, 2007
6. John F Walkerly, Digital Design Principles and Practices, Third Edition., PHI/Pearson
Education, 2005.
7. Samir Palnitkar, Verilog HDL: A Guide to Digital Design and Synthesis, Prentice Hall
PTR Second Edition,2003
10
8
9. MINI PROJECT SUGGESTIONS
S.NO NAME OF THE PROJECT

1. Generating PWM Signals With Variable Duty Cycle using FPGA
2. Bluetooth Based Wireless Home Automation System
3. FPGA Implementation of distance Measurement using Ultrasonic

Sensor
4. Efficient Novel Binary to Gray Code Converter Using Columbic
Interaction on Quantum Dot Cellular Automata
5. Design and Implementation of Vedic Multiplier an Improved Carry
Increment Adder
10
9
Thank
you
Disclaimer:
This document is confidential and intended solely for the educational purpose of RMK Group of
Educational Institutions. If you have received this document through email in error, please notify the
system manager. This document contains proprietary information and is intended only to the
respective group / learning community as intended. If you are not the addressee you should not
disseminate, distribute or copy through e-mail. Please notify the sender immediately by e-mail if you
have received this document by mistake and delete this document from your system. If you are not
the intended recipient you are notified that disclosing, copying, distributing or taking any action in
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1

21EC503 - VLSI DESIGN (Lab Integrated)

Department :Electronics and Communication

5 CO- PO/PSO MAPPING 11

UNIT 1 – INTRODUCTION TO MOS TRANSISTOR 15

6.1 Lecture Plan 16

6.2 Activity based learning 17

6.3 Lecture Notes 18

6.3.1 MOS Transistor 18

6.3.2 Long Channel I-V Characteristics 30

6.3.3 CV Characteristics of MOSFET 43

6.3.4 CMOS Inverter DC Transfer Characteristics 48

6.3.5 Non Linear I-V Characteristics: (or) Non Ideal I-V 56

6.3.7 CMOS Scaling and its limitations 64

6.3.8 Propagation delay of CMOS Inverter 67

6.3.9 Linear Delay Model-Logical effort 70

6.3.10 Stick Diagrams 76

6.5 Part A Question & Answer 91

6.6 Part B Questions 102

6.7 Supportive online Certification courses 104

6.8 Real time Applications in day to day life and to 105

7 Assessment Schedule 111

8 Prescribed Text Books & Reference Books 112

9 Mini Project suggestions 113

❖ To study the fundamentals of CMOS circuits and its characteristics.

❖ To learn the design and realization of combinational & sequential digital

1.21EC303 - DIGITAL ELECTRONICS

2. 21EC404 – LINEAR INTEGRATED CIRCUITS

Subject Code Subject Name L T P C

21EC503 VLSI Design (Lab 3 0 2 4

UNIT I INTRODUCTION TO MOS TRANSISTOR 15

UNIT II COMBINATIONAL MOS LOGIC CIRCUITS 15

UNIT III SEQUENTIAL CIRCUIT DESIGN 15

After successful completion of the course, the students should be

CO2 Realize the combinational circuits using different logic families K3

Understand the memory design in sequential logic circuits K3

Analyze the architectural choice and performance tradeoff

Understand the different FPGA architectures and its testing K2

Design, Simulate to verify the functionality of logic modules

Design solutions for complex engineering problems and design

Create, select, and apply appropriate techniques, resources, and

Apply reasoning informed by the contextual knowledge to assess

Environment Understand the impact of the professional engineering solutions in

Communicate effectively on complex engineering activities with the

To analyze, design and develop solutions by applying

PSO2 To apply design principles and best practices for developing

To adapt to emerging information and communication

CMOS logic, Inverter, K2 Chalk &

Total No. of Periods : 9

Future of VLSI in the AI Era

Layout Design Rules

6.3.1. MOS Transistor

Fig 1. MOSFET Structure

(iii) Inversion Mode

Electrically an MOS device can be considered as a voltage-controlled switch that

In general, any MOSFET is seen to exhibit three operating regions viz.,

and Vds< Vgs-Vt)

Ids=(µCoxW/L)[((Vgs-Vt)Vds-Vds2)/2] , Ids=β[(Vgs-Vt)Vds-Vds ^2 /2]

they can be used as amplifiers.