2EC202

FPGA based System Design

Akash Mecwan & Vijay Savani

APEC, IT, NU.
/2024

Logic Values

Value Condition in Hardware Circuit

0 Logic zero, false condition
1 Logic one, true condition
X Unknown logic value
Z High impedance, floating state

Verilog Basics
2
/2024

Logic Strenths

Verilog Basics
3
Gate Level Modeling
 Basic Gates

Verilog Basics 5
 Truth Table To Follow

Verilog Basics 6
 Buffer and Not Gates

Verilog Basics 7
 Bufif/Notif

Verilog Basics 8
 Bufif/Notif (Cont…)

Verilog Basics 9
 Gate Delays

Rise Delay

Fall Delay

Turnoff Delay

Verilog Basics 10
 Gate Delays (Cont…)

Verilog Basics 11
 Max, Min, Typ Delays

Verilog Basics 12
 Delay Use

Verilog Basics 13
Data Flow Modelling
 Outline
 Continuous Assignment
o The assign statement
o Implicit Continuous Assignment
o Implicit Net Declaration
 Gate Level Vs Data Flow Modeling
 Delays:
o Regular Assignment delay
o Implicit Continuous Assignment Delay
o Net Declaration Delay
 Expressions, Operands and Operators
 Parameter
 Issues with 4-valued logic
04/14/2024 Verilog Basics 15
 Continuous Assignment

 Next level up: Dataflow modeling

o Continuous assignment
 The assign keyword

module my_and(output out, input in1, in2);

assign out = in1 & in2;
endmodule

04/14/2024 Verilog Basics 16

 Rules for assign statement
 LHS data type:
o ONLY net (wire),
o scalar or vector net
o concatenations of scalar or vector net
o can not be scalar or vector reg
 Are always active [RHS evaluated and assign to LHS]
 RHS data type:
 register, net or function calls
 register can be scalar or vector
 Delay values can be specified in terms of time units,
similar to specifying delay for gate
 Default value for strength is strong1 and strong0

04/14/2024 Verilog Basics 17

Rules for assign statement

04/14/2024 Verilog Basics 18

Implicit continuous assignment

04/14/2024 Verilog Basics 19

 Implicit Net declaration

04/14/2024 Verilog Basics 20

Gate Level vs. Dataflow Modeling
Gate Level Model
module mux4_to_1 (output
out,
input i0, i1, i2, i3, s1, s0);
wire s1n, s0n, y0, y1, y2, y3;
not (s1n, s1);
not (s0n, s0);

and (y0, i0, s1n, s0n); Dataflow Model

and (y1, i1, s1n, s0); module mux4_to_1 (output out,
input i0, i1, i2, i3, s1, s0);
and (y2, i2, s1, s0n);
and (y3, i3, s1, s0); assign out = (~s1 & ~s0 & i0)|
(~s1 & s0 & i1)|
or (out, y0, y1, y2, y3); ( s1 & ~s0 & i2)|
endmodule ( s1 & s0 & i3);
endmodule

04/14/2024 Verilog Basics 21

Delays
 Delays
 Control the time between the change in a
right-hand-side operand and when the
new value is assigned to the left-hand
side
1. Regular Assignment Delay
o Assign a delay value in a continuous assignment
statement & Specified after the keyword assign
2. Implicit Continuous Assignment Delay
o Equivalent to implicit continuous assignment
3. Net Declaration Delay
o A delay is specified along with net declaration

04/14/2024 Verilog Basics 23

Specifying Delays at Dataflow Level
1. Regular Assignment Delay
assign #10 out = in1 & in2;

A pulse of width less than the specified assignment

delay is not propagated to the output.
Delays to Dataflow Level are Inertial Delay

04/14/2024 Verilog Basics 24

Specifying Delays at Dataflow Level

2. Implicit Continuous Assignment Delay

wire #10 out = in1 & in2;
//same as
wire out;
assign #10 out = in1 & in2;

3. Net Declaration Delay

04/14/2024 Verilog Basics 25

Expression
Operands
Operators
 Expression, Operands, Operators
Expressions are constructs that
combine operators and operands
to produce a result.

// Examples of expressions. Combines operands and

operators
o a^b
o addr1[20:17] + addr2[20:17]
o in1 | in2

04/14/2024 Verilog Basics 27

 Expression, Operands, Operators
It Can be
o constants, integers, real numbers, nets, registers,
times, bit-select (one bit of vector net or a vector
register), part-select (selected bits of the vector net
or register vector), and memories or function calls
(functions are discussed later).
integer count, final_count;
final_count = count + 1; //count is an integer operand
real a, b, c;
c = a - b; //a and b are real operands
reg [15:0] reg1, reg2;
reg [3:0] reg_out;
reg_out = reg1[3:0] ^ reg2[3:0]; //reg1[3:0] and reg2[3:0] are
//part-select register operands
reg ret_value;
ret_value = calculate_parity(A, B);//calculate_parity is a
//function type operand
04/14/2024 Verilog Basics 28
 Expression, Operands, Operators

 Operators act on the operands to produce desired

results.

 Examples:
o d1 && d2 // && is an operator on
operands d1 and d2
o !a[0] // ! is an operator on operand a[0]
o B >> 1 // >> is an operator on operands
B and 1

04/14/2024 Verilog Basics 29

 Operators
Operator Category Operators Symbol
Arithmetic * / + - % **
Logical ! && ||
Relational > < <= >=
Equality == != === !===
Bitwise ~ & | ^ ^~ ~^
Reduction (out is one bit) & ~& | ~| ^ ~^ OR ^~
Shift >> << >>> <<<
Concatenation {}
Replication {{}}
Conditional ?:

04/14/2024 Verilog Basics 30

 Arithmetic Operators
A = 4'b0011; +5
B = 4'b0100; -4
D = 6; E = 4; F=2;

A*B
D/E
A+B
B-A
F = E ** F;
• 4-valued logic issue:
13 % 3 x and z values
16 % 4 in1 = 4'b101x;
-7 % 2 in2 = 4'b1010;
7 % -2 sum = in1 + in2;

04/14/2024 Verilog Basics 31

 Arithmetic Operators

04/14/2024 Verilog Basics 32

Logical and Relational Operators
 Logical Operators:
 Evaluate to 1-bit value
 ! && ||
 Operands: True:1, False:0, x or z => x
 Outcome: 0, 1, x
 Can take variable or expression as operand

04/14/2024 Verilog Basics 33

 What will be the Hardware (RTL)
module test (a,b,c);
input a,b;
output c;
wire d,e;

assign e = a & d;
assign c = b | e;

endmodule

What if, wire d=1’b0;

What if, wire d= 1’b1;

04/14/2024 Verilog Basics 34

Logical and Relational Operators

04/14/2024 Verilog Basics 35

Logical and Relational Operators
 Relational Operators: [> < <= >=]
 Evaluate to logic 1 - If expression is True
 Evaluate to logic 0 - If expression is False
 “Unknown or z” value usually treated as x
(operand)

04/14/2024 Verilog Basics 36

 Equality Operators

// A = 4, B = 3 // Z = 4'b1xxz, M = 4'b1xxz
// X = 4'b1010, Y = 4'b1101 // N = 4'b1xxx

X == Z -x
A == B - 0
X != Y - 1 Z === M - 1
Z === N - 0
M !== N - 1
04/14/2024 Verilog Basics 37
 Bitwise Operators

 Bitwise Operators: [~ & | ^ ^~ ~^]

 Bit by Bit Operation
 If one operand is shorter than other, it will be
extended to zero [to match the length]
 Z is treated as X
 ~ is unary operator

04/14/2024 Verilog Basics 38

 Bitwise Operators
// X = 4'b1010
// Y = 4'b1101
// Z = 4'b10x1
~X
X&Y
X|Y
X^Y
X ^~ Y
X&Z

04/14/2024 Verilog Basics 39

 Reduction Operators

 Reduction Operators:
 and(&), nand(~&), or(|), nor(~|), xor(^),
xnor(~^)
 Takes only one operand
 Results in one bit output
 Works from right to left

04/14/2024 Verilog Basics 40

 Reduction Operators
// X = 4'b1010

&X => 1’b0

|X => 1’b1
^X => 1’b0

04/14/2024 Verilog Basics 41

 Shift Operators
// X = 4'b1100

Y = X >> 1;
Y = X << 1;
Y = X << 2;

integer a, b, c;
a = 0;
b = -10;
c = a + (b >> 3);

04/14/2024 Verilog Basics 42

 Concatenation Operator
 Provides mechanism to append multiple
operands
 Unsized operands not allowed

// A = 1'b1, B = 2'b00,
// C = 2'b10, D = 3'b110

Y = {B , C} Y = 4'b0010
Y = {A , B , C , D , 3'b001} Y = 11'b100……01
Y = {A , B[0], C[1]} Y = 3'b101

04/14/2024 Verilog Basics 43

 Replication Operator
reg A;
reg [1:0] B, C;
reg [2:0] D;
A = 1'b1; B = 2'b00; C = 2'b10; D = 3'b110;
Y = { 4{A} }
Y = { 4{A} , 2{B} }
Y = { 4{A} , 2{B} , C }

04/14/2024 Verilog Basics 44

 Conditional Operator

Port/Const/Vari = Condition ? True_Value : False_Value;

assign addr_bus = drive_enable ? addr_out : 36'bz;

assign out = control ? in1 : in0;

04/14/2024 Verilog Basics 45

 Operators Precedence
 Unary: [+ - ! ~]
 Mul, Div, Mod: * / %
 Add, Sub: + -
 Shift: >> <<
 Relational: < <= => >
 Equality: == != === !==
 Reduction
 Logical
 Conditional

04/14/2024 Verilog Basics 46

 Radix Specifiers

04/14/2024 Verilog Basics 47

 Examples - MUX

04/14/2024 Verilog Basics 48

Sequential Logic at Dataflow Level

04/14/2024 Verilog Basics 49

Sequential Logic at Dataflow Level
 Negative Edge Triggered D-FF
module edge_dff(q, qbar, d, clk, clear);
output q,qbar;
input d, clk, clear;
wire s, sbar, r, rbar,cbar;
assign cbar = ~clear;
assign sbar = ~(rbar & s),
s = ~(sbar & cbar & ~clk),
r = ~(rbar & ~clk & s),
rbar = ~(r & cbar & d);
assign q = ~(s & qbar),
qbar = ~(q & r & cbar);
endmodule

04/14/2024 Verilog Basics 50

 Edge-Triggered T-FF
module edge_dff(q, qbar, d, clk, clear);
...
endmodule

module T_FF(q, clk, clear);

output q;
input clk, clear;
edge_dff ff1(q, ,~q, clk, clear);
endmodule

04/14/2024 Verilog Basics 51

“Faith is taking the first step
even when you can’t see the
whole staircase.”
– Martin Luther King Jr.

Thank You

Verilog Basics 52