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Embedded Systems
Embedded
Systems Design

By Abebe B.
BASIC STRUCTURE OF AN
EMBEDDED SYSTEM
Let's see the block diagram shows the basic structure
of an embedded system.

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BASIC STRUCTURE OF AN
EMBEDDED SYSTEM
• Sensor: Sensor used for sensing the change in environment condition and it generate
the electric signal on the basis of change in environment condition. Therefore it is also
called as transducers for providing electric input signal on the basis of change in
environment condition.
• A-D Converter: An analog-to-digital converter is a device that converts analog electric
input signal into its equivalent digital signal for further processing in an embedded
system.
• Processor & ASICs: Processor used for processing the signal and data to execute
desired set of instructions with high-speed of operation. Application specific integrated
circuit (ASIC) is an integrated circuit designed to perform task specific operation inside
an embedded system.
• D-A Converter: A digital-to-analog converter is a device that converts digital electric
input signal into its equivalent analog signal for further processing in an embedded
system.
• Actuators: Actuators is a comparator used for comparing the analog input signal level
to desired output signal level for providing the error free output from the system.
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EMBEDDED SYSTEMS -
ARCHITECTURE TYPES
•When data and code lie in different memory blocks, then the
architecture is referred as Harvard architecture.
•In case data and code lie in the same memory block, then the
architecture is referred as Von Neumann architecture.

Von Neumann Architecture Harvard Architecture 4

 EMBEDDED SYSTEMS -
ARCHITECTURE TYPES
•The following points distinguish the Von Neumann Architecture from
the Harvard Architecture.
Von-Neumann Architecture Harvard Architecture

Single memory to be shared by both code
and data.
Processor needs to fetch code in a separate
clock cycle and data in another clock cycle.
So it requires two clock cycles.
Separate memories for code and
data.
Single clock cycle is sufficient, as
separate buses are used to access
code and data.

Higher speed, thus less time consuming. Slower in speed, thus more time-
consuming.
Simple in design. Complex in design.
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CISC AND RISC
•CISC is a Complex Instruction Set Computer. It is a
computer that can address a large number of
instructions.
•In the early 1980s, computer designers recommended
that computers should use fewer instructions with
simple constructs so that they can be executed much
faster within the CPU without having to use memory.
Such computers are classified as Reduced Instruction
Set Computer or RISC.

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 CISC AND RISC
CISC RISC
Larger set of instructions. Easy to program Smaller set of Instructions. Difficult to
program.

Simpler design of compiler, considering Complex design of compiler.

larger set of instructions.

Many addressing modes causing complex Few addressing modes, fix instruction
instruction formats. format.

Emphasis is on hardware. Emphasis is on software.

Slower execution, as instructions are to be Faster execution, as each instruction is to

read from memory and decoded by the be executed by hardware.
decoder unit.
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DESIGN STEPS REQUIRED FOR
THE DEVELOPMENT OF ES
•Designing steps required for
embedded system are different
from the design process of another
electronic system.
•Let's see a flow chart represent the
design steps required in the
development of an embedded
system:

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DESIGN CHALLENGE
Obvious design goal:
 Construct an implementation with desired functionality
Key design challenge:
 Simultaneously optimize numerous design metrics
Design metric
 A measurable feature of a system’s implementation
 Optimizing design metrics is a key challenge

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DESIGN CHALLENGE –
OPTIMIZING DESIGN
METRICS
Common metrics
Unit cost: the monetary cost of manufacturing each copy of the system,
excluding NRE cost.
NRE cost (Non-Recurring Engineering cost): The one-time
monetary cost of designing the system.
Size: the physical space required by the system.
Performance: the execution time or throughput of the system.
Power: the amount of power consumed by the system.
TotalCost = NRE + UnitCost * Volume
UnitCost = the cost to manufacture one unit of the product
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DESIGN CHALLENGE –
OPTIMIZING DESIGN
METRICS
Common metrics (continued)
 Flexibility: the ability to change the functionality of the
system without incurring heavy NRE cost.
 Time-to-prototype: the time needed to build a working
version of the system.
 Time-to-market: the time required to develop a system to the
point that it can be released and sold to customers
 Maintainability: the ability to modify the system after its
initial release.
 Correctness, safety, many more.

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 DESIGN METRIC
COMPETITION -- IMPROVING
ONE MAY WORSEN OTHERS
Power
Expertise with both software and
hardware is needed to optimize design
metrics
Performance Size  Not just a hardware or software expert, as is
common
 A designer must be comfortable with various
NRE cost
technologies in order to choose the best for a
given application and constraints
Digital camera chip
CCD
CCD preprocessor Pixel coprocessor D2A
A2D
lens

JPEG codec Microcontroller Multiplier/Accum

DMA controller Display ctrl Hardware

Software
Memory controller ISA bus interface UART LCD ctrl

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 TIME-TO-MARKET: A
DEMANDING DESIGN
METRIC Time required to develop a product
to the point it can be sold to
customers.
Market window
Period during which the product
Revenues ($)

would have highest sales

Average time-to-market constraint
Market window
is about 8 months
Delays can be costly
Time (months)

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 LOSSES DUE TO DELAYED
MARKET ENTRY
Peak revenue Simplified revenue model
 Product life = 2W, peak at W
Peak revenue from delayed entry  Time of market entry defines a
triangle, representing market
Revenues ($)

On-time
penetration
Market rise Market fall  Triangle area equals revenue
Delayed Loss
 The difference between the on-
time and delayed triangle areas
D W 2W

Time
On-time Delayed
entry entry

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 LOSSES DUE TO DELAYED
MARKET ENTRY
Area = 1/2 * base * height
Peak revenue  On-time = 1/2 * 2W * W
 Delayed = 1/2 * (W-D+W)*(W-D)
Peak revenue from delayed entry
Percentage revenue loss =
Revenues ($)

On-time
(D(3W-D)/2W2)*100%

Market rise Market fall Try some examples

– Lifetime 2W=52 wks, delay D=4 wks
Delayed
– (4*(3*26 –4)/2*26^2) = 22%
– Lifetime 2W=52 wks, delay D=10 wks
– (10*(3*26 –10)/2*26^2) = 50%
D W 2W
– Delays are costly!
Time
On-time Delayed
entry entry

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 NRE AND UNIT COST
METRICS
Costs:
 Unit cost: the monetary cost of manufacturing each copy of the
system, excluding NRE cost
 NRE cost (Non-Recurring Engineering cost): The one-
time monetary cost of designing the system
 total cost = NRE cost + unit cost * # of units
 per-product cost = total cost / # of units
= (NRE cost / # of units) + unit cost
• Example
– NRE cost =$2,000, unit cost =$100
– For 10 units
– total cost = $2000 + 10*$100 = $3000
– per-product cost = $2000/10 + $100 = $300

Amortizing NRE cost over the units results in an

additional $200 per unit
*total cost= deign cost
+Manufacturing cost*(# of 16
units)
 EXERCISE 1
The design of a particular disk (a) added cost = NRE / # units
produced
drive has an NRE cost of $100,000 = $100,000 / 100
and a unit cost of $20. = $1,000 Hence,
•How much will we have to add to Total cost= Added cost+ unit cost
the cost of the product to cover our
= $1000+$20 =$1020
NRE cost, assuming we sell:
(a) 100 units, and
(b) added cost = NRE / # units
(b) 10,000 units produced
(c) 100,000 units = $100,000 / 10,000
= $10 Hence,

(D) 10 units Total cost= Added cost+ unit cost

= $10+$20 =$30

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 NRE AND UNIT COST
METRICS
Compare technologies by costs -- best depends on quantity
 Technology A: NRE=$2,000, unit=$100
 Technology B: NRE=$30,000, unit=$30
 Technology C: NRE=$100,000, unit=$2
$200,000 $200
A A
B B
$160,000 $160
C C
to ta l c o st (x1000)

p e r p ro d u c t c o st

$120,000 $120

$80,000 $80

$40,000 $40

$0 $0
0 800 1600 2400 0 800 1600 2400
Nu m b e r o f u n its (vo lu m e ) Nu m b e r o f u n its (vo lu m e )

• But, must also consider time-to-market

*The best Technology choice depend on the number of units we plan to produce.
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 THREE KEY EMBEDDED
SYSTEM TECHNOLOGIES
Technology
A manner of accomplishing a task, especially using technical
processes, methods, or knowledge
Three key technologies for embedded systems
• Processor technology
• IC technology
• Design technology(reading assignment)

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 PROCESSOR
TECHNOLOGY
The architecture of the computation engine used to implement a
system’s desired functionality
Processor does not have to be programmable
 “Processor” not equal to general-purpose processor

Controller Datapath Controller Datapath Controller Datapath

Control index
Control Register Control logic Registers
logic
logic and file and State total
State register register State
Custom +
ALU register
General
IR PC ALU IR PC
Data Data
memory memory
Program Data Program memory
memory memory
Assembly code Assembly code
for: for:

total = 0 total = 0
for i =1 to … for i =1 to …
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 PROCESSOR TECHNOLOGY
Processors vary in their customization for the problem at hand.

total = 0
for i = 1 to N loop
total += M[i]
end loop
Desired functionality

General-purpose Application-specific Single-purpose

processor processor processor

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 GENERAL-PURPOSE
PROCESSORS
Programmable device used in a variety of Controller Datapath

applications Control
logic and State
Register
file
 Also known as “microprocessor” register

Features IR PC
General
ALU

 Program memory
 General Datapath with large register file and general Program memory Data
ALU memory

Assembly code for:

User benefits total = 0

 Low time-to-market and NRE costs for i =1 to …

 High flexibility

“Pentium” the most well-known, but there are

hundreds of others 22
 SINGLE-PURPOSE
PROCESSORS
Digital circuit designed to execute exactly
one program Controller Datapath

 a.k.a. coprocessor, accelerator or peripheral, microcontroller Control logic index

Features total
 Contains only the components needed to execute a State register
single program +

 No program memory

Benefits Data
 Fast memory

 Low power
 Small size
• They are used in a wide range of applications, including
automotive systems, industrial control systems, and consumer
electronics. 23
 FEATURES OF SINGLE-
PURPOSE EMBEDDED
PROCESSORS
Specialized functionality: designed to perform a specific task
Low power consumption: they are often designed to be energy-efficient,
making them well-suited for battery-powered applications.
Compact size: they are often designed to be small and lightweight, making
them well-suited for applications where space is limited.
High reliability: they are often designed to be highly reliable, as they are
typically used in mission-critical applications where downtime is not an
option.
Low cost: they are often less expensive than general-purpose processors, as
they are designed to perform a specific set of tasks and do not require the
same level of flexibility and programmability.

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 IC TECHNOLOGY
The manner in which a digital (gate-level) implementation is
mapped onto an IC
 IC: Integrated circuit, or “chip”
 IC technologies differ in their customization to a design
 IC’s consist of numerous layers (perhaps 10 or more)
 IC technologies differ with respect to who builds each layer
and when

gate

oxide
IC package IC

source channel drain

Silicon substrate
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 IC TECHNOLOGY
Three types of IC technologies
Full-custom/VLSI
Semi-custom ASIC
PLD (Programmable Logic Device)

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 FULL-CUSTOM/VLSI
All layers are optimized for an embedded
system’s particular digital implementation
 Placing transistors
 Sizing transistors
 Routing wires

Benefits
 Excellent performance, small size, low power

Drawbacks
 High NRE cost (e.g., $300k),
 long time-to-market
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SEMI-CUSTOM
Lower layers are fully or partially built
 Designers are left with routing of wires and maybe placing
some blocks
Benefits
 Good performance, good size, less NRE cost than a full-
custom implementation.

Drawbacks
 Still require weeks to months to develop

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 PLD (PROGRAMMABLE
LOGIC DEVICE)
All layers already exist
 Designers can purchase an IC
 Field-Programmable Gate Array (FPGA) very
popular
Benefits
 Low NRE costs, almost instant IC availability

Drawbacks
 Bigger, expensive (perhaps $30 per unit), power
hungry, slower

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 MOORE’S LAW
The most important trend in embedded
systems
 Predicted in 1965 by Intel co-founder Gordon Moore
IC transistor capacity has doubled roughly every 18 months for
the past several decades
10,000

1,000

Logic transistors per 100

chip 10
(in millions)
1

0.1
Note: logarithmic
scale 0.01

0.001
1981

1983

1985

1987

1989

1991

1993

1995

1997

1999

2001

2003

2005

2007

2009
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GRAPHICAL ILLUSTRATION OF
MOORE’S LAW
1981 1984 1987 1990 1993 1996 1999 2002

10,000 150,000,000
transistors transistors

Leading edge Leading edge

chip in 1981 chip in 2002

Something that doubles frequently grows more quickly than most

people realize!
 A 2002 chip can hold about 15,000 1981 chips inside itself

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 SUMMARY
Embedded systems are everywhere
Key challenge: optimization of design metrics
 Design metrics compete with one another

A unified view of hardware and software is

necessary to improve productivity
Three key technologies
 Processor: general-purpose, application-specific, single-purpose
 IC: Full-custom, semi-custom, PLD
 Design: Compilation/synthesis, libraries/IP, test/verification

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