INTERRUPTS

• Interrupts are signals emitted by hardware when a process or an event needs

immediate attention. It alerts the processor to a high-priority process requiring
interruption of the current working process.

• The real time programming (quick responses to events to control the

environment which generated the events) can be successfully done by
interrupts.
• Interrupts are produced by either internal chip operations or by external
sources.
• Interrupts perform a hardware call to interrupt handling subroutine, that is
stored in program memory.
• Five interrupts are provided in 8051.
• Three are generated automatically by internal operations.
Timer Flag 0
Timer flag 1
Serial Port interrupt (RI or TI)
• Two interrupts are triggered by external signals provided by circuitry that is
connected to pins INT0 and INT1.
• The interrupt functions are under the control of the program.
• Special function registers-IE &IP
• The programmer can block any of the interrupts by altering the control bits in
the IE, IP & TCON registers. (IE – Interrupt Enable, IP – Interrupt Priority, TCON –
Timer Control)

• After handling the interrupt by the interrupt routine, the interrupted program
will resume the operation at the instruction where the interrupt took place.

• For this, the interrupted PC address is stored in the stack (in RAM) before going
to the interrupt address, (in ROM) and which will be restored from stack after
the RETI (Return from Interrupt) instruction is executed at the end of the
interrupt subroutine.
THE INTERRUPT ENABLE (IE) SFR

Bit Symbol Function

7 Enable Interrupt bit. Cleared to 0 by program to disable all
EA interrupts. Set to 1 to permit individual interrupts to be enabled
by their enable bits.
6 ----- Not implemented.
5 ET2 Reserved for future use
4 Enable serial port interrupt. Set to 1 by program to enable serial
ES port interrupt; cleared to 0 to disable serial port interrupt.
3 Enable timer 1 overflow interrupt. Set to 1 by program to
ET1 enable timer 1 overflow interrupt; cleared to 0 to disable
timer 1 overflow interrupt.
2 EX1 Enable external interrupt 1. Set to 1 by program to enable
INT1 interrupt; cleared to 0 to disable INT1 interrupt.
1 Enable Timer 0 overflow interrupt. Set to 1 by program to enable
ET0 timer 0 overflow interrupt; cleared to 0 to disable timer 0
overflow interrupt.
0
EX0
Enable External interrupt 0. Set to 1 program to enable
INT0 interrupt; cleared to 0 to disable INT0 interrupt.
THE INTERRUPT PRIORITY (IP) SFR

Bit Symbol Function

7 ----- Not implemented.
6 ----- Not implemented.
5 PT2 Reserved for future use
4 PS
Priority of serial port interrupt.
3 PT1 Priority of timer 1 overflow interrupt. Set / cleared by program.
2 PX1 Priority of external interrupt 1. Set/ cleared by program.
1 PT0 Priority of timer 0 overflow interrupt. Set/cleared by program.
0 PX0
Priority of external interrupt 0. Set/ cleared by program.
THE FIVE INTERRUPTS IN 8051
TIMER FLAG INTERRUPT
• When timer/counter overflows, TF0 or TF1 is set to 1.
• Cleared to 0 when the interrupt generates a program call to the
appropriate timer subroutine in memory.
SERIAL PORT INTERRUPT
• If a data byte is received an interrupt bit RI is set to 1 in the SCON
register.
• When data byte is transmitted an interrupt bit TI is set to 1 in the SCON
register.
• These are OR-ed to provide a single interrupt to the processor :serial
port interrupt.
• Bits are not cleared when the interrupt generated program call is made.
• The program must reset RI or TI for the next operation.
EXTERNAL INTERRUPT

• Pins INT0 and INT1 are used by external circuitry.

• The interrupt flags IE0 and IE1 in the TCON register are set by two
different ways.
 When INTX pin reaches a low level.
 When high to low transition takes place in the INTX pin.
• Bits IT0 and IT1 program INTX pins
 Set to 0 for low level signal
 Set to 1 for high to low transition.
• IEX is reset when the interrupt is accepted and subroutine is
accessed.
RESET
• It is the ultimate interrupt.
• It is a non-maskable interrupt because no
combination of bits in any register can stop or
mask the reset action.
• The PC is not stored for later program
resumption.
• It is an absolute command to jump to 000h and
to commence program from there.
• Internal RAM is not changed on reset.
• Register bank 0 is selected on reset.
• I INTERRUPT CONTROL
• At critical times the program must be able to inhibit action of some or
all of the interrupts to finish crucial operations.
• The IE register holds the programmable bits that can enable or disable
all interrupts either as a group or one by one.
• Priority is set between competing interrupts.

INTERRUPT ENABLE/DISABLE

• Bits in IE register is set to enable the interrupt source.

• Cleared to disable the interrupts.
• Bit EA is the master/global bit, used to enable or disable all of the
interrupts.
INTERRUPT CONTROL

• IP determine if any interrupt have a low or high priority.

• Set 1 to give the interrupt a high priority.
• Set to 0 to assign a low priority.
• The lower priority interrupt is executed only after the higher is finished.
• If two interrupts having same priority; they are executed as
1. IE0
2. TF0
3. IE1
4. TF1
5. Serial=RI or TI
INTERRUPT CONTROL
• Each interrupt source caused the program to do a hardware call to one of the
dedicated addresses in the memory.
• The programmer must place a routine at this address.
• The interrupt saves the PC of the program in execution.
• A call is then done to the appropriate memory location.
INTERRUPT ADDRESS
IE0 0003
IT0 000B
IE1 0013
ITI 001B
SERIAL 0023

• A RETI Instruction restores the PC in its place and resets the interrupt logic.
• Any ignored interrupt must persist until they are serviced; else lost.
SOFTWARE GENERATED INTERRUPTS

• If any interrupt flag is set by any means an interrupt is generated unless

blocked.
• The program can generate interrupt by setting the interrupt flag to 1 using
program instructions.