Vipin Kizheppatt 17/01/2024: 8085 Microprocessor

8085 MicroProcessor
Vipin Kizheppatt 17/01/2024

Overview
• 8- bits general purpose processor
introduced in 1976
• Word length of a processor : The size of
the data the processor can process at a
time
• An 8-bit processor has instructions to
processor 8-bit data at a time, a 16-bit
processor 16-bit data at a time and so on.
• Most of the processors we use in desktop
and server applications now a day are 64-
bit processors
• 16-bit processors are very common in
embedded systems
• A 16-bit processor can still process 32-bit
data by using multiple 16-bit instructions 2
Overview
• 40-pin DIP package
• Around 6500 transistors in 3um
technology
• Uses +5V single supply and runs at
clock frequency 3MHz to 5MHz
• Can address maximum 64KB
memory
• Instruction set upward compatible
with 8080A
Pinout
3
Overview
For connecting external crystal

Oscillators (3MHz to 5MHz)
4
Overview
5 V Supply and ground
5
Overview
Lower 8 bits of
Address, multiplexed Upper 8 bits of
with Data Address
6
Overview
Address latch enable.
Distinguishes whether
AD0-AD7 contains
valid address or not
7
Overview
Read Enable (Active low)

Write Enable (Active low)
8
Overview
Used distinguish between

memory access and input
output device address
9
Overview
Serial output
data and serial
input data
(Similar to
RS232)
10
8085-Based System Example
A Bus is a communication structure.
Physically they will be a one or a group
A7:A0
AD7:AD0 Latch of conductors. Data communication
happens on the bus based on a set of S
En rules called protocol Y
Address Bus (16-bits wide) S
ALE T
8085 Processor E
A15:A8 M
Data Bus (8-bits wide)
B
IO/M#,RD’,WR’ Control Bus U
S
Memory Memory
(ROM) (RAM)
11
8085 Assembly Level
•
Programming
Assembly-level programs are written using the
instructions of the processor that we use
• All instructions of a processor together is called
instruction set
• 8085 has 74 unique instructions in its instruction set
• Instructions are stored in the memory in binary

format, which the processor executes one after the
other through 3 main steps
 Fetch : Bring the instruction from memory into the
processor
 Decode : With the help of digital circuits inside
processor, determine what the instruction is supposed
to do
 Execute : Perform the actions the instruction12is
8085 Assembly Level
• Since
Programming
writing instructions in binary
is error
prone, they are usually written using
mnemonics and then converted into
numbers either manually (hand assembly) or
with the help of another program called
assembler
• Instructions in hexadecimal/binary after
assembling is called machine code
13
8085 Programming Model
• Along with instructions, we should also need
to know the internal processor register
details to write assembly code
• Programming model is an abstract model of
the processor describing only the required
architecture of the processor from a
programmer’s (software engineers)
perspective
• It doesn’t describe the actual hardware
implementation of the processor
• Low-level hardware implementation details
called the micro-architecture is of interest
to hardware designers 14
Accumulator (A) Flag Register

(8)
B C
(8) (8)
D E
(8) (8)
H L
(8) (8)
Stack Pointer (SP)

(16)
Program Counter (PC)

(16)
15
6 General purpose
registers (B,C,D,E,H,L)
(8)
All are 8-bits wide
B C
(8) (8)
Can combine into
D
(8) E (8) pairs to make 16-bit
registers. Valid
H (8) L combinations are BC,
(8)
DE, HL
Stack Pointer (SP)
(16)
(16)
16
Accumulator (A) Flag Register Accumulator or A register.

(8)
Every arithmetic and logic
B C operation involves A
(8) (8)
register. It is also 8 bits.
D E The result of ALU
(8) (8)
operation gets stored in A
H (8) L
(8)
Stack Pointer (SP)
(16)
(16)
17
Accumulator (A) Flag Register Flag register is a special

(8)
function register.
B C Also called program status
(8) (8)
word (PSW). It indicates
D E the status of ALU
(8) (8)
operation. Although 8 bits,
H (8) L only 5 bits are valid
(8)
Stack Pointer (SP)
(16)
(16)
18
7 6 5 4 3 2 1 0
S Z AC P CY
Zero: Set when ALU Result is 0

Parity: Set if result has even parity
Sign: Set when the MSB of ALU result is 1
Carry: Set if there is carry in ALU operation
Auxiliary Carry: Set when there is auxiliary carry (carry from D3 to D4)
19

(8)
B C Controls the program
(8) (8)
execution sequence
D E
(8) (8)
Also called instruction
H (8) L pointer (IP)
(8)
Stack Pointer (SP) 16-bit register
(16)
Program Counter (PC) Points to the memory
(16)
location from where next
instruction will be fetched
20

(8)
B C Points to the top of stack
(8) (8)
memory
D E
(8) (8)
16-bit register
H (8) L
(8)
Stack Pointer (SP)
(16)
(16)
21
Instruction classification
• Instructions can be classified based on
different criteria such as
(a) the type of operation the instruction does
(Eg: arithmetic instruction, data transfer
instruction etc)
(b) size of instruction (one byte, two byte etc.)
(c) based on addressing mode (register
addressing, immediate addressing etc.)
Every instruction has an operation code
(opcode) and optional one or more operands
Eg MOV A,B
Opcode Operands 22
Instruction classification
8085 instruction set
Data Transfer Logical Control
Arithmetic Branching
23
Data Transfer Instructions
• Instructions to copy data between registers
or registers and memory, registers and
input/output etc.
• Data transfer instructions will have a source
location and a destination location
• Here data is copies meaning the data at the
source location is preserved
• In 8085 data transfer instructions do not
affect any flag bits
• General instruction format
Opcode
Destination, Source
24
Opcode Operand(s) Size Description
MOV Rd, Rs 1 Byte Copy data from Rs

register to Rd register.
Rs/Rd can be
A,B,C,D,E,H,L
MOV M, Rs 1 Byte Copy data from Rs to
memory location
Rd,M Copy data from memory
location to Rs
Rs/Rd : A,B,C,D,E,H,L
M: specified by HL pair
25
MVI Rd,8 bit 2 Bytes Copy constant 8-bit data

data to Rd
Rd : A,B,C,D,E,H,L
MVI M, 8 bit 2 Bytes Copy constant 8-bit data
data to memory location M
LDA 16 bit 3 Bytes Load the content of the
address memory to accumulator
STA 16 bit 3 Bytes Store the content of the
address accumulator to memory
26
Arithmetic Instructions
• Instructions to perform arithmetic
operations such as addition and subtraction
• Accumulator (A) acts as one of the sources
and destination for most of the arithmetic
operations
• Arithmetic operations affect the bits in the
flag register
27
ADD Rs 1 Byte Add register Rs with A and

store result in A
Rs: A,B,C,D,E,H,L
ADD M 1 Bytes Add content of memory M
with A and store result in A
ADC Rs 1 Byte Add register Rs with A and
carry and store result in A
Rs: A,B,C,D,E,H,L
28
ADC M 1 Byte Add memory location M

with A and carry and store
result in A
ADI 8-bit data 2 Bytes Add immediately 8 bit data
ACI 8-bit data 2 Bytes Add immediately 8 bit data
with A and carry and store
result in A
29
SUB Rs 1 Byte Subtract register Rs from A

and store result in A
Rs: A,B,C,D,E,H,L
SUB M 1 Bytes Subtract content of
memory M from A and
store result in A
SBB Rs 1 Byte Subtract register Rs from A
with borrow(carry flag) and
store result in A
Rs: A,B,C,D,E,H,L
30
SBB M 1 Byte Subtract memory location

M from A with borrow and
store result in A
SUI 8-bit data 2 Bytes Subtract immediately 8 bit
data from A and store
result in A
SBI 8-bit data 2 Bytes Subtract immediately 8 bit
data from A with borrow
and store result in A
31
INR R 1 Byte Increment the content of R by

1
R: A,B,C,D,E,H,L
INR and DCR don’t affect carry
flag
INR M 1 Byte Increment the content of
memory M by 1
M specified by HL pair
INX R pair 1 Byte Increment register pair content
by 1
R : B (BC pair), D (DE pair), H
(HL pair)
32
DCR R 1 Byte Decrement the content of R

by 1
R: A,B,C,D,E,H,L
DCR M 1 Byte Decrement the content of
memory M by 1
DCX R pair 1 Byte Decrement register pair
content by 1
R : B (BC pair), D (DE pair), H
(HL pair)
33
Logical Instructions
• Instructions to perform logical operations
such as AND OR etc.
• Accumulator (A) acts as one of the sources
and destination for most of the arithmetic
operations
• logical operations affect the bits in the flag
register
34
ANA Rs 1 Byte AND register Rs with A and

store result in A
Rs: A,B,C,D,E,H,L
ANA M 1 Bytes AND content of memory M
ANI 8 bit data 2 Bytes AND A with 8-bit data and
store result in A
35
ORA Rs 1 Byte OR register Rs with A and

store result in A
Rs: A,B,C,D,E,H,L
ORA M 1 Byte OR content of memory M
ORI 8 bit data 1 Byte OR A with 8-bit data and
store result in A
36
XRA Rs 1 Byte XOR register Rs with A and

store result in A
Rs: A,B,C,D,E,H,L
XRA M 1 Byte XOR content of memory M
XRI 8 bit data 1 Byte XOR A with 8-bit data and
store result in A
37
CMA 1 Byte Complement accumulator

(toggle every bit of A)
CMP R 1 Byte Compare A with register R
A<R CY=1 Z=0
A=R CY=0 Z=1
A>R CY=0 Z=0
R: A,B,C,D,E,H,L
CMP M 1 Byte Compare A with memory M
A<M CY=1 Z=0
A=M CY=0 Z=1
A>M CY=0 Z=0
38
CPI 8-bit data 2 Bytes Compare A with 8 bit data

A<data CY=1 Z=0
A=data CY=0 Z=1
A>data CY=0 Z=0
STC 1 Byte Set carry flag to 1
CMC 1 Byte Complement carry flag
39
Branch Instructions
• Instructions used to implement conditional
statements in the program (similar to if else
conditions in high-level programs)
• The change the sequence of program
• If there are no branch instructions, your
program will be always executing
sequentially one instruction after the other
• Since the next instruction for execution is
selected by program counter (instruction
pointer), branch instructions are indirect
way to manipulate it
• Branch instructions extensively use the flag
bits 40
Branch Instructions
JMP 16-bit address 3 Bytes Unconditionally jump to the

address specified
JC 16-bit address 3 Bytes Jump if carry flag bit is set
(CY=1)to the address
specified
JNC 16-bit address 3 Bytes Jump if carry flag bit is not
set (CY=0) to the address
specified
JZ 16-bit address 3 Bytes Jump if zero flag bit is set
(Z=1) to the address specified
41
Branch Instructions
JNZ 16-bit address 3 Bytes Jump if zero flag bit is not set
(Z=0) to the address specified
JP 16-bit address 3 Bytes Jump if positive (S=0, D7=0)
to the address specified
JM 16-bit address 3 Bytes Jump if minus (S=1, D7=1) to
the address specified
JPE 16-bit address 3 Bytes Jump if even parity (P=1) to
JPO 16-bit address 3 Bytes Jump if odd parity (P=0) to
42
Control Instructions
• Used to control the processor
HLT 1 Bytes HALT instruction. Stop

program execution.
Essentially stop fetching
more instructions
NOP 1 Bytes No operation. Processor
doesn’t perform any
operation and fetches next
instruction
RST N 1 Bytes Restart execution from
address N*8, where N is from
0-7
43
Programming Flow
Eg: Write an assembly level program (ALP) to
add the numbers 20H and 30H and store the
result memory location 1000H
– Step 1: Decide the algorithm you are going to
use (Algorithm you can think in terms of flow-
chart, pseudo code or in natural language)
– Find the instructions to implement each step
of the algorithm
– Assemble your code (either manually or
using an assembler)
– Store the program in processor memory
– Reset the processor and let it execute
– Verify the program output 44
Programming Flow
result memory locationStart
1000H
Store 20H in a register
Store 30H in another register
Add the register contents
Store result in memory
Stop
45
Programming Flow
MVI A,20H
MVI A,0H
ADI A,20H
Store 20H in a register XRA A
ADI A,20H
MVI H,20H
MVI L,00H
MVI M,20H
LDA 2000H
MVI A,0
INR A
CPI 20
JNZ 0002 46
Programming Flow
result memory location
Start 1000H
Store 20H in a register MVI A,20H

Store 30H in another register MVI B,30H
Add the register contents ADD B
Store result in memory 1000H STA 1000H
Stop HLT 47
Programming Flow
Hand assembling
MVI A,20H
MVI B,30H
ADD B
STA 1000H
HLT
MVI A  00111110  0x3E
MVI A,20H  0x3E 0x20 48
Programming Flow
ALP Code Machine Code in Hex

MVI A,20H 3E 20
MVI B,30H 06 30
ADD B 80
STA 1000H 32 00 10
HLT 76
Programming Flow
Latch
00111110 (3EH) 0
8085
Processor 00100000 (20H) 1
00000110 (06H) 2
00110000 (30H) 3
10000000 (80H) 4
Memory Memory Latch(32H)
00110010 5
(ROM) (RAM)
00000000 (00H) 6
10000101 (10H) 7
01110110 (76H) 8
XX 9
XX
A
Memory
Programming Flow
Latch
FETCH
00111110 (3EH) 0
8085
Processor 00100000 (20H) 1
00000110 (06H) 2
00110000 (30H) 3
10000000 (80H) 4
00110010 5
(ROM) (RAM)
00000000 (00H) 6
10000101 (10H) 7
01110110 (76H) 8
XX 9
XX
A
Memory
Programming Flow
Latch
00111110 (3EH) 0
8085
Processor 00100000 (20H) 1
00000110 (06H) 2
00110000 (30H) 3
10000000 (80H) 4
00110010 5
3EH (ROM) (RAM)
Control logic Decodes 00000000 (00H) 6
instructions and Finds 10000101 (10H) 7
it needs to copy data
from next memory 01110110 (76H) 8
location. Increments PC XX
by 2 (instruction size) 9
XX
A
Memory
Programming Flow
Latch
00111110 (3EH) 0
8085
Processor 00100000 (20H) 1
00000110 (06H) 2
00110000 (30H) 3
10000000 (80H) 4
After Execution Memory Memory Latch(32H)
00110010 5
20 (A) Flag Register (ROM) (RAM)
00000000 (00H) 6
B C
10000101 (10H) 7
D E
01110110 (76H) 8
H L
XX 9
Stack Pointer (SP) XX
A
PC = 2 Memory
Programming Flow 00111110 (3EH) 0
00100000 (20H) 1
00000110 (06H) 2
At the end of Program 00110000 (30H) 3
10000000 (80H) 4
50 (A) 0 (Flags)
Latch(32H)
00110010 5
30 (B) C
00000000 (00H) 6
D E
10000101 (10H) 7
H L
01110110 (76H) 8
Stack Pointer (SP)
XX 9
PC = 8
XX
A
XX 9FF
Latch (50H) 1000
01010000
Memory XX 1001
Programming Flow
find the sum of first 10 natural numbers. Store
final result in 0x2000 Start
Initialize a counter to 10
Initialize a register to store sum to 0
Add counter and sum register
Decrement count by 1
No Count
== 0?
Yes
Store sum at 0x2000
Stop 55
Programming Flow
final result in 0x2000
MVI C,10 ;counter

MVI A,0H ;sum register
ADD C
DCR C Manually finding
this jump address
JNZ 0004H is difficult
STA 2000H
HLT
56
Programming Flow
final result in 0x2000
MVI C,10 ;counter We can use labels

as symbolic
Loop: representation of
address and the
ADD C assembler will
DCR C replace them
JNZ Loop appropriate
address.
STA 2000H Indentation not
HLT mandatory 57
Programming Flow
MVI C,0 ;counter
MVI B,0H Variables to register
Loop: mapping, instructions
MOV A,B that you choose and
ADD C the sequence of
INR C execution that you
MOV B,A choose can
MOV A,C considerably affect
CPI 11 your code size
JNZ Loop
MOV A,B
STA 2000H
HLT 58
Programming Flow
Eg: Add the numbers 0x1BC and 0x221 and
store the result in memory from address 0x2000
MVI A,BCH ;Add the lower bytes first

ADI 21H
STA 2000H;Store the result. Remember flags
are not affected by data movement
instructions
MVI A,1
ACI 2;Add the upper bytes along with carry
of previous addition
STA 2001H
59
HLT
Programming Flow
Eg: Store 2 eight-bit numbers at location 0x1000
and 0x1001. Find their product and store at location
0x2000
8085 doesn’t have an instruction for multiplication!!
Multiplication needs to be done by repeated

addition (division by repeated subtraction)
Multiplying 2 8-bit numbers may result in up to 16-

bits. Hence result should be stored using two
continuous locations (lower byte in 0x2000 and
upper in 0x2001 since Intel follows little endian
architecture) 60
Programming Flow
MVI A,20H ;Let’s try to multiply
STA 1000H ;20H and 30H
MVI A,30H ;This part of code
STA 1001H ;enables us to test main code
61
Programming Flow
main:
MVI A,0H ;Clear accumulator
MVI B,0H ;Upper byte of result
MVI H,10H
MVI L,00H
MOV C,M ;Will use C as counter
INX H
loop:
ADD M
JNC Next
INR B
Next:
DCR C
JNZ loop
STA 2000H
MOV A,B
STA 2001H
62
HLT
Addressing Modes
• Addressing modes  Various formats of
specifying operands in instruction
• Immediate Addressing Mode: Operand data
is directly specified in the instruction itself
Eg: MVI A,20H
JMP 2000H
• Register Addressing Mode: Instruction uses
operand stored in a register
Eg: MOV A,B
ADD B
INR C
63
Addressing Modes
• Direct Addressing Mode: Data to be operated
is stored/to be stored in memory and that
memory address is directly specified in the
instruction
Eg: LDA 2000H
STA 1000H
• Register Indirect Addressing Mode: Address
of the operand is stored in a register pair
(such as HL or BC) and the register pair is
used in the instruction (similar to a pointer)
Eg: MOV A,M
LDAX B ; Move content of the
memory pointed by BC pair to accumulator 64
Stack Memory
• Part of main memory used to store data
temporarily during program execution
• Starting location of stack is usually
configured from the main program
• Stack is a last-in first-out memory (LIFO)
• In 8085 top of stack (address till which data
is stored) is pointed by a 16-bit register
called stack pointer
Stack Pointer (SP) Next data will be stored here 9FF
1000H
Last dataLatch
stored in stack 1000
XX 1001
65
Stack Instructions
LXI SP 16-bit address 3 Bytes Load the SP with 16-bit

address
PUSH Rp 1 Byte PUSH (Store) the content of
register pair into the Stack
memory
Rp : B (BC pair), D (DE pair), H
(HL pair), PSW (A and Flag
register)
POP Rp 1 Byte POP (copy) the top 2 bytes of
data to the register pair Rp
Rp : B, D, H, PSW
66
Stack Program Flow
9F6
LXI SP, 1000H xx (A) xx (Flags) 9F7
xx (B) xxC 9F8
xx D xxE 9F9
9FA
xx H xx L
SP Latch 9FB
PC 9FC
9FD
9FE
9FF
1000
Stack Program Flow
9F6
xx (B) xxC 9F8
xx D xxE 9F9
9FA
xx H xx L
1000H (SP) Latch 9FB
PC 9FC
9FD
9FE
9FF
1000
Stack Program Flow
9F6
LXI B, 1234H
12H (B) 34H (C) 9F8
xx D xxE 9F9
9FA
xx H xx L
PC 9FC
9FD
9FE
9FF
1000
Stack Program Flow
9F6
LXI B, 1234H
12H (B) 34H (C) 9F8
PUSH B
xx D xxE 9F9
9FA
xx H xx L
9FFH (SP) Latch 9FB
PC 9FC
9FD
9FE
9FF
1000
Stack Program Flow
9F6
LXI B, 1234H
12H (B) 34H (C) 9F8
PUSH B
xx D xxE 9F9
9FA
xx H xx L
9FFH (SP) Latch 9FB
PC 9FC
9FD
9FE
12H 9FF
1000
Stack Program Flow
9F6
LXI B, 1234H
12H (B) 34H (C) 9F8
PUSH B
xx D xxE 9F9
9FA
xx H xx L
9FEH (SP) Latch 9FB
PC 9FC
9FD
9FE
12H 9FF
1000
Stack Program Flow
9F6
LXI B, 1234H
12H (B) 34H (C) 9F8
PUSH B
xx D xxE 9F9
9FA
xx H xx L
9FEH (SP) Latch 9FB
PC 9FC
9FD
34H 9FE
12H 9FF
1000
Stack Program Flow
9F6
LXI SP,1000H xx (A) xx (Flags) 9F7
LXI B,1234H
56H (B) 78H (C) 9F8
PUSH B
LXI B,5678H xx D xxE 9F9
9FA
xx H xx L
9FEH (SP) Latch 9FB
PC 9FC
9FD
34H 9FE
12H 9FF
1000
Stack Program Flow
9F6
LXI B,1234H
12H (B) 34H (C) 9F8
PUSH B
POP B 9FA
xx H xx L
9FEH (SP) Latch 9FB
PC 9FC
9FD
34H 9FE
12H 9FF
1000
Stack Program Flow
9F6
LXI B,1234H
12H (B) 34H (C) 9F8
PUSH B
POP B 9FA
xx H xx L
9FFH (SP) Latch 9FB
PC 9FC
9FD
34H 9FE
12H 9FF
1000
Stack Program Flow
9F6
LXI B,1234H
12H (B) 34H (C) 9F8
PUSH B
POP B 9FA
xx H xx L
PC 9FC
9FD
34H 9FE
12H 9FF
1000
Code Manipulation with Stack
PUSH B
PUSH D
Essentially swaps BC and DE pairs
POP B
POP D
MVI L,0
PUSH H Essentially clears flag register
POP PSW
78
Stack Overflow
• Since stack grows in higher address to lower
address, SP is usually initialized at
maximum memory address
• Because of the way SP works in 8085,
initializing it to 0 doesn’t cause any issue
• But what happens if you X keep on pushing
data to stack? X+1 Code grows in this direction
X+2
X+3
Latch
X+4
X+5
Stack grows in this direction
X+6
79
X+7
Subroutines
• Subroutines are like functions in high-level
languages
• They allow modular design of program
• They enable code reuse
• They helps in reducing program size
80
Subroutine Instructions
CALL 16-bit 3 Bytes Call subroutine

address unconditionally
CC, CNC, CZ, CNZ, 16-bit 3 Bytes Conditional CALLs
CP, CN, CPE, CPO address
RET 1 Byte Return from
subroutine
unconditionally
RC,RNC,RZ,RNZ, 1 Byte Conditional Return
RP,RN,RPE,RPO
81
Subroutine Program Flow
• Write a subroutine to add two 8-bit numbers
main:
LXI SP,1000H
mvi A,20H
mvi B,30H
call add
hlt
;subroutine. Assumes the numbers to add ;are

in registers A and B and return value ;is in A
add:
add B
82
ret
main: Address Machine Code
LXI SP,1000H 0 31 00 10
mvi A,20H 3 3E 20
mvi B,30H 5 06 30
call add 7 CD 0A 00
hlt A 76

add:
add B B 80
83
ret C C9
Subroutines and Stack
call add 7 CD 08 00
9F6
20H( A) xx (Flags) 9F7
30H(B) XX H (C) 9F8
xx D xxE 9F9
9FA
xx H xx L
9FEH (SP) Latch 9FB
PC 9FC
9FD
0AH 9FE
Address of the next instruction after call is
automatically pushed to stack 00H 9FF
1000
84
call add 7 CD 08 00
9F6
30H(B) XX H (C) 9F8
xx D xxE 9F9
9FA
xx H xx L
9FEH (SP) Latch 9FB
0008 (PC) 9FC
9FD
0AH 9FE
Program counter gets loaded with starting
address of subroutine and execution jumps 00H 9FF
to the subroutine 1000
85
main: Address Machine Code
LXI SP,1000H 0 31 00 10
mvi A,20H 3 3E 20
mvi B,30H 5 06 30
call add 7 CD 0A 00
hlt A 76

add:
add B B 80
86
ret C C9
ret C C9
9F6
30H(B) XX H (C) 9F8
xx D xxE 9F9
9FA
xx H xx L
000A (PC) 9FC
9FD
0AH 9FE
When RET instruction is executed, top two
bytes from stack is read and stored in PC. Thus 00H 9FF
the function returns 1000
87
Caution
• The number of push and pop operations
within a subroutine should exactly match!!
• Otherwise, you don’t know where the
function will return when the ret instruction
is executed
• When writing a subroutine, it is a good idea
to restore every register except the one
through which you are returning the value
• For this purpose, you can push every register
to stack at the beginning of subroutine and
pop them back just before returning
• Make sure the order of push or pop are
exactly opposite in this case (since stack 88is

Vipin Kizheppatt 17/01/2024: 8085 Microprocessor

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Vipin Kizheppatt 17/01/2024: 8085 Microprocessor

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8085 MicroProcessor

Vipin Kizheppatt 17/01/2024

For connecting external crystal

5 V Supply and ground

Read Enable (Active low)

Used distinguish between

• Instructions are stored in the memory in binary

Accumulator (A) Flag Register

Stack Pointer (SP)

Program Counter (PC)

Accumulator (A) Flag Register Accumulator or A register.

Accumulator (A) Flag Register Flag register is a special

Zero: Set when ALU Result is 0

Sign: Set when the MSB of ALU result is 1

Carry: Set if there is carry in ALU operation

Accumulator (A) Flag Register

Accumulator (A) Flag Register

Data Transfer Logical Control

MOV Rd, Rs 1 Byte Copy data from Rs

MVI Rd,8 bit 2 Bytes Copy constant 8-bit data

ADD Rs 1 Byte Add register Rs with A and

ADC M 1 Byte Add memory location M

SUB Rs 1 Byte Subtract register Rs from A

SBB M 1 Byte Subtract memory location

INR R 1 Byte Increment the content of R by

DCR R 1 Byte Decrement the content of R

ANA Rs 1 Byte AND register Rs with A and

ORA Rs 1 Byte OR register Rs with A and

XRA Rs 1 Byte XOR register Rs with A and

CMA 1 Byte Complement accumulator

CPI 8-bit data 2 Bytes Compare A with 8 bit data

JMP 16-bit address 3 Bytes Unconditionally jump to the

HLT 1 Bytes HALT instruction. Stop

Store 20H in a register

Store 30H in another register

Add the register contents

Store result in memory

Store 20H in a register MVI A,20H

ALP Code Machine Code in Hex

Initialize a register to store sum to 0

Add counter and sum register

MVI C,10 ;counter

MVI C,10 ;counter We can use labels

MVI A,BCH ;Add the lower bytes first

8085 doesn’t have an instruction for multiplication!!

Multiplication needs to be done by repeated

Multiplying 2 8-bit numbers may result in up to 16-

LXI SP 16-bit address 3 Bytes Load the SP with 16-bit

xx (B) xxC 9F8

xx (B) xxC 9F8

CALL 16-bit 3 Bytes Call subroutine

;subroutine. Assumes the numbers to add ;are

;subroutine. Assumes the numbers to add ;are

0008 (PC) 9FC

;subroutine. Assumes the numbers to add ;are

000A (PC) 9FC

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