Synthesis Optimization

Techniques
1. Ungrouping:
• The compile_ultra command automatically ungroups logical hierarchies.
• Ungrouping merges sub-designs of a given level of the hierarchy into the parent cell or design.
• It removes hierarchical boundaries and allows Design Compiler to improve timing by reducing the levels of logic and
to improve area by sharing logic.
• compile.flow.autoungroup false | true (default)
2.Boundary Optimization:
• The compile_ultra command performs the following types of Boundary optimization by default.
• compile.flow.boundary_optimization true | false (By Default it is true)
• Propagation of constant across the hierarchy:

• Propagation of equal and opposite information across the hierarchy:

• Propagation of unconnected port information across the hierarchy:

• Pushing of inverters across the hierarchy (phase inversion):

3. Register Retiming:
• Retiming is a sequential optimization technique.
• It is used to move registers across combinatorial logic to improve the design performance without affecting the input/output behavior
of the circuit.
• compile.retiming.optimization_priority auto (the default)
• auto (the default) : The tool determines the best tradeoff between register count and timing.
• timing : Timing is high priority while minimizing register count.
• register_count : Register count reduction is prioritized over timing. Timing violations are assumed to be recovered by other
optimizations.
4.High-level Optimization:

• During high-level optimization, Design Compiler applies techniques such as tree delay minimization and arithmetic simplifications .
Tree Delay Minimization and Arithmetic Simplifications:
• During tree delay minimization, Design Compiler arranges the inputs to arithmetic trees.

• For example, the expression a + b + c + d describes three levels of cascaded addition operations. The tool can rearrange this
expression to (a + b) + (c + d), which might result in faster logic (only two levels of cascaded operations).
• Additional simplification is available with compile_ultra command; some examples are
Sink Cancellation
• The expression (a + b - a) is simplified to b.

Constant Folding
• The expression (a * 3 * 5) is transformed to (a * 15)
• Resource Sharing:
• The tool determines whether to share or reverse the sharing of operators during a later phase that is, during timing-driven
optimization.
5. Register Merging
• Register Banking, also referred to as Multi-Bit Register Banking is a physical implementation technique of merging two or
more flip-flops into a single multi-bit register.
• compile.seqmap.enable_register_merging true(default) | false
6. High-Fanout Net synthesis
• High Fanout Net Synthesis (HFNS) is the process of buffering the high fanout nets to balance the load.
• To balance the load HFNS is performed. Too many loads will affect delay number and transition times because load is directly proportional to
the delay. By buffering the High Fanout Net (HFN) load can be balanced.
• Clock nets, reset, scan enable nets are generally considered as High Fanout Nets.
• HFNS is not performed on clock nets and don't touch attribute nets.
7.Group path:

• The synthesis tool organizes timing paths into groups. The grouping of paths affects the optimization of the design and the
generation of timing reports.
• By default, there is one path group for each clock in the design. All timing paths clocked by a given clock at the path
endpoint belong to that clock’s path group.
• All timing paths within a path group are optimized for timing together, starting with the critical path. Paths within a group
are optimized and reported separately from other groups.
• You can use the group_path command to assign paths to existing groups or new groups that you create, which lets you
control the focus of optimization effort and the reporting of paths.
• Groups all endpoints clocked by CLK1A or CLK1B into a new group called group1 that has a weight = 2.0:

• group_path -name "group1" -weight 2.0 -to {CLK1A CLK1B}

• Groups all endpoints clocked by CLK into a group with a critical range of 0.5:

• group_path -name CLK -critical_range 0.5 -to CLK

8. Concurrent Clock and Data Optimization:

• In concurrent clock and data optimization technique, it optimizes both data and clock path
concurrently.
• By default, CCD will be performed in compile_fusion.
• To disable CCD => compile.flow.enable_ccd true(default)|false.
• All path groups, boundary paths are considered for useful skew computation (CCD optimization).