Dayalbagh Educational

Institute

Stream Seminar
Topic: FinFet
Anirudh Pratap Singh
2002108
B.Tech (3RD Year)
Electrical (Electronics)
From the
Beginning
Source: - https://spectrum.ieee.org/transistor-timeline
 Year Technology Organization
1947 Point contact Bell Labs
1948 Grown junction Bell Labs
1951 Alloy junction General Electric
1953 Surface barrier Philco
1953 JFET Bell Labs
1954 Diffused base Bell Labs
1954 Mesa Bell Labs
1959 Planar Fairchild
1959 MOSFET Bell Labs

Source:- https://en.wikipedia.org/wiki/History_of_the_transistor#cite_note-2
PLANAR
TRANSISTOR
1. Planar transistors are a type of transistor that use a flat,
planar structure rather than a bulky, three-dimensional
structure.
2. They were first developed in the late 1950s and early
1960s, and were a major advancement in the field of
electronics.
3. Planar transistors are made using a process called
photolithography, which involves shining light through a
mask onto a silicon wafer to create patterns that define
the transistor's structure.
4. Planar transistors come in two main types: NPN and Source:- https://learnabout-electronics.org/Semiconductors/bjt_02.php
PNP, which refer to the type of doping used in the
transistor's base region
 MOSFETs

Source:- https://www.researchgate.net/publication/277095691_Simulation_Analysis_of_Characteristics_of_Quantum-Well_FET
MOSFET Operation and Modes

Source: - Microelectronics Circuits 7th Edition, SEDRA & SMITH

Limitation
of
MOSFET:-
1. SHORT CHANNEL EFFECT
2. LEAKAGE CURRENT
 Short Channel Effect:-
Short-channel effects occur when the channel length is the
same order of magnitude as the depletion-layer widths of
the source and drain junction.
Due to SCE Many Effects comes into action:-
1. Drain-Induced Barrier Lowering (DIBL)
2. Velocity Saturation
3. Mobility Degradation

This effect can be reduced by Reducing Oxide

layer thickness.

Source:- Analytical_Modeling_of_the_Pocket_Implanted_Nano_Scale_n-MOSFETs
Source:- Short-Channel Effects in MOSFETs
 Leakage Current:

“Gate cannot control the

leakage current paths that are far from the
gate.”
- Chenming Hu, August 2011

S.D. Pable, Mohd. Hasan / INTEGRATION, the VLSI journal 45 (2012) 186–
196
 •It is observed that on reducing
channel length, Gate Control over
Source: -B. Yu et al., ISDRS 1997 R.‐H. Yan et al., IEEE TED 1992 15
current is reducing.
•In order to eliminate the above
limitations, There are two approaches.

Source: -B. Yu et al., ISDRS 1997 R.‐H. Yan et al., IEEE TED 1992
15
Double-Gate MOSFET:
“HOW THE FATHER OF FINFETS HELPED
SAVE MOORE’S LAW?”
Chenming Hu, the 2020 IEEE Medal of Honor
recipient

•https://spectrum.ieee.org/how-the-father-
of-finfets-helped-save-moores-law
This is a part of the article published in New York Times on 5 May 2011
 FINFET

Source: - https://www.circuitbread.com/ee-faq/what-isa-finfet
FINFETS Timeline:-
First mass
production of
system-on-chip
Vested Interest products with 10
from Industry nm FinFET
First N‐channel (SRC, AMD, FinFET based 2nm GAA will be
10 nm FinFETs technology by
FinFETs DARPA, etc ) DRAM design launched by intel
Samsung

1999 2001 2004 2011 2022 2028

1998 2000 2002 2005 2016 2024

First P‐channel High‐k/Metal First time INTEL Samsung 1.5 nm nanosheet

15 nm FinFETs commercially introduced 3nm
FinFETs Gate FinFET FinFET
used FinFET with technology GAA
22nm FinFET .
technology.

SOURCE:- KingLiu_2012VLSI-Tshortcourse
FINFET
FABRICATIO
N PROCESS
SOURCE: - https://www.halbleiter.org/en/fundamentals/construction-of-a-finfet/
SOURCE: - https://www.halbleiter.org/en/fundamentals/construction-of-a-finfet/
FIN Design Considerations:-

Fin Height Fin Pitch Fin Width

– Limited by – Determines – Determines
etch technology layout area DIBL
– Tradeoff: – Tradeoff:
layout efficiency performance vs.
vs. design layout efficiency
flexibility

For double-gate: W = 2 ∙ Hfin

For tri-gate: W = 2 ∙ Hfin + T
Multiple fins will increase the transistor width.
Weff = n ∙ W
Where n = number of fins
 https://overclock3d.net/news/gpu_displays/why_are_finfet_transistors_important/1

FinFET vs MOSFET
Source: Planar bulk MOSFETs versus FinFETs
 FinFET vs
MOSFET

Source: Planar bulk MOSFETs versus FinFETs

 FinFET vs
MOSFET

Source: Planar bulk MOSFETs versus FinFETs

 FinFET vs
MOSFET

Source: Planar bulk MOSFETs versus FinFETs

ADVANTAGES

• Better control over the channel

• Suppressed short-channel effects
• Lower static leakage current
• Faster switching speed
• Higher drain current (More drive-current per
footprint)
• Lower switching voltage
• Low power consumption
 DISADVANTAGES
Difficult to control dynamic Vth

Quantized device-width. It is impossible to make fractions of the fins, whereby designers can only
specify the devices’ dimensions in multiples of whole fins.
Higher parasitics due to 3-D profile

Very high capacitances

Corner effect: electric field at the corner is always amplified compared to the electric field at the
sidewall. This can be minimized using a nitrate layer in corners.
High fabrication cost
Application: -
FinFETs offer improved performance and reduced power consumption, making
High-performance computing them well-suited for use in high-performance computing applications such as
data centers, supercomputers, and artificial intelligence.

The high performance and radiation resistance of FinFETs make them well-
Aerospace suited for use in aerospace applications, such as satellites and space probes.

FinFETs' improved electrostatic control and reduced power consumption make

Internet of Things (IoT) them well-suited for use in IoT devices, such as smart sensors and wearables

The high performance and low power consumption of FinFETs make them ideal
Telecommunications for use in telecommunications applications, such as base stations and routers
Current Challenges
• Manufacturing complexity
• The fabrication process for FinFETs is more complex
than that of traditional MOSFETs, which can make
them more expensive to produce
• Heat dissipation
• As FinFETs become smaller and more powerful, there is
a greater need for effective heat dissipation to prevent
overheating and damage to the devices.
• Lithography limitations
• As transistor sizes continue to shrink, there are
limitations in current lithography techniques, which
may require the development of new lithography
techniques
• Scaling limitations
• As FinFETs continue to scale down in size, they may
encounter physical and technological limitations, which
could ultimately limit their performance and usefulness
IS IT
ENOUGH?

WE SAY NO!!
Thank you