VHDL

COE4DI4
Engineering Design and VHDL

Definition of Engineering Design
• The process of devising a system, component, or process to
meet desired needs
Copyright S. Shirani
2
Required product
Design specifications
Initial design
Simulation Redesign
Design correct? No
Yes
Prototype implementation Make corrections
Yes
Testing
Minor errors?
No
Meets specifications? No
Yes
Finished product
The development process 3
Design Process
• Define specifications: essential features of the product are
identified.
– Specifications must be tight enough to ensure that the developed
product will meet the general expectations, but not be unnecessarily
constraining.
• Initial design: is generated from the design specifications
– This step is usually performed by a human designer.
– It requires considerable design experience and intuition.
4
Design Process
• Simulation: CAD tools are used to simulate the behavior of
the initial design to determine whether the obtained design
meets the required specifications.
• If errors are found appropriate changes are made and
verification is repeated through simulation.
• Usually all except subtle problems are discovered in this way.
• When simulation indicated that the design is correct, a
prototype of the product is constructed.
5
Design Process
• The prototype is thoroughly tested for conformance with the
specifications.
• Minor errors are often eliminated by making small corrections
directly on the prototype.
• In the case of large errors, it is necessary to redesign the
product.
6
Design of digital hardware
7
Design concept
A
Partition
B
Design one block Design one block

C
Design interconnection between blocks
Functional simulation of complete system
No
Correct?
Yes D
Physical mapping
Timing simulation
No
Correct?
Yes
Implementation
Figure 1.6 Design flow for logic circuits 8
Implementation
Build prototype
Testing Modify prototype
Yes
No
Correct? Minor errors?
Yes No
Finished Go to A, B, C, or D
Development of a complex digital hardware

9
• A common way of dealing with complexity in digital
hardware is to partition the circuit into smaller blocks and
design each block separately.
• Having successfully designed all blocks, the interconnection
between blocks must be defined.
• The complete circuit is simulated and errors are corrected
• Errors caused by incorrect connections: connections are
redefined (path C)
• Some blocks have not been designed correctly: erroneous
blocks are redesigned (path B)
• Some functionality missing: incorrect partitioning (path A)
10
• Physical mapping: physical location of each chip on the board
and wiring pattern
– CAD tools are relied on
• Does the physical layout affect the performance of the circuit
(even though the functional behavior of complete system is
correct)?
• Physical wiring introduce resistance and capacitance. It may
have an impact on the speed of operation.
• Timing simulation is used to check the performance of the
circuit after wiring.
11
• Having completed timing simulation a prototype of the circuit
is implemented.
• The prototype is tested.
• Minor errors are corrected on the prototype.
• Large problems require a redesign.
12
CAD tools
• A CAD system has tools for performing the following tasks:
– Design entry
– Initial synthesis
– Functional simulation
– Logic synthesis and optimization
– Physical design
– Timing simulation
– Chip configuration
13
Design conception
DESIGN ENTRY
Truth table Schematic capture VHDL
Simple synthesis
Translation
Merge
INITIAL SYNTHESIS TOOLS Boolean equations
Functional simulation
No
Design correct?
Yes
Logic synthesis, physical design, timing simulation
The first stages of a CAD system 14
Design conception
Design entry, initial synthesis, and functional simulation
Logic synthesis/optimization
Physical design
Timing simulation
No Design correct?
Yes
Chip configuration
A complete CAD system 15
CAD tools
• The starting point in the process of designing a digital circuit
is the conception of what the circuit is supposed to do and the
formulation of its general structure.
• This step is done manually. The rest is done by CAD tools.
16
CAD tools
• Design entry: a description of the circuit being designed
should be entered into CAD system
• Different ways of doing this:
– Truth tables
– Schematic capture
– Hardware description languages
• Initial synthesis: produces a network of logic gates
17
CAD tools
• Functional simulation: is used to verify the functionality of
the circuit based on input provided by the designer
• This simulation is performed before any optimization and
propagation delays are ignored.
• Goal: validate the basic operations of the circuit
18
CAD tools
• Logic synthesis and optimization: produces an equivalent but
better circuit
• The measure of what makes one circuit better depends on the
needs of a design project and the technology chosen for
implementation
19
CAD tools
• Physical design (layout synthesis): how to implement the
circuit in the target technology
• This step consists of placement and routing
• Placement: where in the target device each logic function in
the optimized circuit will be realized
• Routing: which wires in the chip are to be used to realize the
required interconnections
20
CAD tools
• Timing simulation: determines the propagation delays that are
expected in the implemented circuit
• Timing simulation: ensures that the implemented circuit
meets the required performance
• Some of timing errors can be corrected by using the synthesis
tool
• If the logic synthesis tool cannot resolve the timing problem,
it is necessary to return to the beginning of the design flow to
consider other alternatives
• Final step: configure the target chip to implement the circuit
21
Summary
• Design and development process
• Design of digital hardware
• CAD tools
22
Design concept
Initial design
Simulation Redesign
No
Design correct?
Yes
Successful design
The basic design loop Copyright S. Shirani

23
Introduction to VHDL
• VHDL (VHSIC Hardware Description Language) is a
language used to express complex digital systems concepts
for documentation, simulation, verification and synthesis.
• VHDL is a language widely used to model and design digital
hardware.
• Design tools translate a design described in VHDL into actual
working system in various target technologies very fast and
reliable.
• VHDL is supported by numerous CAD tools and
programmable logic vendors.
• VHDL was first standardized in 1987 in IEEE 1076-1987
• An enhanced version was released in 1993
24
Introduction
• VHDL has had an enormous impact on digital system design
and methodology
• VHDL promotes a hierarchical top-down design
• It takes the designer away from low level details (e.g.,
transistors and gates) to higher levels (system description)
• VHDL allows design entry in different levels:
– Exp: part of the design at behavioral level and part at the level of
netlist
• Conventional programming languages: sequential operations
• VHDL is designed to model parallel operations (concurrent
events)
25
Introduction
• Advantages of using VHDL for design:
1. Shorter design time and reduced time to market
2. Reusability of already designed units
3. Fast exploration of design alternatives
4. Independence of the target implementation technology
5. Automated synthesis
6. Easy transportability to other design tools
7. Parallelization of the design process using a team work
approach
26
Introduction
• VHDL consists of several parts organized as follows:
1. Actual VHDL language specified by IEEE
2. Some additional data type declarations in the standard
package called IEEE standard 1164
3. A WORK library reserved for user’s designs
4. Vendor packages with vendor libraries
5. User packages and libraries
27
VHDL design
• A VHDL design consists of several design units (building
blocks)
• Each design unit can be compiled into a library for
subsequent simulation or use in other designs
• Four source design units that can be compiled are:
– Entity: describes the design’s interface signals
– Architecture: describes design’s behavior
– Package: stores frequently used specifications such as data types
– Configuration: selects a variation of a design from a library
28
VHDL design
• Two built-in libraries are WORK and STD
• VHDL source design units are complied into WORK library
• The ieee library is a storage place for IEEE standard design
units
• User can create other libraries
29
VHDL design (Library)
• To use a library it should be declared (made accessible to the
design):
– Exp: library ieee
• WORK library is implicitly accessible in all designs and does
not need to be declared
• Complied units in a library can be accessed via a use
statement
• Syntax:
– use library_name.package_name.item_name
– use library_name.item_name
• Exp: use ieee.std_logic_1164.all
30
VHDL design (Package)
• Next level of hierarchy within a library is a package.
• Package is created to store common data types, constants and
complied designs that will be used in more than one design
(reusability)
• A package is used for:
– Type and subtype declaration
– Constant declaration
– Function and procedure declaration
– File declaration
31
VHDL design (Package)
• All vendors provide a package named STANDARD in a
predefined library named STD. This package defines useful
data types
• A use clause allows access to a package in a library
• Syntax:
– use library_name.package_name.item_name
– use library_name.item_name
• Exp: use ieee.std_logic_1164.all
• No use clause is required for the package STANDARD (it is
default)
32
Entity & Architecture
• A VHDL design is a paring of an entity declaration and an
architecture body.
• Entity declaration: describes the design I/O and my include
parameters used to customize an entity
• Architecture body: describes the function of a design
• Each I/O signal in an entity declaration is referred to as a port
• A port is a data object
• Like other data objects it can be assigned values and used in
expressions
33
• Each port must have a name, a direction (mode) and a data
type.
• Mode: describes the direction in which data is transferred
through a port
• Example: port (a, b : in bit_vector(3 downto 0);
equals: out bit);
• Mode can be one of 4 values: in, out, inout, or buffer
• In: data flows only into the entity. The driver of the port is
external (e.g., clock input)
• Out: data flows only from its source (inside the entity) to the
port
• Note: out does not allow feedback
34
• Buffer: for internal feedback (to use a port also as a driver
within the architecture)
• Buffer is used for ports that must be readable inside the entity,
such as the counter outputs (the present state of a counter
must be used to determine its next stage
• Inout: allows data to flow into or out of the entity. It also
allows for internal feedback
• Mode inout can replace any of the other modes
35
• In addition to specifying modes for ports, you must declare
data types for ports
• The most important data types in VHDL are Boolean, bit,
bit_vector, and integer
• The most useful types provided by the IEEE std_logic_1164
package is std_logic and array of this type.
• For simulation and synthesis software to process these types,
their declaration must be made visible to the entity by way of
library and use clauses
36
entity eqcomp4 is
port (a, b : in bit_vector(3 downto 0);
equals: out bit);
end eqcomp4;
architecture dataflow of eqcomp4 is
begin
equals <=‘1’ when (a=b) else ‘0’;
end dataflow;
37
VHDL design (Entity)
• Design entity defines a new component name, its input/output
connections and describes parameterized values.
• Entity represents the I/O interface (external connections) of a
component.
ANDGATE
A C
B
entity andgate is
port (a,b : in bit;
c: out bit);
end andgate
38
VHDL design (Entity)
•Syntax for an entity declaration:
entity entity_name is
[generic (list-of-generics-and-their-types);]
[port (list-of-interface-port-names-and-their-
types);]
[begin entity-statements]
end [entity] entity-name;
• Generic list: allows additional information to pass into an

entity
• Useful for parameterization of the design
39
VHDL design (Architecture)
• An architecture specifies the behavior, interconnections and
components of an entity.
• Architecture defines the function of an entity
• It specifies the relationship between inputs and outputs.
• VHDL architectures are categorized in style as:
1. Behavior
2. Dataflow
3. Structural
• A design can use any or all of these styles.
40
• Behavior: the behavior of the entity is expressed using
sequentially executed procedural code (very similar to
programming languages like C)
• Sometimes called high-level description
• Rather than specifying the structure of a circuit, you specify a
set of statements that when executed in sequence model the
behavior of the entity.
• Uses process statement and sequential statements (the
ordering of statements inside process is important)
41
• Dataflow: specifies the functionality of the entity (the flow of
information) without explicitly specifying its structure
• It specifies how data will be transferred from signal to signal
and input to output without the use of sequential statements.
• No use of process or sequential statements
• Structural: an entity is modeled as a set of components
connected by signals
• Components are instantiated and connected together
42
-- a four bit equality comparator
library ieee;
use iee.std_logic_1164.all;
entity eqcomp4 is
port (a, b : in std_logic_vector(3 downto 0);
equals: out std_logic);
end eqcomp4;
architecture behav of eqcomp4 is
begin
comp: process (a, b);
begin
if a=b then
equals <= ‘1’;
else
equals<=‘0’;
end if;
end process comp;
end behav;
43
library ieee;
entity eqcomp4 is
end eqcomp4;
architecture dataflow of eqcomp4 is

begin
equals <=‘1’ when (a=b) else ‘0’;
end dataflow;
44
library ieee;
entity eqcomp4 is
end eqcomp4;
architecture bool of eqcomp4 is

begin
equals <= not(a(0) xor b(0))
and not(a(1) xor b(1))
and not(a(2) xor b(2))
and not(a(3) xor b(3)) ;
end bool;
45
library ieee;
library altera;
use altera.quartus.all;
entity eqcomp4 is port (a, b : in std_logic_vector(3 downto 0);

end eqcomp4;
architecture struct of eqcomp4 is
signal x: std_logic_vector(0 to 3);
begin
u0: xnor port map (a(0),b(0),x(0));
u4: and4 port map(x(0), x(10, x(2), x(3), equals);
end struct;
46
VHDL
• VHDL does not assume any precedence of operation and
therefore parentheses are necessary in VHDL expressions.
• <= is the signal assignment operator in VHDL
47
x1
x3
x2
x4
Logic circuit for four-input function
48
Whenever there is an event on x1, x2, x3, the
expression on the right side is evaluated and the value
appears on f and/or g.
Figure 2.30 VHDL code for a four-input functionCopyright S. Shirani

49
Example
• The signal assignments in the previous example are
concurrent statements.
• Concurrent statements are order independent.
50
VHDL
• A very useful data type defined in VHDL: STD_LOGIC
• STD_LOGIC can have a number of legal values: 0, 1, z, -
• To use STD_LOGIC type the VHDL code must have these
two lines:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
• The first line declares that the code will use ieee library
51
xi yi
ci 00 01 11 10
0 1 1
ci xi yi ci +1 si
1 1 1
0 0 0 0 0
0 0 1 0 1
si = x i  y i  c i
0 1 0 0 1
0 1 1 1 0 xi yi
1 0 0 0 1
ci 00 01 11 10
1 0 1 1 0
1 1 0 1 0 0 1
1 1 1 1 1
1 1 1 1
(a) Truth table

ci + 1 = xi yi + xici + yici
(b) Karnaugh maps
xi
yi si
ci
ci + 1
(c) C ircuit
Figure5.4 Full-adder 52
LIBRARY ieee ;
USE ieee.std_logic_1164.all ;
ENTITY fulladd IS
PORT ( Cin, x, y : IN STD_LOGIC ;
s, Cout : OUT STD_LOGIC ) ;
END fulladd ;
ARCHITECTURE LogicFunc OF fulladd IS

BEGIN
s <= x XOR y XOR Cin ;
Cout <= (x AND y) OR (Cin AND x) OR (Cin AND y) ;
END LogicFunc ;
Figure 5.23 VHDL code for the full-adder Copyright S. Shirani

53
VHDL
• Now if we want to create a 4-bit adder we can use the 1-bit
adder already designed as a sub-circuit.
• This is an important feature of VHDL which makes the reuse
of entities possible.
• components: design entities used in other designs
• Before an entity can be used in another design it has to be
declared
• A component declaration defines an interface for instantiating
a component.
54
VHDL
• A component declaration may be
1. in a package: the package is made accessible by use statement
2. might be declared in an architecture declarative region using
component statement
• Every time a component is used it has to be instantiated
• Every instantiation has a name.
55
LIBRARY ieee ;
ENTITY adder4 IS
PORT ( Cin : IN STD_LOGIC ;
x3, x2, x1, x0 : IN STD_LOGIC ;
y3, y2, y1, y0 : IN STD_LOGIC ;
s3, s2, s1, s0 : OUT STD_LOGIC ;
Cout : OUT STD_LOGIC ) ;
END adder4 ;
ARCHITECTURE Structure OF adder4 IS

SIGNAL c1, c2, c3 : STD_LOGIC ;
COMPONENT fulladd
PORT ( Cin, x, y : IN STD_LOGIC ;
s, Cout : OUT STD_LOGIC ) ;
END COMPONENT ;
BEGIN
stage0: fulladd PORT MAP ( Cin, x0, y0, s0, c1 ) ;
stage1: fulladd PORT MAP ( c1, x1, y1, s1, c2 ) ;
stage2: fulladd PORT MAP ( c2, x2, y2, s2, c3 ) ;
stage3: fulladd PORT MAP (
Cin => c3, Cout => Cout, x => x3, y => y3, s => s3 ) ;
END Structure ;
Figure 5.24 VHDL code for a four-bit adder Copyright S. Shirani

56
Data objects
• Data objects: hold values of specific types
• Data objects belong to one of four classes: constant, signals,
variables, or files
• Constant: holds a value that cannot be changed within the
design
• Exp: width of a register
– constant width: integer :=8;
• := indicates immediate assignment
• Constant can be declared in package, entity, architecture, or
process
– Defined in a package: can be referenced by any entity or architecture
for which the package is used
57
Data objects
– Defined in an entity declaration is visible only within the entity
– Defined in an architecture is visible only to the architecture
– Defined in a process declarative region is visible only to that process
• Signals: represent wires, and therefore interconnect
components
• Ports are signals
– signal count: bit_vector(3 downto 0);
58
Data objects
• Variables: used only in processes, functions and procedures
• Unlike signals variables do not represent wires
• They are usually used for computational purposes in high
level modeling (e.g., index, temporary storage of data)
• Usually we avoid using them
• Files: contain values of a specific type
59
Variables
• Operator for variable assignment is :=
• Signal assignment generally results in a latch
• Variable assignment generally is synthesized to a node (a
wire)
• In short, signal assignment has a delay and variable
assignment has no delay
60
Common mistake
process(i0,i1,a) process(i0,i1,a)
begin variable muxval :integer;
muxval <=0; begin
if (a =‘1’) then muxval :=0;
muxval <=muxval +1; if (a =‘1’) then
end if; muxval :=muxval +1;
case muxval is end if;
when 0 => case muxval is
q<=i0; when 0 =>
when 1 q<=i0;
q<=i1; when 1
when others => q<=i1;
null; when others =>
end case null;
end process end case
end process
61
Data types
• VHDL is a strongly typed language: data objects of different
types cannot be assigned to one another without use of type-
conversion
• Besides predefined types (e.g., BIT, STD_LOGIC) user can
define their own types in VHDL.
• The command for this purpose is type
• Example:
type DIGIT is (‘0’,’1’,’2’,’3’,’4’,’5’,’6’,’7’,’8’,’9’);
• A subtype is a type with a constraint
• Example:
subtype MIDDLE is DIGIT range ’3’ to ’7’;
62
Data types
• Arrays of predefined or user defined types can be introduced.
• Example:
– type ADDRESS_WORD is array (0 to 63) of BIT
– type DATA_WORD is array (7 downto 0) of STD_LOGIC
• In the first example ADDRESS_WORD(0) is the most
significant bit and in the second one DATA_WORD(7) is the
most significant bit.
• There is a predefined array type in ieee library:
STD_LOGIC_VECTOR
• It can be used for presentation of multibit signals.
63
Data types
• An array object can be assigned to another array object of the
same type.
• Assignment can be made to an entire array, or to an element
or to a slice.
• Example:
SIGNAL X: STD_LOGIC_VECTOR(3 to 0)
X <=“1100”
X(3) <=‘0’
X(2 to 0) <=“101”
64
Data types
• Now that we have multibit signals we are able to represents
numbers.
• Are we able to perform arithmetic operations on the numbers
in VHDL?
• Another package named std_logic_arith defines types for this
• Two predefined types in this package: SIGNED and
UNSINGED
• SIGNED and UNSIGNED are the same as
STD_LOGIC_VECTOR
• SIGNED represents signed integer data in two’s complement
form
• UNSIGNED represents unsigned integer data in the form of
an array of std_logic
65
Arithmetic operations
std_logic_signed
STD_LOGIC_VECTOR
std_logic_arith
SIGNED UNSINGED
std_logic_unsigned
STD_LOGIC_VECTOR
66
LIBRARY ieee ;
USE ieee.std_logic_arith.all ;
ENTITY adder16 IS
PORT ( Cin : IN STD_LOGIC ;
X, Y : IN SIGNED(15 DOWNTO 0) ;
S : OUT SIGNED(15 DOWNTO 0) ;
Cout, Overflow : OUT STD_LOGIC ) ;
END adder16 ;
ARCHITECTURE Behavior OF adder16 IS

SIGNAL Sum : SIGNED(16 DOWNTO 0) ;
BEGIN
Sum <= ('0' & X) + Y + Cin ;
S <= Sum(15 DOWNTO 0) ;
Cout <= Sum(16) ;
Overflow <= Sum(16) XOR X(15) XOR Y(15) XOR Sum(15) ;
END Behavior ;
Figure 5.30 Use of the arithmetic package Copyright S. Shirani

67
4-bit up-down counter
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter is port (clk, clr, load, up, down: in std_logic; data: in std_logic_vector(3
downto 0); count: out std_logic_vector(3 downto 0));
end counter;
architecture count4 of counter is

signal cnt: std_logic_vector(3 downto 0);
begin
process (clr, clk)
begin
if clr=‘1’ then cnt<=‘0000’;
elsif clk’event and clk=‘1’ then
if load=‘1’ then cnt<=data
elsif up=‘1’ then
68
cnt<=cnt+1;
elsif down=‘1’ then
cnt<=cnt-1;
else
cnt<=cnt;
end if;
end if;
count<=cnt;
end process;
end count4;
69
Selective signal assignment
• Selected signal assignment is used to assign one of multiple
values to a signal, based on some criteria.
• The WITH-SELECT-WHEN structure can be used for this
purpose.
• Syntax: with selection_signal select
signal_name <= value_a when value1_of_selection_signal,
value_b when value2_of_selection_signal,
value_c when value3_of_selection_signal;
• All values of selection_signal must be listed in the when
clause
• We can use the word OTHERS to cover some of the values
70
LIBRARY ieee ;
ENTITY mux2to1 IS
PORT ( w0, w1, s : IN STD_LOGIC ;
f : OUT STD_LOGIC ) ;
END mux2to1 ;
ARCHITECTURE Behavior OF mux2to1 IS

BEGIN
WITH s SELECT
f <= w0 WHEN '0',
w1 WHEN OTHERS ;
END Behavior ;
Figure 6.27 VHDL code for a 2-to-1 multiplexer Copyright S. Shirani 71

Conditional signal assignment
• Conditional signal assignment is used to assign one of
multiple values to a signal, based on some criteria.
• The WHEN ELSE structure can be used for this purpose.
• Syntax:
signal_name <= value_a when condition1 else
value_b when condition2 else
value_c when condition3 else
value_d;
72
LIBRARY ieee ;
USE ieee.std_logic_unsigned.all ;
ENTITY compare IS
PORT ( A, B : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;
AeqB, AgtB, AltB : OUT STD_LOGIC ) ;
END compare ;
ARCHITECTURE Behavior OF compare IS

BEGIN
AeqB <= '1' WHEN A = B ELSE '0' ;
AgtB <= '1' WHEN A > B ELSE '0' ;
AltB <= '1' WHEN A < B ELSE '0' ;
END Behavior ;
Figure 6.34 VHDL code for a four-bit comparatorCopyright S. Shirani 73

Concurrent statements
• Assignment statements, selected assignment statements and
conditional assignment statements are called concurrent
statements because the order in which they appear in VHDL
code does not affect the meaning of the code
• Concurrent statements are executed in parallel.
• Each concurrent statement is a different hardware element
operating in parallel.
74
VHDL
• Syntax of architecture body
architecture architecture_name of entity_name is
[architecture_item_declaration]
begin
concurrent_statements
process_statement
block_statement
concurrent_procedure_call_statement
component_instantiation_statement
generate_statement
end
75
Sequential statements
• Sequential statements: ordering of statements may affect the
meaning of the code
• Sequential statements should be placed inside process
statement.
76
Process
[process_label:] process [(sensitivity_list)] [is]
[process_item_declaration]
begin
sequential_statements; these are
variable_assignment
signal_assignment
wait_statement
if_statement
case_statement
loop_statement
null_statement
exit_statement
next_statement
report_statement
return_statement
end process [process_label]
77
Process
• Sensitivity list: signals to which the process is sensitive
• Each time an event occurs on any of the signals in sensitivity
list, the sequential statements within the process are executed
in the order they appear
78
If statement
• An if statement selects a sequence of statements for execution
based on the value of a condition
• Syntax:
If condition1 then
sequential_statements
[elsif condition2 then
sequential_statements]
[else
sequential_statements]
end if
79
LIBRARY ieee ;
ENTITY mux2to1 IS
PORT ( w0, w1, s : IN STD_LOGIC ;
f : OUT STD_LOGIC ) ;
END mux2to1 ;
ARCHITECTURE Behavior OF mux2to1 IS

BEGIN
PROCESS ( w0, w1, s )
BEGIN
IF s = '0' THEN
f <= w0 ;
ELSE
f <= w1 ;
END IF ;
END PROCESS ;
END Behavior ;
A 2-to-1 multiplexer specified using an if-then-else statement
80
Case
• Syntax:
case selection_signal is
when value1_selection_signal => sequential_statements
when value2_selection_signal => sequential_statements
..
[when others => sequential_statements]
end case
81
LIBRARY ieee ;
ENTITY seg7 IS
PORT ( bcd : IN STD_LOGIC_VECTOR(3 DOWNTO 0) ;
leds : OUT STD_LOGIC_VECTOR(1 TO 7) ) ;
END seg7 ;
ARCHITECTURE Behavior OF seg7 IS
BEGIN
PROCESS ( bcd )
BEGIN
a
CASE bcd IS -- abcdefg
WHEN "0000" => leds <= "1111110" ; f b
WHEN "0001" => leds <= "0110000" ; g
WHEN "0010" => leds <= "1101101" ;
WHEN "0011" => leds <= "1111001" ; e c
WHEN "0100" => leds <= "0110011" ;
WHEN "0101" => leds <= "1011011" ; d
WHEN "0110" => leds <= "1011111" ;
WHEN "0111" => leds <= "1110000" ;
WHEN "1000" => leds <= "1111111" ;
WHEN "1001" => leds <= "1110011" ;
WHEN OTHERS => leds <= "-------" ;
END CASE ;
END PROCESS ;
END Behavior ;
Figure 6.47 A BCD-to-7-segment decoder Copyright S. Shirani
82
L IB R A R Y IE E E ;
U S E IE E E .S T D _ L O G IC _ 1 1 6 4 .A L L ;
E N T I T Y m u lt ip le x e r I S - - I n p u t S ig n a ls a n d M u x C o n t r o l
P O R T ( A , B , M u x _ C o n tro l : IN S T D _ L O G IC ;
M u x _ C o n tro l
M u x _ O u t1 , M u x _ O u t2 ,
M u x _ O u t3 , M u x _ O u t4 : O U T S T D _ L O G IC );
A 0
E N D m u lt ip le x e r ;
M u x _ O u tx
B 1
A R C H I T E C T U R E b e h a v io r O F m u lt ip le x e r I S
B E G IN - - s e le c t e d s ig n a l a s s ig n m e n t s t a t e m e n t …
M u x _ O u t 1 < = A W H E N M u x _ C o n t r o l = '0 ' E L S E B ;

- - … w it h S e le c t S t a t e m e n t
W IT H m u x _ c o n tro l S E L E C T
M u x _ O u t2 < = A W HEN '0 ',

B W HEN '1 ',
A W HEN OTHERS; - - O T H E R S c a s e r e q u ir e d s in c e S T D _ L O G I C
-- h a s v a lu e s o t h e r t h a n " 0 " o r " 1 "
P R O C E S S ( A , B , M u x _ C o n t r o l)
B E G IN - - S t a t e m e n t s in s id e a p r o c e s s
I F M u x _ C o n t r o l = '0 ' T H E N -- e x e c u t e s e q u e n t ia lly .
M u x _ O u t3 < = A ;
ELSE
M u x _ o u t3 < = B ;
E N D IF ;
C A S E M u x _ C o n tro l IS
W H E N '0 ' = >
M ux_O u t4 < = A ;
W H E N '1 ' = >
M ux_O u t4 < = B ;
W HEN OTHER S =>
M ux_O u t4 < = A ;
END CASE;
END PROCESS;
E N D b e h a v io r ;
83
Combinational logic implementation
• Combinational logic circuits can be modeled in different
ways:
– Using signal assignment statements (which include expressions with
logic, arithmetic and relational operators)
– Using if and case statements
84
Logic operators
• Standard VHDL logical operators are defined for types bit,
std_logic, Boolean and their arrays.
Library ieee;
Use ieee.std_logic_1164.all;
Entity logic_operators_1 is
Port(a, b, c, d, : in std_logic; y: out std_logic);
End logic_operators_1;
Architecture arch1 of logic_operators_1 is
Signal e:bit;
Begin
y <=(a and b) or e;
e <= c or d;
End arch1;
85
Conditional Logic
• Concurrent statements for creating conditional logic:
– Conditional signal assignment
– Selected signal assignment
• Sequential statements for creating conditional logic:
– If statement
– Case statement
86
Conditional Logic
Library ieee;
Entity condit_stmt is Port(

sel, b, c: in boolean;
y: out boolean);
End condit_stmt;
Architecture concurrent of condit_stmt is

Begin
y <=b when sel else c;
End concurrent;
87
Conditional Logic
• The same function implemented using sequential statements
Library ieee;
Entity condit_stmt is Port(
sel, b, c: in boolean;
y: out boolean);
End condit_stmt;
Architecture sequential of condit_stmt is
begin
Process(s,b,c)
begin
if sel then
y <=b;
else
y <=c;
end if;
end process;
end sequential;
88
Three-state (tri-state) logic
• When data from multiple possible sources need to be
directed to one or more destinations we usually use either
multiplexers or three-state buffers.
• Output buffers are placed in a high impedance state so they
do not drive a shared bus at the wrong time
• Bidirectional pins are placed in high impedance state so they
are not driven by off-chip signals at the wrong time
• VHDL provides two methods to describe three-state buffers:
1. Using the ‘Z’ (high impedance) which applies to the type std_logic
2. Using an assignment of null to turn off a driver. This applies to any
type.
89
Library ieee;
Entity tbuf4 is Port(
enable: in std_logic;
a: in std_logic_vector(0 to 3);
y: out std_logic_vector(0 to 3));
End tbuf4;
Architecture arch1 of tbuf4 is
Begin
Process(enable, a)
begin
if enable=‘1’ then
y<=a;
else
y<=‘Z’;
end if;
end process
End arch1;
90
The same function implemented using concurrent
statements
Library ieee;
enable: in std_logic;
a: in std_logic_vector(0 to 3);
y: out std_logic_vector(0 to 3));
End tbuf4;
Begin
y <=a when enable=‘1’ else ‘Z’;
End arch2;
91
• Another way to model three-state buffers is to use the assignment of null to a
signal to turn off its derives.
Library ieee;
Package pack_bus is
subtype bus8 is integer range 0 to 255;
End pack_bus;
Use work.pack_bus.all;
enable: in std_logic; a: in bus8;
y: out bus8);
End tbuf8;
Begin
process(enable, a)
begin
y <=a ;
else
y<= null;
end if;
end process
End arch1;
92
Relational Operators
• Relational operators are = ,/= , >=, <=, >, <.
• The resulting type for all these operators is Boolean
• Equal and not equal are cheaper to implement (in terms of
gates) than the ordering operators.
93
Library ieee;
Entity relat_operators is Port(
a, b : in integer range 0 to 15 ;
y: out boolean);
End relat_operators;
Architecture arch2 of relat_operators is
Begin
y <= a >= b;
End arch2;
94
• Relational operators might be used in connection with conditional signal
assignment
Library ieee;
Use ieee.std_logic_ungined.all;
Entity compare is Port(
a : in unsgined(3 downto 0);
x: out std_logic);
End compare;
Architecture compare of compare is
Begin
x <= ‘1’ when a=3 else ‘0’;
End compare;
95
Arithmetic Operators
• Adding operators (+,-) are fairly expensive (in terms of number of gates)
• Multiplying operators (*,/,mod, rem) are very expensive.
• They are not supported on many VHDL synthesis tools.
• In Quartus II, only multiply and divide by integers are supported
• Mod and Rem are not supported
• Implementation is highly dependent to the target technology
Library ieee;
Use ieee.std_logic_unsigned.all;
Entity arith_operators is
Port(a, b, c, d : in unsigned (7 downto 0); y: out unsigned (9 downto 0));
End arith_operators;
Architecture arch2 of relat_operators is
Begin
y <= a+b+c+d;
End arch2;
96
Wait
• When a process has a sensitivity list it is always suspended
after executing the last statement in the process
• Wait is an alternative way of suspending a process
• Syntax:
wait on sensitivity_list
wait until boolean_expression;
wait for time_expression;
97
LIBRARY ieee ;
ENTITY flipflop IS
PORT ( D, Clock : IN STD_LOGIC ;
Q : OUT STD_LOGIC) ;
END flipflop ;
ARCHITECTURE Behavior OF flipflop IS

BEGIN
PROCESS ( Clock )
BEGIN
IF Clock'EVENT AND Clock = '1' THEN
Q <= D ;
END IF ;
END PROCESS ;
END Behavior ;
Figure 7.38 Code for a D flip-flop Copyright S. Shirani

98
LIBRARY ieee;
USE ieee.std_logic_1164.all;
ENTITY flipflop IS
PORT ( D, Clock : IN STD_LOGIC ;
Q : OUT STD_LOGIC ) ;
END flipflop ;
ARCHITECTURE Behavior OF flipflop IS

BEGIN
PROCESS
BEGIN
WAIT UNTIL Clock'EVENT AND Clock = '1' ;
Q <= D ;
END PROCESS ;
END Behavior ;
Figure 7.39 Code for a D flip-flop using WAIT UNTIL

99
Sequential Logic Synthesis
• Sequential logic elements: latch, flip-flop, register, counter
• Behavior of sequential logic elements can be described using a process
statement
• The sequential nature of process statements make them idea for the
description of circuits that have memory and must save their state over
time
• The design of sequential logic uses one or more of the following rules:
1. A process that does not include all entity inputs in the sensitivity list
(otherwise the combinational circuit will be inferred)
2. Use incompletely specified if-then-elsif logic to imply that one or more
signals must hold their values under certain conditions
3. Use one or more variables in such a way that they must hold a value between
iterations of the process
100
Basic Sequential Logic
• Two most basic types of synchronous elements:
1. D-type latch
2. D-type flip-flop
• D-type latch: a level sensitive memory element that passes
the input (D) to output (Q) when enabled (ENA=1) and hold
the value of the output when disabled (ENA=0)
• D-type flip-flop: an edge-triggered memory element that
transfers the input (D) to output (Q) when an active edge
transition occurs on its clock. The output value is held until
the next active clock edge
• Active clock edge: transition of clock from 0 to 1
101
• Conditional specification is the most common method in
describing behavior of basic memory elements
• This relies on an if statement and assigning a value in only
one condition
• Example: a D latch
process(enable)
begin
q <=d;
end if;
end process
• If we had assigned values in both conditions the behavior
would be a multiplexer
102
• Exp: Edge triggered flip-flop
process(clk)
begin
if (clk and clk’event) then
q <=d;
end if;
End process
• The second method is to use a wait statement
wait until clk and clk’event
q <=d;
103
• Latches can have additional inputs such as preset and clear.
• Preset and clear inputs to the latch are always asynchronous.
• Exp: a latch with active high preset and clear
Library ieee;
Entity latch is
Port(enable, clear, preset, d : in std_logic; q:out std_logic);
End latch;
Architecture arch2 of latch is
Begin
process(enable, preset, clear)
begin
if (clear = ‘1’) then
q <=‘0’;
elsif (preset=‘1’)
q <=‘1’;
elsif (enable=‘1’)
q <=d;
end if;
End process;
End arch2;
104
• Registers can be implemented using if statement or wait statement
• They can have any combination of clear, preset and enable
• Exp: register with edge-triggered clock and asynchronous load
Library ieee;
Entity reg is
Port(load, clk, d, data : in std_logic; q:out std_logic);
End reg;
Architecture arch1 of reg is
Begin
process(load, clk)
begin
if (load = ‘1’) then
q <=data;
elsif clk’event and clk=‘1‘
q <=d;
end if;
end process
End arch1;
105
• Counters can be implemented with if and wait statements
• Exp: an 4-bit, synchronous load, up-down counter
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity counter is port (clk, clr, load, up, down: in std_logic; data: in std_logic_vector(3 downto 0); count: out
std_logic_vector(3 downto 0));
end counter;
architecture count4 of counter is

signal cnt: std_logic_vector(3 downto 0);
begin
process (clr, clk)
begin
if clr=‘1’ then cnt<=‘0000’;
elsif clk’event and clk=‘1’ then
if load=‘1’ then cnt<=data
elsif up=‘1’ then
106
if cnt=‘1111’ then cnt <=‘0000’;
else cnt<=cnt+1;
endif
elsif down=‘1’ then
if cnt=‘0000’then cnt<=‘1111’;
else cnt<=cnt-1;
end if
else
cnt<=cnt;
end if;
end if;
count<=cnt;
end process;
end count4;
107
Finite-State Machine
• Finite State Machines (FSMs) represent an important part of
design of almost any complex digital system.
• FSMs are used to sequence specific operations, control other
logic circuits, and provide synchronization of different parts
of more complex circuits.
• FSM is a circuit that is designed to sequence through specific
patterns of states in a predetermined manner.
• Sequence of states through which an FSM passes depends on
the current state of the FSM and the input
• A state is represented by the binary value held on the current
state register
• FSM is clocked from a free running clock source
108
• FSM contains three main parts:
1. Current state register: holds the current state of FSM (the
current state should be represented in binary form)
2. Next state logic: a combinational logic used to generate the
transition to the next state from the current state
– The next state is a function of current state and inputs to FSM
– A feedback mechanism is necessary in FSM
3. Output logic: a combinational circuit used to generate output
signals from the FSM.
• Outputs are a function of the current state and possibly FSM’s input
109
Next State Logic Current State Output Logic

(combinational) (combinational)
Register output
input
clk
110
• If the output is a function of only the current state: Moore
FSM
• If the output depends on the input and state: Mealy FSM
• Behavior of an FSM is usually described either in the form of
a state transition table or a state transition diagram.
111
• To describe a FSM, an enumeration type for states, and a
process statement for the state register and the next-state logic
can be used.
• Example:
Input=0
s0 s1
reset
Input=1
112
Library ieee;
Entity sm is
Port(clk, reset, input : in std_logic; output: out std_logic);
End sm;
Architecture arch of state_machine is
Type state_type is (s0, s1);
Signal state: state_type;
Begin
Process(clk, reset)
Begin
If reset=‘1’ then state <=s0;
Elsif (clk’event and clk=‘1’) then
Case state is
When s0 =>
state <= s1;
When s1 =>
If input=‘0’ then state <=s1;
Else state <=s0;
End if;
End case;
End if;
End process;
Output <=‘1’ when state=s1 else ‘0’;
End arch;
113
• An important issue when designing FSMs is state encoding:
assignment of binary numbers to states.
• For small designs or those in which there are not too tight
constraints in terms of resources, the common way is to let
the synthesis tool encode the state automatically.
• For bigger designs a kind of manual intervention is necessary
• Sequential state encoding: increasing binary numbers are
assigned to the states
– Exp: s0=“00”, s1=“01”, s2=“10”,
• Gray code or Johnson state encoding are other options.
• One-hot encoding: each state is assigned its own flip-flop, in
each state only one flip-flop can have value ‘1’.
114
• One-hot encoding is not optimal in terms of number of flip-
flops, but used very often by FPLD synthesis tools.
• Reasons:
– FPLDs have a high number of flip-flops available,
– A large number of flip-flops used for state representation leads to a
simpler next state logic.
115
Moore Machines
• Moore state machine: outputs are a function of current state
only
Next State Logic Output Logic d

Current State
Register c
b
a
clk
116
Moore Machines (pseudo code)
Entity system is
Port (clk: std_logic; a: some_type; d: out some_type);
End system
Architecture moore1 of system is
Signal b,c: some_type;
begin
Next_state: process (a,c)
begin
b <=next_state_logic(a,c);
end process next_state;
State_reg: process(clk)
begin
if (clk’event and clk=‘1’) then
c<=b;
end process state_reg;
System_output: process(c)
begin
d<=output_logic(c)
end process system_output
end moore1
117
Mealy Machines
• Mealy state machine: outputs are a function of current state
and system inputs both
Next State Logic Output Logic d

Current State
Register c
b
a
clk
118
Mealy Machines (pseudo code)
Entity system is
Port (clk: std_logic; a: some_type; d: out some_type);
End system
Architecture mealy1 of system is
Signal b,c: some_type;
begin
next_state: process (a,c)
begin
b <=next_state_logic(a,c);
end process next_state;
system_output: process(a,c)
begin
d<=output_logic(a,c)
end process system_output
state_reg: process (clk)
begin
if (clk’event and clk=‘1’) then
c<=b;
end process state_reg;
end mealy1
119
Integer types
• Integer type: a type whose set of values fall within a specified
integer range
• Exp:
– Type index is integer range 0 to 15
– Type word_length is range 31 downto 0;
• Values belonging to an integer type are called integer literals
• The underscore character can be used freely in writing integer
literals and has no impact on the value of a literal
• Exp: 98_71_28 is the same as 987128
120
Type conversion
• to_stdlogicvector(bit_vector): converts a bit vector to a
standard logic vector
• example: to_stdlogicvector(X”FFFF”)
• conv_std_logic_vector(integer, bits): converts an integer to a
standard logic vector
• example: conv_std_logic_vector(7,4) generates “0111”
• conv_integer(std_logic_vector): converts a standard logic
vector to an integer
• example: conv_integer(“0111”) produces 7
121
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY memory IS
PORT( read_data : OUT STD_LOGIC_VECTOR( 7 DOWNTO 0 );
read_address : IN STD_LOGIC_VECTOR( 2 DOWNTO 0 );
write_data : IN STD_LOGIC_VECTOR( 7 DOWNTO 0 );
write_address : IN STD_LOGIC_VECTOR( 2 DOWNTO 0 );
Memwrite : IN STD_LOGIC;
Clock : IN STD_LOGIC );
END memory;
ARCHITECTURE behavior OF memory IS

-- define new data type for memory array
TYPE memory_type IS ARRAY ( 0 TO 7 ) OF STD_LOGIC_VECTOR( 7 DOWNTO 0 );
SIGNAL memory : memory_type;
BEGIN
-- Read Memory and convert array index to an integer with CONV_INTEGER
read_data <= memory( CONV_INTEGER( read_address( 2 DOWNTO 0 ) ) );
PROCESS -- Write Memory?

BEGIN
WAIT UNTIL clock 'EVENT AND clock = '1';
IF ( memwrite = '1' ) THEN
-- convert array index to an integer with CONV_INTEGER
memory( CONV_INTEGER( write_address( 2 DOWNTO 0 ) ) ) <= write_data;
END IF;
END PROCESS;
END behavior;
122
Altera’s VHDL (Quartus)
Package Library Content
maxplus2 altera Quartus primitives and macrofunctions
std_logic_1164 ieee Standard for VHDL modeling and the std_logic and
std_logic_vector types
std_logic_arith ieee Singed and unsigned types, arithmetic and comparison
functions for use with singed and unsigned types and
the conversion functions conv_integer conv_singed,
conv_unsigned
std_logic_signed ieee Functions to use std_logic_vector types as if they are

singed types
std_logic_unsigned ieee Functions to use std_logic_vector types as if they are

unsinged types
lpm_components lpm LPM megafunctions supported by VHDL.
123
Library of commonly used circuits
• Primitives: basic functional blocks used in circuit design
• Macrofunctions: collection of high-level building blocks that
can be used in logic designs
• Macrofunction usual names have the prefix a_ due to the fact
that VHDL does not support names that begin with digits.
124
Primitives
• Primitives:
– Basic building blocks
– Package: maxplus2
– Library: altera
Primitive Primitive Name
Buffer Carry, Cascade, Exp, Global, Lcell, Soft,

Tri
Flip-Flop & latch dff, dffe, jkff, KJFFF, SRFF, SRFFE, TFF,
TFFE, latch
Input and outputs INOUT, IN, OUT
Logic AND, NOR, BAND, NOT, BNAND, OR,

BNOR, XOR,…..
125
Macrofunctions
• Macrofunctions:
– Collection of high-level building blocks that can be used in logic
designs
– All input ports have default signal values, so the designer can simply
leave unused inputs unconnected
– Macrofunction usual names have the prefix a_ due to the fact that
VHDL does not support names that begin with digits.
126
Macrofunctions
Macrofunction Name Description
Adder a_8fadd 8 bit full adder

a_7480 Gated full adder
a_74283 4 bit full adder with fast carry
Arithmetic logic unit a_74181 Arithmetic logic unit
a_74182 Look ahead carry generator
Application specific ntsc NTSC video control signal generator
Buffer a_74240 Octal inverting 3-state buffer
a_74241 Octal 3-state buffer
Comparator a_8mcomp 8-bit magnitude comparator
a_7485 4-bit magnitude comparator
a_74688 8-bit identity comparator
Converter a_74184 BCD-to-binary converter
127
Macrofunctions
Counter Gray4 Gray code counter

a_7468 Dual decade counter
a_7493 4-bit binary counter
a_74191 4-bit up/down counter with asynch. load
a_74669 Synchr. 4-bit up/down counter
Decoder a_16dmux 4-to-16 decoder
a_7446 BCD-to-7 segment decoder
a_74138 3-to-8 decoder
EDAC a_74630 16-bit parallel error detection and correction
circuit
Encoder a_74148 8-to-3 encoder
a_74348 8-to-3 priority encoder with 3-state outputs
Frequency divider a_7456 Frequency divider
128
Macrofunctions
Latch Inpltch Input latch

a_7475 4-bit bistable latch
a_74259 8 bit addressable latch with clear
a_74845 8 bit bus interface D latch with 3 state outputs
Multiplier Mult4 4-bit parallel multiplier
a_74261 2-bit parallel binary multiplier
Multiplexer a_21mux 2-to-1 multiplexer
a_74151 8-to-1 multiplexer
a_74157 Quad 2-to-1 multiplexer
a_74356 8-to-1 data selector/multiplexer/register with 3 state outputs
Parity a_74180 9-bit odd/even parity generator/checker
generator/checker
129
Macrofunctions
Register a_7470 AND gated JK filp flop with preset and clear
a_7473 Dual JK flip-flop with clear
a_74171 Quad D flip-flop with clear
a_74173 4-bit D register
a-74396 Octal storage register
Shift register Barrelst 8-bit barrel shifter
a_7491 Serial-in serial out shift register
a_7495 4-bit parallel access shift register
a_74198 8 bit bidirectional shift register
a_74674 16-bit shift register
Storage register a_7498 4-bit data selector/storage register
130
Macrofunctions
SSI functions Inhb Inhibit gate

a_7400 NAND2 gate
a_7421 AND4 gate
a_7432 OR2 gate
a_74386 Quadruple XOR gate
True/Complement a_7487 4-bit true/complement I/O element
I/O element Quadruple complementary output elements
131
Macrofunctions
Library ieee;
Use ieee_std_logic_1164.all;
Library altera;
Use altera.maxplus2.all;
Entity example is
Port(data, clock, clearn, presetn: in std_logic;
q_out: out std_logic;
a, b, c, gn: in std_logic;
d: in std_logic_vector(7 downto 0);
y, wn: out std_logic);
End example
Architecture arch of example is
Begin
dff1: dff port map (d=>data, q=>q_out clk=>clock, clrn=>clearn, prn=>presetn);
mux: a_74151 port map(c,b,a,d, gn, y, wn);
End arch;
132
Library of Parameterized Modules
• Library of Parameterized Modules (lpm) is a library of
macrofunctions that is included in Max+Plus II
• Each module is parameterized: there are parameters and the
module can be used in different ways.
• Modules in the library are technology independent.
• The modules can be included in a schematic entry mode or in
VHDL code.
• Package: lpm_components
• Library: lpm
133
lpm modules
Name Description
Gates lpm_and Multi-bit and gate
lpm_inv Multi-bit inverter
lpm_bustri Multi-bit three state buffer
lpm_mux Multi-input multi-bit multiplexer
lpm_clshift Combinatorial logic shifter and barrel shifter
lpm_or Multi-bit or gate
lpm_constant Constant generator
lpm_xor Multi-bit xor gate
lpm_decode Decoder
mux Single input multi-bit multiplexer
busmux Two-input multi-bit multiplexer
Arithmetic lpm_compare Two-input multi-bit comparator
Components lpm_abs Absolute value
lpm_counter Multi-bit counter with various control options
lpm_add_sub Multi-bit adder subtractor
lpm_divide Parameterized Divider
lpm_mult Multi-bit multiplier
134
lpm modules
Name Description
Memory altdpram* Parameterized Dual-Port RAM
lpm_latch Parameterized Latch
csfifo Cycle shared first-in first-out buffer
lpm_shiftreg Parameterized Shift Register
dcfifo* Parameterized Dual-Clock FIFO
lpm_ram_dp Parameterized Dual-Port RAM
scfifo* Parameterized Single-Clock FIFO
lpm_ram_dq Synchronous or Asynchronous RAM with a separate I/O ports
csdpram Cycle shared dual port RAM
lpm_ram_io Synchronous or Asynchronous RAM with a single I/O port
lpm_ff Parameterized flip flop
lpm_rom Synchronous or Asynchronous ROM
lpm_fifo Parameterized Single-Clock FIFO
lpm_dff* Parameterized D-Type flip flop and Shift Register
lpm_fifo_dc Parameterized Dual-Clock FIFO
lpm_tff* Parameterized T-Type flip flop
Other functions clklock Parameterized Phase-Locked Loop
pll Rising- and Falling-Edge Detector
ntsc NTSC Video Control Signal Generator
135
Parameterized Modules
• An instance of a parameterized function is created with a
component instantiation statement and a generic map.
• Generic map assigns values to the parameters.
136
Library ieee;
Use ieee_std_logic_1164.all;
Library lpm;
Use lpm.lpm_components.all;
Entity reg24lpm is
Port(d: in std_logic_vector(23 downto 0); clk: in in std_logic;
q: out std_logic_vector(23 downto 0));
End reg24lpm;
Architecture arch of reg24lpm is
Begin
reg12a: lpm_ff
generic map (lpm_width =>12)
port map(data =>d(11 downto 0), clock => clk, q => q(11 downto 0));
reg12b: lpm_ff
generic map (lpm_width =>12)
port map(data =>d(23 downto 12), clock => clk, q => q(23 downto 0));
end arch;
137
VHDL Synthesis of Multiply & Divide
• The lpm_mult function can be used to synthesize integer multiplication
• The function lpm_divide is also available for integer division.
• Syntax
COMPONENT lpm_mult
GENERIC (LPM_WIDTHA: POSITIVE;
LPM_WIDTHB: POSITIVE;
LPM_WIDTHS: POSITIVE;
LPM_WIDTHP: POSITIVE;
LPM_REPRESENTATION: STRING := "UNSIGNED";
LPM_PIPELINE: INTEGER := 0;
LPM_TYPE: STRING := "L_MULT";
LPM_HINT : STRING := "UNUSED");
PORT (dataa: IN STD_LOGIC_VECTOR(LPM_WIDTHA-1 DOWNTO 0);
datab: IN STD_LOGIC_VECTOR(LPM_WIDTHB-1 DOWNTO 0);
aclr, clken, clock: IN STD_LOGIC := '0';
sum: IN STD_LOGIC_VECTOR(LPM_WIDTHS-1 DOWNTO 0) := (OTHERS => '0');
result: OUT STD_LOGIC_VECTOR(LPM_WIDTHP-1 DOWNTO 0));
END COMPONENT;
138
LIBRARY IEEE;
USE IEEE.STD_LOGIC_ARITH.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
LIBRARY lpm;
USE lpm.lpm_components.ALL;
ENTITY mult IS
PORT( A, B : IN STD_LOGIC_VECTOR( 7 DOWNTO 0 );
Product : OUT STD_LOGIC_VECTOR( 15 DOWNTO 0 ) );
END mult;
ARCHITECTURE a OF mult IS
BEGIN -- LPM 8x8 multiply function P = A * B
multiply: lpm_mult
GENERIC MAP( LPM_WIDTHA => 8,
LPM_WIDTHB => 8,
LPM_WIDTHS => 16,
LPM_WIDTHP => 16,
LPM_REPRESENTATION => "UNSIGNED" )
PORT MAP ( data => A,

datab => B,
result => Product );
END a;
139
VHDL synthesis of memory
• The memory functions in LPM are lpm_ram_dq,
lpm_ram_dp, lpm_ram_io, and lpm_rom.
• The memory can be set to an initial value using a file with
extension .mif.
• lpm_ram_dq can implement asynchronous memory or
memory with synchronous inputs and/or outputs.
• The lpm_ram_dq function uses EABs in FLEX 10K and
Cyclone devices.
• The Quartus Compiler automatically implements suitable
portions of this function in EABs.
• Small blocks of special purpose memory can be synthesized
using registers.
140
VHDL Component Declaration:
COMPONENT lpm_ram_dq
GENERIC (LPM_WIDTH: POSITIVE;
LPM_TYPE: STRING := "L_RAM_DQ";
LPM_WIDTHAD: POSITIVE;
LPM_NUMWORDS: POSITIVE;
LPM_FILE: STRING := "UNUSED";
LPM_INDATA: STRING := "REGISTERED";
LPM_ADDRESS_CONTROL: STRING := "REGISTERED";
LPM_OUTDATA: STRING := "REGISTERED";
LPM_HINT: STRING := "UNUSED");
PORT (data: IN STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0);
address: IN STD_LOGIC_VECTOR(LPM_WIDTHAD-1 DOWNTO 0);
we: IN STD_LOGIC := '1';
inclock: IN STD_LOGIC := '1';
outclock: IN STD_LOGIC := '1';
q: OUT STD_LOGIC_VECTOR(LPM_WIDTH-1 DOWNTO 0));
END COMPONENT;
141
• LPM_WIDTH Width of data[] and q[] ports.
• LPM_WIDTHAD Width of the address port.
• LPM_NUMWORDS Number of words stored in
memory.
• LPM_FILE Name of the Memory
Initialization File (.mif) or Hexadecimal (Intel-Format) File (.hex)
containing ROM initialization data ("<filename>"), or "UNUSED".
If omitted, contents default to all 0's.
142
LIBRARY IEEE;
ENTITY memory IS
read_address : IN STD_LOGIC_VECTOR( 2 DOWNTO 0 );
write_address : IN STD_LOGIC_VECTOR( 2 DOWNTO 0 );
Clock : IN STD_LOGIC );
END memory;
ARCHITECTURE behavior OF memory IS

-- define new data type for memory array
TYPE memory_type IS ARRAY ( 0 TO 7 ) OF STD_LOGIC_VECTOR( 7 DOWNTO 0 );
SIGNAL memory : memory_type;
BEGIN
-- Read Memory and convert array index to an integer with CONV_INTEGER
read_data <= memory( CONV_INTEGER( read_address( 2 DOWNTO 0 ) ) );
PROCESS -- Write Memory?

BEGIN
WAIT UNTIL clock 'EVENT AND clock = '1';
IF ( memwrite = '1' ) THEN
-- convert array index to an integer with CONV_INTEGER
memory( CONV_INTEGER( write_address( 2 DOWNTO 0 ) ) ) <= write_data;
END IF;
END PROCESS;
END behavior;
143
LIBRARY IEEE;
LIBRARY lpm;
USE lpm.lpm_components.ALL;
ENTITY amemory IS
memory_address : IN STD_LOGIC_VECTOR( 2 DOWNTO 0 );
clock,reset : IN STD_LOGIC );
END amemory;
ARCHITECTURE behavior OF amemory IS

BEGIN
data_memory: lpm_ram_dq -- LPM memory function
GENERIC MAP ( lpm_widthad => 3,

lpm_outdata => "UNREGISTERED",
lpm_indata => "REGISTERED",
lpm_address_control => "UNREGISTERED",
-- Reads in mif file for initial data values (optional)
lpm_file => "memory.mif",
lpm_width => 8 )
PORT MAP ( data => write_data, address => memory_address( 2 DOWNTO 0 ),

We => Memwrite, inclock => clock, q => read_data );
END behavior;
144
• Designer can create parameterized functions
• To create a parameterized logic function in VHDL, the
generic clause in the entity declaration must list all
parameters used in the architectural description and optional
default value
145
LIBRARY ieee ;
ENTITY regn IS
GENERIC ( N : INTEGER := 8 ) ;
PORT ( R : IN STD_LOGIC_VECTOR(N-1 DOWNTO 0) ;
Rin, Clock : IN STD_LOGIC ;
Q : OUT STD_LOGIC_VECTOR(N-1 DOWNTO 0) ) ;
END regn ;
ARCHITECTURE Behavior OF regn IS

BEGIN
PROCESS
BEGIN
WAIT UNTIL Clock'EVENT AND Clock = '1' ;
IF Rin = '1' THEN
Q <= R ;
END IF ;
END PROCESS ;
END Behavior ;
Figure 7.62 Code for an n-bit register with enableCopyright S. Shirani 146
LIBRARY ieee ;
ENTITY shiftr IS -- left-to-right shift register with async reset

GENERIC ( K : INTEGER := 4 ) ;
PORT ( Resetn, Clock, w : IN STD_LOGIC ;
Q : BUFFER STD_LOGIC_VECTOR(1 TO K) ) ;
END shiftr ;
ARCHITECTURE Behavior OF shiftr IS

BEGIN
PROCESS ( Resetn, Clock )
BEGIN
IF Resetn = '0' THEN
Q <= (OTHERS => '0') ;
ELSIF Clock'EVENT AND Clock = '1' THEN
Genbits: FOR i IN K DOWNTO 2 LOOP
Q(i) <= Q(i-1) ;
END LOOP ;
Q(1) <= w ;
END IF ;
END PROCESS ;
END Behavior ;
Figure 7.64 Code for the shift-register controllerCopyright S. Shirani 147

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COE4DI4

Engineering Design and VHDL

Prototype implementation Make corrections

Design one block Design one block

Design interconnection between blocks

Functional simulation of complete system

Testing Modify prototype

Development of a complex digital hardware

Truth table Schematic capture VHDL

INITIAL SYNTHESIS TOOLS Boolean equations

Logic synthesis, physical design, timing simulation

Design entry, initial synthesis, and functional simulation

The basic design loop Copyright S. Shirani

• Generic list: allows additional information to pass into an

architecture dataflow of eqcomp4 is

architecture bool of eqcomp4 is

entity eqcomp4 is port (a, b : in std_logic_vector(3 downto 0);

Figure 2.30 VHDL code for a four-input functionCopyright S. Shirani

(a) Truth table

(b) Karnaugh maps

ARCHITECTURE LogicFunc OF fulladd IS

Figure 5.23 VHDL code for the full-adder Copyright S. Shirani

ARCHITECTURE Structure OF adder4 IS

Figure 5.24 VHDL code for a four-bit adder Copyright S. Shirani

ARCHITECTURE Behavior OF adder16 IS

Figure 5.30 Use of the arithmetic package Copyright S. Shirani

architecture count4 of counter is

ARCHITECTURE Behavior OF mux2to1 IS

Figure 6.27 VHDL code for a 2-to-1 multiplexer Copyright S. Shirani 71

ARCHITECTURE Behavior OF compare IS

Figure 6.34 VHDL code for a four-bit comparatorCopyright S. Shirani 73

ARCHITECTURE Behavior OF mux2to1 IS

M u x _ O u t 1 < = A W H E N M u x _ C o n t r o l = '0 ' E L S E B ;

M u x _ O u t2 < = A W HEN '0 ',

Entity condit_stmt is Port(

Architecture concurrent of condit_stmt is

ARCHITECTURE Behavior OF flipflop IS

Figure 7.38 Code for a D flip-flop Copyright S. Shirani

ARCHITECTURE Behavior OF flipflop IS

Figure 7.39 Code for a D flip-flop using WAIT UNTIL

architecture count4 of counter is

Next State Logic Current State Output Logic

Next State Logic Output Logic d

Next State Logic Output Logic d

ARCHITECTURE behavior OF memory IS

PROCESS -- Write Memory?

maxplus2 altera Quartus primitives and macrofunctions

std_logic_signed ieee Functions to use std_logic_vector types as if they are

std_logic_unsigned ieee Functions to use std_logic_vector types as if they are

Primitive Primitive Name

Buffer Carry, Cascade, Exp, Global, Lcell, Soft,

Input and outputs INOUT, IN, OUT

Logic AND, NOR, BAND, NOT, BNAND, OR,

Adder a_8fadd 8 bit full adder

Counter Gray4 Gray code counter

Latch Inpltch Input latch

SSI functions Inhb Inhibit gate

PORT MAP ( data => A,