G PULLA REDDY ENGINEERING COLLEGE (AUTONOMOUS),

KURNOOL
Affiliated to JNTUA, Anantapuramu

DESIGN OF CMOS INSTRUMENTATION AMPLIFIER USING

180nm TECHNOLOGY
TEAM MEMBERS: BATCH 14 PROJECT GUIDE:
S Khadir Basha (209X1A04F0) Sri B Siva Reddy, M.Tech, (Ph.D)
S Lakshmi Tejaswini (209X1A04D4) Assistant Professor
R Blessy Chrysoprase (209X1A04C9) Dept of ECE
 CONTENTS

• Abstract
• Introduction
• Literature Survey
• Software tool
• Existing & Proposed design
• Description of Proposed Design
• Simulation Parameters
• Simulation Results
• Advantages
• Applications
• References
 ABSTRACT

This project entails the front-end design and simulation of a CMOS instrumentation
amplifier (IA) using the 180nm technology node. The instrumentation amplifier serves
as a critical front-end component for precision signal processing in sensor applications,
demanding high performance in terms of output voltage, power consumption and
reliability. The project leverages Cadence Virtuoso, a leading electronic design
automation (EDA) tool, for schematic creation, simulation, and validation of the IA
design. schematic, carefully considering key parameters such as output voltage and
power consumption.
 INTRODUCTION

Analog Devices instrumentation amplifiers (in-amps) are precision gain blocks that
have a differential input and an output that may be differential or single-ended with
respect to a reference terminal. These devices amplify the difference between two input
signal voltages while rejecting any signals that are common to both inputs. The
amplifiers can be customized according to the necessity. In our project, we intend to
design an instrumentation amplifier to reduce power consumption and maintain
accuracy of amplification.
 LITERATURE SURVEY

• B. Prakash Sharma., Rajesh Mishra. (2016). Design of CMOS instrumentation

amplifier with improved gain & CMRR for low power sensor applications. IEEE.

• The proposed work reveals a high performance instrumentation amplifier based

on operational amplifier (op-amp) for low power applications. The
instrumentation amplifier (IA) is designed for low power while maintaining the
high gain, high CMRR low noise as well as other design constraints.
 LITERATURE SURVEY

• Gajare, Dr. D. K. Shedge. (2023). CMOS Trans conductance Based

Instrumentation Amplifier for Various Biomedical signal Analysis. IJISAE.

• The proposed study demonstrates the design of an instrumentation amplifier

based on CMOS and the processing of biomedical ECG,
EEG, and EMG signals using Trans-conductance operational amplifiers.
Amplifiers with enormous trans-conductance that operate in the Giga hertz
frequency range are now available to design.
 SOFTWARE TOOL

• Cadence Virtuoso is a comprehensive platform designed to facilitate the entire IC

design process, from schematic entry and simulation to layout and verification. It
is renowned for its user-friendly interface, advanced features, and seamless
integration of different design stages.

• Efficiency and Productivity, Accurate Simulation, Customization and Flexibility,

Collaboration and Integration are some of the key benefits of using Cadence
EDA tool.
EXISTING DESIGN OF IA
PROPOSED DESIGN OF IA
 DESCRIPTION OF PROPOSED DESIGN

• The instrumentation amplifier was designed based on the three op-amp

approach.

• In the existing design, the number of transistors in the cmos input stage op-amp
is 24. The high number of transistors lead to more power consumption and heat
dissipation.

• In the proposed design, the number of transistors in the cmos input stage op-
amp is reduced to 8 by which the power consumption reduced by 3 times and
also the amplified signal is more accurate.
 SIMULATION PARAMETERS

• Signal Amplification: The amplification of signals can be defined as an increase

in the intensity of a signal. For Input signals VIN1=1.4V, VIN2=1.8V,

Amplified output voltage of the existing design = 0.4V

Amplified output voltage of our proposed design = 0.8V

• Power Consumption: The power consumption refers to the power used by the
circuit components.

Total power consumption of the existing design = 900uW

Total power consumption of the proposed design = 300uW

SIMULATION RESULTS OF EXISTING DESIGN

VIN1=1.4V, VIN2=1.8V; Amplified Output Voltage at 120nm Transistor Width = 467.1mV

VIN1=1.4V, VIN2=1.8V; Amplified Output Voltage at 240nm TW = 503.015mV
Total power consumption = 945.377 uW
SIMULATION RESULTS OF PROPOSED DESIGN

V1=1.4V, V2=1.8V; Amplified Output Voltage VOUT at 120nm TW = 801.702mV

Amplified Output Voltage VOUT at 240nm TW = 868.954mV
Total Power Consumption = 324.071uW
 ADVANTAGES

• Differential Amplification

• Variable Gain

• Precision and Accuracy

• Balanced Inputs

• Ease of Use

• Wide Frequency Range

 APPLICATIONS

• Sensor Interfaces

• Medical Instrumentation & Biomedical Devices

• Industrial Process Control

• Strain Gauge Measurements

• Audio Systems

• Communication Systems
 REFERENCES

• B. Prakash Sharma., Rajesh Mishra. (2016). Design of CMOS instrumentation

amplifier with improved gain & CMRR for low power sensor applications. IEEE

• Gajare, Dr. D. K. Shedge. (2023). CMOS Trans conductance Based

Instrumentation Amplifier for Various Biomedical signal Analysis. IJISAE

• https://www.electronicshub.org/instrumentation-amplifier-basics-applications/

• Texas Instruments : https://www.ti.com/lit/pdf/sboa282

• https://www.egr.msu.edu/classes/ece480/capstone/spring15/group05/uploads/
4/7/5/1/475156 39/ece_480_app_note_justin_bauer.pd
THANK
YOU