System on chip design using Rocket chip generator

Kashif Khan , Ahmar Khan

Reg no : 19abelt0843/37
Under the supervision of
Dr.Anees-Ullah
Assistant Professor

University of Engineering & Technology , Peshawar

Department of Electronics Engineering, Abbottabad Campus 1
• A framework used to design System on chip.
Components

Generators Chisel

Rocket chip
Accelerators Dsp tools
generator

Electronics Engineering Department, UET Peshawar 2

 Rocket Chip SOC Generator
• Used to design System on chip.
• Rocket chip use chip-building libraries we can use it to
generate different SOC variants.
• Rocket chip use many parts of SOC besides CPU.
• Memory, input/output (I/O) interface are the basic components
of an SOC

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 Sub components of Rocket Chip
• The Rocket Chip generator consists of the following
subcomponents
Rocket tile

System bus L1 to L2

L2 to TL /
Other
Control bus AXI
devices
adapter

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 System
bus

Control Other
bus devices

TL /
Boot Debug
AXI
rom unit
adapter

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 Rocket chip instance

Figure 1: Rocket chip instance

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 Observation of SOC
• Debug Unit is used to control the chip externally
• It can be controlled through a custom DMI or standard JTAG
protocol.

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 Observation of SOC
System
bus

Control
DMI
bus

Boot Debug JTAG

rom unit protocol
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 Communication With DUT
• There are two types of DUTs
• tethered and standalone DUTs.
• An example of a tethered DUT is a Chipyard simulation where
the host loads the test program into the DUTs memory and
signals to the DUT that the program is ready to run.

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 Communication With DUT

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 Communication With DUT
• Debug Module Interface (DMI) is a bus it can be used to
control Debug unit.
• FESVR is a C++ library that manages communication between
a host machine and a RISC-V DUT.
• FESVR uses the Host Target Interface (HTIF), a
communication protocol, to speak with the DUT .

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