Vlsi Design 21

“THE BEST WAY TO LEARN IS BY DOING”
VLSI DESIGN
AMANUEL ABREHA
1
05/02/2024 ECEg4191 VLSI DESIGN
VLSI and Its Trends
 VLSI:
 very large scale integration
 lots of(more numbers of ) transistors integrated on a single
chip
 Moore’s Law
In 1965, Gordon Moore predicted that transistors would
continue to shrink, allowing:
• Doubled transistor density every 18-24 months
• Doubled performance every 18-24 months
History has proven Moore right
But, is the end is in sight?
• Physical limitations
• Economic limitations
05/02/2024 ECEg4191 VLSI DESIGN 2
IC Evolution
 SSI (Small-Scale Integration)-(1962)
 Tens of Transistors[contained 1 –10 logic gates]
 NAND, NOR
 MSI (Medium-Scale Integration)-(late 1960)
 Hundreds of Transistors()
 Counters
 LSI (Large-Scale Integration)-(mid 1970)
 Tens of Thousands of Transistors
 First Microprocessor ()
 VLSI (Very Large-Scale Integration)-(1980)
 started Hundreds of Thousands of Transistors-several billion transistors in 2009
()
 64 bit Microprocessor with cache memory and floating-point arithmetic units
 ULSI (Ultra Large-Scale Integration)-(late 1980)
 More than about one million circuit elements on a single chip. ()
 The Intel 486 and Pentium microprocessors, use ULSI technology
 Giga-Scale Integration (2005)-[]
05/02/2024
 Tera-Scale Integration (2020)-[]
ECEg4191 VLSI DESIGN 3
IC technologies
 Bipolar
More accuracy
 MOS
Gate-Aluminium
Low power consumption
Low cost
 CMOS
Gate-Poly-Silicon
Low power consumption
Low cost
 BiCMOS
The aim is to combine the low-power, high-input impedance and
wide noise margins of CMOS with the high current-driving
capability of bipolar transistors
IC technologies
 Design Flow in Modern Digital System Design

General overview of VLSI design hierarchy

Advantage and limitations of IC
Advantages of IC
Size is less
Manufacturing cost: as virtually no manual assembly is
required
Design improvement
High Speed
Less Power Dissipation
Limitations of IC
 Feature size can’t be reduced ultimately
• Two factors that prevents further feature size reduction are
 Statistical fluctuation:-as the device size decreases Statistical fluctuation will
become important factor to limit performance of IC
 Resolution and photolithography equipment: the cost of developing these
equipment will likely high.
Types of IC
The variety of Integrated Circuits?
 More Specialized Circuits
 Application Specific Integrated Circuits (ASICs)
 Systems-On-Chips

Types of IC
 Standard ICs
Examples of ICs that are not ASICs include standard parts
such as:
• memory chips sold as a commodity item—ROMs, DRAM, and SRAM;
microprocessors; TTL or TTL-equivalent ICs at SSI, MSI, and LSI
levels.
 ASICs(Application Specific Integrated Circuits )
Examples of ICs that are ASICs include:
 a chip for a toy bear that talks;
 a chip for a satellite;
 a chip designed to handle the interface between memory and a
microprocessor for a workstation CPU;
 a chip containing a microprocessor as a cell together with other
logic.

IC fabrication steps
IC can be fabricated using the following process
 Silicon wafer
 Oxidation
 Photolithography
 Etching
 Diffusion
 Ion implementation
 Chemical vapour deposition
 Metallization
 Packaging

Implementation approach in VLSI design
Digital circuit
implementatio
n approach
Semi-Custom Full-Custom
Cell based Array based
Pre-diffused Pre-wired
Standard cell Macro cell
Gate array Field programmable array

ASICs
The steps in ASIC design flow.
 Design entry
 Logic synthesis System partitioning
 Pre-layout simulation.
 Floor planning
 Placement
 Routing
 Extraction

Types of ASICs
Give the different types of ASIC.
1. Full custom ASICs
2. Semi-custom ASICs
 standard cell based ASICs
 gate-array based ASICs
3. Programmable ASICs
• Programmable Logic Device (PLD)
• Field Programmable Gate Array (FPGA).

 Full-custom
In the full-custom design, the designers do not use the pre-
designed standard cell library.
Instead, they design the entire chip from the scratch. As each
and every part is designed in this approach, the chips are highly
optimized for area, power, and delay.
it can result in ICs that can operate at the highest possible
speed and require the smallest die (individual IC chip) area.
Hence, a full-custom design is always superior to any other
design style.
However, full-custom design cycle time is higher compared to
other design styles.
Full-custom design style is used for high performance and high
volume products.

 Advantage and Disadvantage of Full-custom
Advantages:
 highest speed and
 smallest die area;
 Disadvantages:
 design/development time and
 expense

• Figure below shows full custom design

 Semi-custom Design
In this style of design, almost all the basic building blocks are
used from the standard cell library.
Only few cells are designed from the beginning, which are
not available in the standard cell library or to be optimized
for a specific target.
 This approach is faster compared to the full-custom style
but slower than the standard cell-based design.
Performance-wise also, it is superior to the standard cell-
based design but inferior to the full-custom design.

Gate array
 Gate Array is an IC chip on which gates are placed m matrix form
without connection among the gates, as illustrated in Fig.(a) shown
below.
 The essential features of gate arrays are that
 standard transistors have been fabricated in advance using standard masks
and
 only the metallization masks are left to users to define their final logic
functions.
 Consequently, gate arrays (GAs) are also referred to as uncommitted
logic arrays (ULAs) because of the above reason
 By connecting gates, we can realize logic works, as exemplified in Fig.
(b).

Gate array
 Depending on the array structure, the GA are of the following three types:
 Channelled
 Channel-less
 Structured
 Channelled gate array
 In this architecture, there are rows of transistors called arrays and channels
are provided between the rows of transistors for their interconnections.
 Channel-less gate array
 Here there are no channels between the rows.
 As there are no channels in the channel-less architecture, the interconnections
are made by drawing metal lines through the unused transistors.
 Structured GA
 In this architecture, either channelled or channel-less structure can be used,
but the only difference is that it includes custom blocks.

Types of Gate array

Standard cells
 Standard cells are pre-defined logic elements used in the circuit.
 The design methodology that uses standard cells is known as cell

based design methodology.
 Standard cells are the basic building blocks of cell-based IC design

methodology
 A standard cell is designed either to store information or perform a

specific logic function (such as inverting, a logic AND, or a logic OR).

Standard cells
 The type of standard cell created to store data is referred to
as a sequential cell.
Flip-flops (FF) and latches are examples of sequential cells, which
are indispensable elements of any ASIC library.
 The type of standard cell used to perform logic operations on
the signals presented on its inputs is called combinational
cell.
logic gates (AND, OR, NAND, NOR, XOR, XNOR,NOT, etc.), some
mega cells (such as multiplexer, full-adder, decoder, etc.)
 Standard cells are built on transistors. They are One
abstraction level higher than transistors.
 All these standard cells are designed, tested, and
characterized and put in a database which is known as a
standard
05/02/2024
cell library. ECEg4191 VLSI DESIGN 22
VLSI design process
 The process of developing a chip from concept to silicon is
divided in to the following four tasks
 Design
 Verification
 Implementation
 Software development
 Abstraction : a very effective means of dealing with design
complexity.
 5 levels of abstraction in VLSI design process
Functional or architectural
Resister transfer level (module or functional block)
Logical design
Circuit design
Physical design
05/02/2024 ECEg4191 VLSI DESIGN 23
VLSI design
 Hardware block can be represented in four different
abstraction levels during the chip implementation process.
The lowest level is the transistor or device level.
• At this level, the entire block is described directly by
• Transistors,
• Diodes,
• Capacitors, and
• Resistors.
One level up is the cell level,
• This level composed of standard cells(gates and flip-flops).
One more step up is the module level.
• At this level, designs are represented by modules such as
• Adder,
• Multiplier,
• ALU, and
• Shifter.
VLSI design
The highest level is the chip level.
• At the chip level, designs are partitioned into sub-systems, such as
• DSP,
• Microcontroller,
• USB,
• ADC,
• DAC,
• PLL etc
 The higher the abstraction level, the less implementation detail it
contains.
 Levels of standard cells are created for easy chip implementation,
especially for large digital designs..

VLSI design
 Abstraction is a vary effective means of dealing with design
complexity
 Creating a model at high level of abstraction involves replacing detail at
low level with simplification
 Figure below shows level of abstraction

The advantages of cell-based design
methodology
 Designers save time as they need not design the standard
cells to be included in the design as they just import them
from the ASIC or Design library directly into the design.
 As the standard cells are predesigned, pretested and pre-
charecterized and kept in the STANDARDIZED library the
risk of the design is reduced.
 Each standard cell can be optimized individually and the
changes can be reflected throughout the chip at a time.
 During the design of cell library each and every transistor in
every standard cell can be chosen to maximise the speed or
minimize the area.

ASIC Library or standard Cell
Library
• An ASIC library or standard cell library is a group of
standard cells glued together as a package.
• A standard-cell library is one of the foundations upon which
the VLSI design approach is built.
• Typically, an ASIC library contains a sufficient number of
combinational cells to perform any logic operation required
by commonly used design styles with decent efficiency.

Standard cell library
• A typical modem ASIC library, could have more than several
hundred different standard cells.
• Those cells are categorized into groups by their
functionality, such as INV, BUF, NAND, NOR, AND, OR, XOR,
Boolean functions, flip-flop, and scan flip-flop.
• All
• these standard cells are designed, tested, and characterized
and put in a database
• which is known as a standard cell library.

Standard cell library
 A complete ASICs library should have the following
information available for each cell for automatic design
tools to use during various design phase
 Logic view
 Timing view
 Physical view
 Power view
 Electrical view
 Together ,these views provide a complete picture of each
cell in the library
 Quality of ASICs library has great impact on the quality of
the designs that use this library

Standard cell based design
 Sequences of operations in standard based design
 A design is captured using the standard cells in a library via
schematic or HDL
 The layout is then normally automatically and routed by the
CAD software
 As the complete layout is being done optimization of the height
of routing channels may be completed by good placement

VLSI Tech: CMOS Logics

CMOS DEVICES

CMOS technology
• Complementary metal oxide semiconductor (CMOS) is a
major class of integrated circuits.
• CMOS technology is used in microprocessors,
microcontrollers, static RAM, and other digital logic circuits.
• CMOS technology is also used for a wide variety of analog
circuits such as image sensors data converters, and highly
integrated transceivers for communications.
• In CMOS technology circuit, both n-type and p-type
transistors are used to realize logic functions.

CMOS technology (Comparison Between CMOS and BJTs)
 The main advantages of CMOS transistors over BJTs are as follows:
 Lower static power dissipation
 Higher noise margins
 Higher packing density, i.e., lower manufacturing cost per device
 High yield with large integrated complex functions
 The other features of CMOS transistors are as follows:

 High input impedance (low drive current)
 Scalable threshold voltage
 High delay sensitivity to load (fan-out limitations)
 Low output drive current (issue in driving large capacitive loads)
 Low transconductance, where transconductance (gm ∝ Vin)
 Bi-directional capability (drain and source are interchangeable)
 A near-ideal switching device

CMOS technology (Comparison Between CMOS and BJTs)
 Now, let us describe the advantages of BJTs over CMOS transistors:
 Higher switching speed
 Higher current drive per unit area, higher gain
 Generally better noise performance and better high frequency
characteristics
 Better analog capability
 Improved I/O speed (particularly significant with the growing importance of
package limitations in high-speed systems)
 The other features of BJTs are as follows:
 High power dissipation
 Lower input impedance (high drive current)
 Low voltage swing logic
 Low packing density
 Low delay sensitivity to load
 High gm (gm ∝ Vin)
 High unity gain bandwidth at low currents
 Essentially unidirectional
CMOS logic
 Switch-Level Transistor Model
CMOS digital circuits utilize NMOS and PMOS transistors
operating as switches
MOS transistor can operate as an on/off switch by using the
gate voltage to operate the transistor in the Acive region
(“on” position) and in the cut-off region (“off” position)
An NMOS transistor behaves as a closed switch, exhibiting a
very small resistance (Ron or rDS) between its drain and
source terminals when its gate voltage is “high,” usually at
the power-supply level VDD, which represents a logic 1.
Conversely, when the gate voltage is “low” (i.e., at or close to
ground voltage), which represents a logic 0, the transistor is
cut off, thus conducting zero current and acting as an open
switch.
CMOS switch level transistor model
 The PMOS transistor operates in a complementary fashion:
 =0V [or logic 0]
 The gate terminal of the MOSFET is used as the controlling node, and
thus it is usually the input terminal of the logic gate.
 Figure below shows the circuit diagram of a static CMOS inverter

CMOS logic
 The CMOS Inverter
 Armed with this knowledge of the switching behavior of MOSFETs,
let’s consider making an inverter
 the logic inverter inverts the logic value of its input signal.
 For a logic-0 input, the output will be a logic 1, and vice versa.
 Boolean expression representation of the logic function
 Here in this discussion we have to consider the following conditions

 =logic high and=logic low

CMOS logic

General Structure of CMOS Logic
 A CMOS logic circuit is in effect an extension, or a generalization, of the
CMOS inverter:
 The inverter consists of an NMOS pull-down transistor and a PMOS
pull-up transistor,
 operated by the input voltage in a complementary fashion.
 CMOS Push-Pull Networks
pMOS
 “on” when input is low
 pushes output high
nMOS
 “on” when input is high
 pulls output low

General Structure of CMOS Logic
 The CMOS logic gate consists of two networks:
Pull-down network (PDN) constructed of NMOS transistors
Pull-up network (PUN) constructed of PMOS transistors
 The two networks are operated by the input variables, in a
complementary fashion
 The PDN will conduct for all input combinations that require a low
output (Y = 0) and will then pull the output node down to ground,
causing a zero voltage to appear at the output, Y=0.
 The PUN will conduct for all input combination that requires high
output (Y = 1) , and the PUN will then pull the output node up to VDD,
establishing an output voltage Y= VDD.

CMOS Logics
• That is

CMOS Logics
 The transistor network is related to the Boolean function with a
straightforward design procedure:
1. Derive the nMOS transistor topology with the following rules:
 Product terms in the Boolean function are implemented with series-
connected nMOS transistors.
 Sum terms are mapped to nMOS transistors connected in parallel
2. The pMOS transistor network has a dual or complementary topology with
respect to the nMOS net. This means that serial transistors in the nMOS net
convert to parallel tansistors in the pMOS net, and parallel connections within
the nMOS block are translated to serial connections in the pMOS block.
3. Add an inverter to the output to complete the function if needed. Some
functions are inherently negated, such as NAND and NOR gates, and do not
need an inverter at the output state. An inverter added to a NAND or NOR
function produces the AND and OR function. The examples below require an
inverter to fulfil the function.

CMOS Logics
 All standard Boolean logic functions (INV, NAND, OR, etc.) can be
produced in CMOS push-pull circuits.
 Rules for constructing logic gates using CMOSuse a
complementary nMOS/pMOS pair for each input
 connect the output to VDD through pMOS txs
 connect the output to ground through nMOS txs
 ensure the output is always either high or low
 CMOS produces “inverting” logic
 CMOS gates are based on the inverter
 outputs are always inverted logic functions
 e.g., NOR, NAND rather than OR, AND

CMOS Logics
 Examples of PDNs

CMOS Logics
• Examples of PUNs

CMOS Logics (the two input NOR gate )
• We first consider the CMOS gate that realizes the two-

input NOR function

CMOS Logics (the two input NAND gate )
• The two-input NAND function is described by the

Boolean expression

CMOS Logics (A Complex Gate)
• Consider next the more complex logic function

CMOS Logics
 Obtaining the PUN form PDN

So far we have seen that the PUN AND PDN are dual
networks
i.e. when a series branch exist in one, a parallel exist in the
other.
Thus we can obtain one from the other ,a process that can
be simpler than having to synthesize each separately from
the Boolean expression of the function
 Problem: synthesize the CMOS logic expressed by
Boolean expression shown below

CMOS Logics (summary of the synthesize method )
1. The PDN can be most directly synthesized by

expressing as a function of the uncomplemented
variables. If complemented variables appear in this
expression, additional inverters will be required to
generate them.
2. The PUN can be most directly synthesized by
expressing as a function of the complemented variables
and then applying the uncomplemented variables to
the gates of the PMOS transistors. If uncomplemented
variables appear in the expression, additional inverters
will be needed.
3. The PDN can be obtained from the PUN (and vice
versa) using the duality property.
CMOS Logics (summary of the synthesize method )
END OF CHAPTER ONE

Chapter Two
Programmable
ASICs

Digital system families
• Using a hardware solution for your digital system design is always faster than a software
solution.
Digital systems
 As we can see from the above figure, The major digital system
categories include
Standard logic,
Application-specific integrated circuits (ASICs) and
Microprocessor/digital signal processing (DSP) devices.
 Standard logic devices refers to the basic functional digital

components such as
gates,
flip-flops,
decoders,
multiplexers,
registers,
counters, etc. These are available as SSI and MSI chips.
Digital systems
 Microprocessor/digital signal processing (DSP)
 it is a much different approach to digital system design.
These devices actually contain the various types of functional
blocks .
With microcomputer/DSP systems, devices can be controlled
electronically, and data can be manipulated by executing a
program of instructions that has been written for the
application.
 A great deal of flexibility can be achieved with
microcomputer/DSP systems because all you have to do is
change the program.
The major downfall with this digital system category is speed

Digital systems
 The third major digital system category is called application-
specific integrated circuits (ASiCs).
 This broad category represents the modern hardware design
solution for digital systems.
 As the acronym implies, an integrated circuit is designed to
implement a specific desired application
 Four subcategories of ASIC devices are available to create digital
systems:
 gate arrays,
 standard-cell, and
 full-custom
 programmable logic devices, (i.e. the programmable ASICs)

Programmable logic devices (ASICs)
 Introduction : importance of PLDs
 Hardware realization of logic networks is generally very time-consuming
and expensive.
 Because, once logic functions are realized in hardware, it is difficult to
change them.
 In some cases, we need logic networks that are easily changeable.
 logic networks whose output function need to be changed frequently, such
as control logic in microprocessors
 logic networks that need to be debugged(corrected) before finalizing
 PLDs Are the solution and they serve for this purpose
 PLD is used to build reconfigurable digital circuits.
 General purpose chip for implementing circuits
 Can be customized using programmable switches
 i.e. programmable logic devices has undefined function unlike that of logic
gate which is fixed

Programmable logic devices
 Programmable logic devices (PLDs), sometimes referred to as field
programmable logic devices (FPLDs)
 Can be custom-configured(user design) to create any desired digital circuit,
from simple logic gates to complex digital systems.
 Generally, PLDs can be described as being one of three different types:
 Simple programmable logic devices (SPLDs),

 Programmable logic array
 Programmable array logic
 Complex programmable logic devices (CPLDs), or
 Field programmable gate arrays (FPGAs).
 Together, CPLDs and FPGAs are often referred to as high- capacity

programmable logic devices (HCPLDs).

Programmable ASICs
 PLDs can
 reduce parts inventory,
 simplify prototype circuitry,
 Shorten the development cycle,
 reduce the size and power requirements of the product, and
 allow the hardware of a circuit to be upgraded easily.
 Programmable link process technology

 Several different process technologies are used for
programmable link in the PLDs
 Fuse technology
 Anti-fuse technology
 EPROM technology

Programmable ASICs
 FUSE Technology : Metal link technology
 Anti-fuse Technology :it is the opposite of fuse technology

 two conductors separated by an insulator

Programmable ASICs
 EPROM technology used Floating- gate MOS transistors

Programmable ASICs
 Simple PLDs
Programmable logic array (PLA)
 Used to implement circuits in SOP form
 The connection in the AND plane are programmable
 The connection in the OR plane are programmable
05/02/2024 64
ECEg4191 VLSI DESIGN
Programmable ASICs
05/02/2024 65
ECEg4191 VLSI DESIGN
Programmable ASICs
 gate level version of PLA

Programmable ASICs
Two basic types of programmable gate array

Programmable ASICs
Two basic types of programmable gate array

Programmable ASICs
 Programmable array logic (PAL)
 Used to implement circuits in SOP form
 The connection in the AND plane are programmable
 The connection in the OR plane are not programmable

PAL(Programmable Array
Logic )
Fig. Implementation of a Full Adder Using a PAL

Programmable ASICs
• Example schematic of PLA

PLDs (PASICs)
 Comparing PALs and PLAs
 PALs have the same limitation as PLAs( Small number of AND terms ) plus they
have fixed OR planes less flexibility than PLAs
 PALs are simpler to manufacture cheaper, faster(better performance )
 PALs have extra circuitry connected out put of each OR gate
 OR gates plus these circuitry are called macro-cell
 Macro-cell

Programmable ASICs
 Complex programmable logic devices(CPLDs)
Contains multiple circuit blocks on a single chip
Each block is like a PAL
Connections are provided between PAL like blocks via an
interconnection network that is programmable
Each block is connected to I/O blocks
Most CPLDs contain logic blocks that have programmable
AND/fixed-OR logic circuits with fewer product terms available
than most PAL devices
The programming technologies used in CPLD devices are all non-
volatile and include
 EPROM,
 EEPROM, and
 flash, with EEPROM being the most common.
All three technologies are erasable and reprogrammable.
Programmable ASICs
 CPLDs structure

Field Programmable Gate Array
 A Field Programmable Gate Array (FPGA) is a PLDs that
supports implementation of relatively large logic circuits.
 FPGAs are quite different from SPLDs and CPLDs because
FPGAs do not contain AND and OR planes
 FPGAs provides logic blocks implementation required functions
 The general structure of an FPGA contains three main types of
resources
Logic blocks
I/O blocks for connecting to the pins of the packag
Interconnection of wires and switches
 FPGAs can be used to implement a logic circuit with more than
20,000 gates whereas a CPLD can implement circuits of upto
about 20,000 equivalent gates.
Field Programmable gate array
 Logic blocks are arranged in two dimensional arrays
 Interconnection wires are organized as horizontal and vertical
routing channels between rows and columns of logic blocks
 Used to perform Boolean expression or sequential expressions
 Routing channels contains wires and programmable switches that
allows logic blocks to be interconnected in many ways

FPGA ASICs
The field programmable logic array (FPLA) was

developed in the mid-1970s as the first nonmemory
programmable logic device.
It used a programmable AND array as well as a
programmable OR array. Although the FPLA is more
flexible than the PAL architecture, it has not been as
widely accepted by engineers.
FPLAs are used mostly in state-machine design where a
large number of product terms are needed in each SOP
expression.

FPGA
• FPGA is a semiconductor device that can be configured
by the customer or designer after manufacturing—hence the
name “field-programmable*’.
• FPGAs are programmed using a logic circuit diagram or a source
code in a hardware description language (HDL) to specify how
the chip will work.
• FPGA can be used to implement any logical functions that an
application-specific integrated Circuit (ASIC) could perform.
• Unlike an ASIC which can perform a single specific function for
the lifetime of the chip and it can be reprogrammed to perform
a different function in a matter of microseconds.
• Before it is programmed an FPGA knows nothing about how to
communicate with the devices surrounding it.

Application of CPLDs AND FPGAs
 CPLDs and FPGAs are used today in many diverse
applications, such as consumer products like DVD players
high end televisions sets controller circuits for automobile
factories and test equipment ,internet routers and high
speed network switches and computer equipment like
large and disk storage systems .

Questions regarding the chapter
• What do you understand by the word interconnected
switches or wires?
• What do understand by programmable circuits?
• What do understand by the word fuses in
programmable circuits?
• What do you think is the difference between
Programmable ASICs and Normal ASICs ?write a brief
note about the two types of ASICs
• What is the difference between PAL and PLA ?
• Why is FPGAs faster than CPLDs in data processing

• END OF CHAPTER TWO
• Any ? is welcomed

CHAPTER THREE
HARDWARE DESCRPTION LANGUAGE

HDL (Hardware description Language )
 The design of IC needs a computer language to
describe its structure and function.
 HDL is a Hard ware Description Language used for the
above purpose.
 Two languages are developed .These two languages are
called
VHDL(very high speed integrated circuit hard ware
description language )
Verilog
 A third language is called ABEL(Advanced Boolean
Equation Language )and is less powerful than the other
two languages and is less popular in industry.

VHDL
 VHDL
Used to develop very high integrated circuits
It is one of the industry standard language
Powerful language to simulate and describe complex digital
systems
described by the IEEE standard 1076-1993
It can execute commands in parallel –concurrent statements
 Concurrent statements are executed simultaneously as soon as
new input arrives
• (This the important difference between HDL and other
programming languages )

VHDL program
 Every pieces of VHDL code is composed of
at least three sections
Library declaration: Contains a list of all
libraries to be used in the design
Entity: Specifies the input and output pins of
the circuit
Architecture: Contains the VHDL code which
describes how the circuits should behave
(function )

VHDL program
 At least three packages, from three different
libraries, are usually needed in a design :
ieee.std_logic_1164 (from the ieee library),
standard (from the std library) , and
work (work library) LIBRARY ieee;

HDL(Levels of representation and abstraction )
• A digital system can be represented at different levels of abstraction.
• This keeps the description and design of complex systems
manageable
• Fig: Levels of abstraction: Behavioral, Structural and Physical

HDL(Levels of representation and abstraction )
 Behavioural
 level is the highest level of abstraction
This level describes a system in terms of what it does (or
how it behaves) rather than in terms of its components and
interconnection between them.
it specifies the relationship between the input and output
signals using
 Boolean expression
 Register transfer level
 Algorithms
Behavioral level further divided into two kids of styles
 Data flow
• Concurrent statement:- executed simultaneously
• Sequential statement :- executed in sequence they are specified
 Algorithms

VHDL(Levels of representation and abstraction )
 Example consider a circuit that warns car passengers when the door is open or
seatbelt is not used whenever the car key is inserted in the ignition lock
Warning =Ignition _on AND (Door _open OR Seatbelt _off)
 Structural
 describes a system as a collection of gates and components that are
interconnected to perform a desire function.
 Usually closer to the physical realization of a system
Fig-2: Structural representation of a “buzzer” circuit.

Design units in VHDL
 Five design units of HDL
 Entity :-
 Name plate of the design
 Define input and output ports
 Specifies what types of ports they will be
 An entity can have more than one architecture
 Different data modes that will be specified in the entity are
 BIT data type
 Boolean data type
 STD_LOGIC data type

 what type of value these data types can take
 BIT data type
 This data type supports the value of ‘1’ and ‘0’
 If it is a digital circuit no way to have a value rather than 0 and 1
 Boolean data type :- less frequently used
 It has two values TRUE and FALSE
 STD_LOGIC data type :- most commonly used data type
 Data type defined in the std_logic _1164 package of IEEE Library . It is
defined as
 Packages – own data type
 Types std_logic is ()
‘U’ : uninitialized ‘0’ : Logic 0
‘X’ : unknown ‘1’ : Logic 1
‘Z’ : High impedance ‘W’ : unknown
‘L’ : Low logic 0 ‘H’ : Low logic 1
‘_’ : Don’t care

STD_LOGIC type
 Similar to BIT and BIT_VECTOR types, VHDL provides STD_LOGIC_VECTOR.
 To use the definitions and functions of the Standard Logic Package, the
following statements have to be included in the program
 Library ieee;
 Use IEEE.STD_LOGIC_1164.all ;

Summary of data type

operators
• VHDL provides several kinds of pre-defined
operators:
Assignment operators
Logical operators
Arithmetic operators
Relational operators
Shift operators
Concatenation operators

Assignment operators
 They are used to assign values to signals, variables, and constants. They are:
 <= Used to assign a value to a SIGNAL.
 := Used to assign a value to a VARIABLE, CONSTANT, or
GENERIC. Used also for establishing initial values.
 => Used to assign values to individual vector elements or with
OTHERS.
 Example: Consider the following signal and variable declarations:
SIGNAL x : STD_LOGIC;
VARIABLE y : STD_LOGIC_VECTOR(3 DOWNTO 0); -- Leftmost bit is MSB
SIGNAL w: STD_LOGIC_VECTOR(0 TO 7); -- Rightmost bit is MSB
Then the following assignments are legal:
x <= '1'; -- '1' is assigned to SIGNAL x using "<=“
y := "0000"; -- "0000" is assigned to VARIABLE y using ":=“
w <= "10000000"; -- LSB is '1', the others are '0„
w <= (0 =>'1', OTHERS =>'0'); -- LSB is '1', the others are '0’


 Modes of entity
 Mode IN
 Mode OUT
 Mode INOUT – less frequently used
 Mode Buffer- least frequently used and complex
entity NAME_OF_ENTITY is
port (signal_names: mode type;
signal_names: mode type;
:
signal_names: mode type);
end [NAME_OF_ENTITY] ;

-- comments: example of the buzzer circuit of fig.

entity BUZZER is
port (DOOR, IGNITION,SBELT: in std_logic;
WARNING: out std_logic);
end BUZZER;
 Architecture:-it specifies
 How my circuit is going to behave
 What my circuit is going to do

 Different styles of Architectural modelling
 Dataflow :- how and from where
architecture architecture_name of NAME_OF_ENTIT

-- Declarations
-- components declarations
-- signal declarations
-- constant declarations
-- function declarations
-- procedure declarations
-- type declarations
:
begin
-- Statements
:
end architecture_name;
architecture behavioral of BUZZER is

begin
WARNING <=
(not DOOR and IGNITION) or (not SBELT and IGNITION);
end behavioral;
 Different styles of Architectural modelling
 Dataflow :- how and from where
-- Example:- how to write entity for AND gate
entity AND2 is
port(a,b:in std_logic;
c:out std_logic);
end AND2;
Architecture Behavioral of AND2 is
begin
C<= a AND b;
end behavioral;
Behavioral :-
 known as high level description
 Consists of assignment statements to represent behavior
 No need to focus on gate level implementation
architecture behavioral of and_gate is

begin
Process(a,b)
begin
if a= ‘1’ and b=‘1’then
C<=‘1’,
else
C<=‘0’,
end if;
end process
end behavioral;

Design of Full ADDER USING BEHAVIORAL
architecture BEHAVIOUR of FULL_ADDER is
begin
process (A, B, CIN)
Begin
if (A=„0‟ and B=„0‟ and CIN=„0‟) then
SUM <= „0‟;COUT <=„0‟;UM <= „0‟;COUT <=„0‟;
elsif (A=„0‟ and B=„0‟ and CIN=„1‟) or
(A=„0‟ and B=„1‟ and CIN=„0‟) or
(A=„1‟ and B=„0‟ and CIN=„1‟) then
SUM <= „1‟;COUT <=„0‟;
elsif (A=„0‟ and B=„1‟ and CIN=„1‟) or
(A=„1‟ and B=„0‟ and CIN=„1‟) or
(A=„1‟ and B=„1‟ and CIN=„0‟) then
SUM <= „0‟;COUT <=„1‟;
elsif (A=„1‟ and B=„1‟ and CIN=„1‟) then
SUM <= „1‟;COUT <=„1‟;
end if ;
end process ;
end BEHAVIOUR ;
 Structural
 A structural design methodology is used to split in to manageable
unit
 A design can be described in an architecture by different levels of
abstraction
 To facilitate faster design
 Better understanding
 Lesser complexity

 A few other examples follow. The behavioral description
of a two-input AND gate is shown below.
entity AND2 is
port (in1, in2: in std_logic;
out1: out std_logic);
end AND2;
architecture behavioral_2 of AND2 is
begin
out1 <= in1 and in2;
end behavioral_2;

 Example of a two-input XNOR gate is shown below.
entity XNOR2 is
port (A, B: in std_logic;
Z: out std_logic);
end XNOR2;
architecture behavioral_xnor of XNOR2 is

-- signal declaration (of internal signals X, Y)
signal X, Y: std_logic;
begin
X <= A and B;
Y <= (not A) and (not B);
Z <= X or Y;
End behavioral_xnor;
HDL(Basic Structure of a VHDL file)
 Few key terms we will be regularly using

 Assigned
Assume we have variables . If we give the value from y to
x , x is assigned the value of y
 Read
If x is getting the value of y , x is reading the value of y
If y is getting the value of z , y is reading the value of z
 That is
 Take – Read
 Give – Write
 Drivers
A signal or port that gives a logic value i.e. a particular
type of value to signal or port
Person who gives this value typically called Driver
VHDL code Waveform (VHDL Simulation)
Library ieee;
use ieee.std_logic_1164.all;
entity and1 is
port(x, y:in bit ; z:out bit);
end and1;
architecture simu of and1 is
begin
z<=x and y;
end simu;
VHDL Programming Combinational Circuits
VHDL Code for a Half-Adder Waveform
Library ieee;
entity half_adder is
port(a,b:in bit;
sum,carry:out bit);
end half_adder;
architecture data of half_adder is

Begin
sum<= a xor b;
carry <= a and b;
end data;
VHDL code full Adder Waveform
Library ieee;
entity full_adder is port(a,b,c:in bit;

sum,carry:out bit);
end full_adder;
architecture data of full_adder is

Begin
sum<= a xor b xor c;
carry <= ((a and b) or (b and c) or (a and c));
end data;

VHDL code for MUX Waveform
Library ieee;
entity mux is
port(S1,S0,D0,D1,D2,D3:in bit; Y:out bit);
end mux;
architecture data of mux is

begin
Y<= (not S0 and not S1 and D0) or
(S0 and not S1 and D1) or
(not S0 and S1 and D2) or
(S0 and S1 and D3);
end data;

VHDL code 8x3 encode Waveform
library ieee;
entity enc is
port(i0,i1,i2,i3,i4,i5,i6,i7:in bit; o0,o1,o2: out
bit);
end enc;
architecture synth of enc is

begin
o0<=i4 or i5 or i6 or i7;
end synth;
VHDL Programming Combinational Circuits)
Exercise
• Write A VHDL code for
4-bit parity checker
• Write A VHDL code for
4- bit parity generator
• Write a VHDL code Two
bit subtractor
• Write VHDL code Jk flip-
flop
VHDL Programming for Sequential Circuits
VHDL Code for an SR Latch Waveform
library ieee;
entity srl is
port(r,s:in bit; q,qbar:buffer bit);
end srl;
architecture virat of srl is

signal s1,r1:bit;
begin
q<= s nand qbar;
qbar<= r nand q;
end virat;
VHDL code for sequential circuits
VHDL Code for an SR Flip Flop Waveform
library ieee;
entity srflip is
port(r,s,clk:in bit; q,qbar:buffer bit);
end srflip;
architecture virat of srflip is

signal s1,r1:bit;
begin
s1<=s nand clk;
r1<=r nand clk;
q<= s1 nand qbar;
qbar<= r1 nand q;
end virat;

VHDL(multiplexer (4x1) using case)
entity Mux4 is
port(i: IN BIT_VECT0R(3 downto 0);
sel: IN BIT_VECT0R(1 downto 0);
S: out BIT);
end Mux4;
architecture Synthesis of Mux4 is
begin
process (sel, i)
begin
case sel is
when “00” => s <= i(0): when “01” => s <= i(1):
when “10” => s <= i(2); when “11” => s <= i(3):
end case;
end process;
end Synthesis;
 A Structural Style defines the structural implementation using

component declarations and component instantiations.
 The following shows a structural description of the same FULL_ADDER.
 Two types of components are defined in this example, HALF_ADDER
and OR_GATE.
 Structural style does not use processes !!!

VHDL(Half adder structural Design )
architecture STRUCTURE of FULL_ADDER is
component HALF_ADDER
port ( L1, L2 : in BIT ;
CARRY, SUM : out BIT ) ;
end component ;
component OR_GATE
port ( L1, L2 : in BIT ;
O : out BIT ) ;
end component ;
signal N1, N2, N3 : BIT ;
Begin
HA1 : HALF_ADDER port map (A, B, N1, N2) ;
HA2 : HALF_ADDER port map (N2, CIN, N3, SUM) ;
OR1 : OR_GATE port map (N1, N3, COUT) ;
end STRUCTURE ;
 Top level entity consists of two HALF_ADDER instances and an OR_GATE

instance. The HALF_ADDER instance can be bound to another entity which
consists of an XOR gate and an AND gate.
HDL(VHDL data objects )
Objects can have values, attributes and methods.
A data object holds a value of a specific type
Object declared in a package are available to all VHDL
descriptions which use that package
Object declared in an entity are available to all
architectures associated with that entity
Object declared in an architecture are available to all
statements in that architecture
Object declared in a process are available only within that
process.
We will primarily use the following VHDL data objects:
Signals, Constants, Variables
VHDL(constants )
 A constant is an object which is initialized to a specific value when
it is created and which cannot be subsequently modified.
 Constant declarations are allowed in packages, entities,
architectures, subprograms, blocks, and processes.
 They cannot be implemented in hardware.
The syntax is :

Constant constant_name : type_name [:= int_value] ;
 Example:
constant s0: std_logic_vector(1 downto 0):= “01”;
constant YES : BOOLEAN := TRUE ;
constant CHAR7 : BIT_VECTOR (4 downto0) := “00111” ;
constant MSB : INTEGER := 5 ;
CONSTANT PI: Real: = 3.14;
Constant Speed: integer;
Notes:
1. Use a set of single apostrophes to enclose a single bit (e.g. „1‟).
2. Use a set of quotations to enclose multiple bits (e.g. “01”)

VHDL(constants)
• Constants :-
It holds value that can’t be changed with in a design
• Syntax:
Constant constant_name:<type_spec>:=<value>;
• Example declaration of constants

VHDL(variables)
 Variables are used to hold temporary data
 They can only be declared in a process or a subprogram.(Scope)
 Provide convenient mechanism for local storage
Example: Loop counters, intermediate values
 When a variable is assigned, the assignment executes in zero
simulation time. In other words, it changes the value of the variable
immediately at the current simulation time (no delta or users pecified delay is
incurred).
 They cannot be implemented in hardware.
 The syntax is :
Variable variable_name : type_name [:= value] ;
 Examples :
variable opcode : bit_vector( 3 downto 0): = “0000”;
variable freq: integer;
variable X , Y : BIT ;
variable TEMP : BIT_VECTOR (8 downto 0) ;
variable DELAY : INTEGER range 0 to 15 := 5 ;
VHDL(variables)
Internal representation used by programmers : don’t exist physicaly
The update of variable is immidate

VHDL(Signals)
 They can be interpreted as wires or busses in an actual circuit.
 Signals are data objects in which the value of the object can be changed.
 Signals are used to pass information directly between VHDL processes and
entities. That is, Signals connect design entities together and communicates
changes in values between processes.
 Signal assignments require a delay before the signal assumes its new
value. In fact, a particular signal may have a series of future values with
their respective timestamps pending in the signal's waveform. That is, There
is an implied or explicit delay between the signal assignment and when the signal is
updated.
 They can be implemented in hardware.
 Scope: Signals can be declared in packages(global signals), entities(entity global
signals), architectures(architecture global signals)and blocks.
 The syntax is :
Signal signal_name : type_name [:= value] ;
 Examples :
signal BEEP : BIT := „0‟ ;
signal TEMP : STD_LOGIC_VECTOR (8 downto0) ;
signal COUNT : INTEGER range 0 to 100 := 5 ;
Signal A: bit;
A<=„0‟ after 5ns, „1‟ after 10 ns;
VHDL(signals)
 Used to represent wire connection
 Declaration : SIG NAME:<type spec>
 Example


VHDL(signlas)
library IEEE;
use IEEE.std_logic_1164.all;
entity full_adder is
port (in1, in2, c_in: in std_ulogic;
sum, c_out: out std_ulogic);
end entity full_adder;
architecture dataflow of full_adder is
signal s1, s2, s3 : std_ulogic;
constant gate_delay: Time:= 5 ns;
begin
L1: s1 <= (In1 xor In2) after gate_delay;
L2: s2 <= (c_in and s1) after gate_delay;
L3: s3 <= (In1 and In2) after gate_delay;
L4: sum <= (s1 xor c_in) after gate_delay;
L5: c_out <= (s2 or s3) after gate_delay;
end architecture dataflow;

VHDL(Array type)
 Array types group one or more elements of the same type together as a single object.
 VHDL composite types consists of arrays and records. Each object of this data type can
hold more than one value.
 Arrays consist of many similar elements of any data type, including arrays.
 Example:
TYPE data_bus is ARRAY ( 0 to 31) of bit;
Variable x: data_bus;
Variable y: bit;
Y:= x(12); -- y gets value of x at index 12
 The array is declared in a TYPE statement. There are numerous items in an array
declaration:
 The first item is the name of the array.
 Second, the range of the array is declared. The keywords TO and DOWNTO
designate ascending or descending indices, respectively, within the specified range.
 The third item is the specification of the data type for each element of the array.

VHDL(Array)
 In the example above, an array consisting of 32 bits is specified.
 Note that individual elements of the array are accessed by using the index
number of the element as shown above.
 The index number corresponds to where in the specified range the index
appears.
 For example, X(12) above refers to the thirteenth element from the left (since
the leftmost index is 0) in the array.
 type A1 is array (0 to 31) of INTEGER ;
 Downto- key is used when leftmost index is greater than the right most index.
Example:
Type reg_type is Array(31 downto 0) of bit;
Variable x: reg_type;
Variable y: bit;
Y:= x(4); -- , X(4) refers to the fifth element from the right in the array (with 0
being the index for the element furthest to the right in this case).

VHDL
End Of Chapter Three

Thank U !

CHAPTER FOUR
Simulation

Chapter four
Logic Simulation
 What is simulation?
 Design verification
 Circuit modeling
 True-value simulation algorithms
 Compiled-code simulation
 Event-driven simulation
 Summary

Simulation Defined
 Definition: Simulation refers to modeling of a design, its function
and performance.
 A software simulator is a computer program; an emulator is a
hardware simulator.
 Simulation is used for design verification:
 Validate assumptions
 Verify logic
 Verify performance (timing)
 Types of simulation:
 Logic or switch level
 Timing
 Circuit
 Fault

Modeling for Simulation
 Modules, blocks or components described by
 Input/output (I/O) function
 Delays associated with I/O signals
 Examples: binary adder, Boolean gates, FET, resistors and capacitors
 Interconnects represent
 ideal signal carriers, or
 ideal electrical conductors
 Netlist: a format (or language) that describes a design as an
interconnection of modules.

Logic state
 Binary logic(0,1)
 Three valued logic (0,1,u) ternary logic
 U (unknown) for logic value can’t be determined during
simulation
 Four valued logic (0,1,u,z)
 Floating node without conduction path to Vdd or GRD
 z: high impedance
 Note: see what is happen with u and z
 More state, more accuracy, more CPU time

Ternary logic simulation
Problem: output k should be zero
Ternary logic simulation:k=u

 What is the moral
of this problem?
 Simulation results
are always
accurate
Enumerate all possible cases(B=0,or 1)  W need to check
carefully

Gate evaluation using truth table
• Determine the output value based on a
pre-stored truth table
• Example four valued logic truth table

• Practical implementation
Break n-input gates in to multiple 2
input gates
Use for loop to evaluate gates one by one
Gate delay model
 Propagation delay (transport delay)
 DEF: time from gate input to output change
 Zero delay: pro. Delay of all gates is zero
 Unit delay:pro. Delay of all gates is one time unit (Levelization )
 Multiple delay: pro. Delay is multiple of unit time delay
 Rise delay
 Fall delay
 Ambiguous delay mode
 Max. delay , min. delay , typical (nominal delay)
 Internal delay mode
 Minimum amount of time during which a signal must persist at the
gate input in order to change gate output

True-Value Simulation Techniques
 Compiled-code simulation
 Applicable to zero-delay combinational logic
 each circuit component is evaluated at fixed time
points
 Efficient for highly active circuits, but inefficient for
low-activity circuits
 High-level (e.g., C language) models can be used

Compiled codes
 Translate circuit into sequence of codes
 Execute codes: run simulation

How to compile codes?

Logic optimization
 Simplify logic before generating codes
 Shorten code length and simulation time
 Example :

Logic levelization
 Levelization: order gate in sequence such that
 A gate won’t be evaluated until all its driving gates have been
evaluated
 Example
 Levelization ensures correct order

Logic Levelization
Step A B C
0 0 0 0
1 0 0 0
2 0 0 0 1
3 0 0 0 1 2
4 0 0 0 1 2
5 0 0 0 1 2 2
6,7,8 0 0 0 1 2 2 3

Code generation
1. High level code (like C)
 Portable easy, easy debug
 Need compilation every time circuit change
2. Machine code
 Fast to run
 Not portable, hard to debug
3. Interpreted code
 (at run time, code are interpreted and excuted )
 Portable ,easy debug
 Slower than machine code

Compiled code simulation problems
1. Gate delay model not considered

2. Oblivious: forget results in previous cycle

summary
 compile code simulation: converts gates into codes for evaluation
optimization : simplifies logic
Levelization: sorts gate in order (i,e. topological sort of graph)
code generation: high level, machine and interpreted
 pros
simple to implement
can speed up by parallelism
 cons :
only cycle based accuracy(it doesn’t proved timing information ),
not timing (zero gate delay )
need to evaluate whole circuit even only small portion changed

Event-driven simulation(ulrich 1965)
 Event derive simulation:

a component is evaluated only when one of its inputs
changes.
Delays can be accurately simulated for timing
verification
Efficient for low-activity circuits
Can be extended for fault simulation
Better simulation technique
 Ideal : evaluates a gate only if there is events at its gate
inputs
Event is a signal value changed (at time T)
 gate with inputs change are activated

Event-driven simulation(ulrich 1965)

Event derive simulation
 Longer line may has larger delay
 Static one: 1- hazard
 The more variable you take, the more accurate is the
simulation

Event-Driven Algorithm
(Example)
Scheduled Activity
events list
a=1 e=1 t=0 c=0 d, e
c=1 0 2
1
g=1
2
2 2 d = 1, e = 0 f, g
d=0
3
Time stack
4 f=0
b=1 4 g=0
5
g 6 f=1 g
0 4 8
Time, t 7
8 g=1
Efficiency of Event-Driven Simulator
 Simulates events (value changes) only

 Speed up over compiled-code can be ten times or more; in large
logic circuits about 0.1 to 10% gates become active for an input
change
Steady 0 Large logic

Steady 0 block without
(no event) activity
0 → 1 event

Summary
 Logic or true-value simulators are essential tools for design
verification.
 Verification vectors and expected responses are generated (often
manually) from specifications.
 A logic simulator can be implemented using either compiled-code
or event-driven method.
 Per vector complexity of a logic simulator is approximately linear in
circuit size.
 Modeling level determines the evaluation procedures used in the
simulator.

CHAPTER FIVE
TESTING

Testing
 Introduction:
In VLSI design once you design a circuit in different levels such as
Behavioral level,
RTL(functional )netlist level,
gate level netlist
switch(transistor)level
finally you have a finished product in the form of a chip or ASIC.
So the natural question that can be raised here is, the proper
functionality of the chip to its intended specifications .
The goal of testing is to do this verification process of the chip to
it intended specification.

Testing
 Why do we need testing ?
Possibility of errors during design process
There cab be bugs in the translation process(viz. the CAD tool
used )
Possibility of faults during fabrication/ packaging
Necessary to test each and every chip before they can be used
Million and billions of transistors in present- day of VLSI chip
 Chance of fault creeping in is also quite significant
Testing is used to test a circuit whether it is behaving as per as our
specification or not.

Testing
 Basic objectives
 We need testing to determine the presence of faults
in a given circuit/chip
Fallacy:
 testing is used to guarantee that a circuit /chip is fault free
 No amount of testing can give this guarantee
 using testing we can increase our confidence in the correct working of
the circuit / chip
 We usually use verification along with the testing
Distinctly different objectives
 testing means not creating a circuit which is fault free.

Difference between verification and testing
Testing Verification
 Testing tries to guarantee  Verification guarantees

the correctness of the the correctness of the
manufacture circuit or chip design
 Has to be performed in  Performed once before
every manufactured device actual manufacturing of
 Primary responsible for the the circuit or chip
quality of the device that  Primary responsible the
go to the market quality of the design
 Two steps involved  Uses formal methods,
Test generation
simulation etc
Test application

Levels of Testing
 Testing can be carried out at different levels
 Chip Level: when chips are manufactured
 Board Level: when chips are integrated on the board
 System Level: when several boards are assembled
 Other ways categorization which depends on level of abstraction (other ways of define
levels )
 This level of testing is important to develop correct fault models and fault
simulation models
 Transistor level
 Gate level
 Register transfer level (blocks such as MUX,ALU,ADDER etc.)
 Functional /Behavioral level
 Here testing really depends at which level the test engineers are
concetrating on.
 Example: if the test engineer needs to test gate level circuit, he has to
develop fault models and fault simulation models which is pertaining
to the gate level circuit ECEg4191 VLSI DESIGN
05/02/2024 158
Testing
 Rule of thumb or Rule 10
 Detecting a fault early reduces the cost of testing
 Empirical rule: it is ten times more expensive to test a device as we move to
the next higher level
 Important aspects of testing are
 Defect Level
 Testing Time
 The product quality is measured in terms of defects.
 More the number of defective chips, poorer will be the quality of the chip.

Testing
 To test a combinational circuit with completely, we need number of
possible input combinations (or test vectors).
 In case of sequential circuits, the required test vectors would be if
there are m number of registers.
 Example.
For a VLSI chip, if there are 50 inputs and 50 registers inside, it requires test
vectors to fully test it out. Now, if testing one pattern requires 1 ns time, testing
all the test vectors would require years.
 The above example indicates that there must be innovative ways of testing the
chip without applying so many test vectors, but catch all possible defects or
most of the defects.
 Because testing the state table of sequential circuits and all possible
input of combinational circuits is infeasible.

Testing
 Various processes during testing

Fault modelling
 Abstract the physical defects and define a suitable logical model
 Limits/ simplifies the scope of test generation
Test generation
 Give a circuit and a set of faults F, determine test vector T that detects all the
faults in F
Fault simulation
 Give a circuit a set of faults F, and test vector T, determine the faults that are
tested by the test vector T

Cost of Testing
 Design for testability (DFT)
 Chip area overhead: as external testing circuit can be added to the chip area of the chip
increases
 Software process of test
 Test generation: software process executed once during design
 Fault simulation
 Manufacturing test
 Test application: electrical tests applied to hardware using ATE
 Automatic test equipment (ATE): using of this equipment incurs additional cost
 Test centre operational cost
The total cost of testing is the sum of all these costs

Basic principles of testing
 DESIGN FOR TESTABILITY (DFT):
 Formulates a set of design rules , if followed, results in a circuit that will be easily
testable.
 Typically introduce area overhead and performance degradation
 Built-in- Self –Test (BIST):
 The generation and response evaluation of the circuits are performed on chip
 The chip can test itself
 No Additional area over head

Basic principles of testing
 Testing process

Fault and its model
 Fault:- is the manifestation of manufacturing defects in an IC.
 During the IC fabrication, the MOS devices could be fabricated incorrectly, or the
interconnect wires could have open-circuit or short-circuit fault. All these defects lead to
malfunctioning of the IC.
 Fault model can be done at different levels of abstraction with respect to the circuit
description
 The fault models are used to identify different types of faults.
 There are many fault models. A list of fault models is shown in Table below

Common Fault model
 Stuck-at-fault (concentrated on Gate level and RTL level most of the faults can be
modelled using this types of fault model and can cover 95% faults)
 Single stuck -at
 multiple stuck -at
 Transistor fault (can’t be captured using stuck-at faults i.e 0 and1 )
 Open
 Short
 Memory faults
 Coupling
 Pattern - Sensitivity
 PLA faults
 Stuck-at
 Cross point
 Bridging
 Delay faults
 Transition
 Path
 Functional faults (Behavioral description of the circuit that is input and output here
every thin is a black box )
Faults: Sources and Types
 Sources
Design process
Device defects
Manufacturing process
 Types
Physical Faults
Logical faults

Faults models and their sources
 The open-circuit fault is caused by several reasons. Some
of the possible causes are as follows:
 Bad contact
 Over-etched metal
 Break in poly silicon line etc.
The short-circuit fault is also caused by various reasons.
Some of the possible causes are as follows:
 Under-etching of metal lines
 Junction spiking
 Pin holes or shorts through the gate oxide
 Diffusion shorts etc.
Another important fault is the bridging fault that happens

in interconnects. It occurs mainly due to metal coverage
problems.
Physical faults
 Physical Faults: can be changed to Logical Faults
 Leakage short between package leads (short)
 Broken, misaligned, or poor wire bonding(open)
 Stress, peeling … (open or short)
 Metallization(open or short)
 Gate oxide imperfection (open or short)
 Mask misalignment(open or short)
 A physical fault can be mapped to a logical fault as shown in the
above.
 Logical fault models are the most important fault models since
they can cover almost all typed of faults.

Physical fault mapping
 Mapping of physical faults to Logical faults

Logical Faults models
 logical faults models :

 A good fault model has two requirements:
 Accurately reflects the behavior of a physical defect
 Is computationally efficient with respect to simulation
 Current common fault models include:
 Gate level stuck-at faults
 Stuck-at-0 (sa0) & stuck-at-1 (sa1)
 Transistor level stuck faults
 Stuck-on (stuck-closed) & stuck-off (stuck-open)
 Logical faults can be classified into two main subclasses:
 Degradation fault—this degrades the performance of the chip
 A delay fault can be classified as a degradation fault, as it may not cause any functionality
failure, but causes the chip to operate at a slower speed.
 Fatal fault—this causes the chip to malfunction
 The open-circuit and short-circuit faults are often grouped under fatal faults.

 Stuck-at Fault: The most popular fault model is the stuck-at fault
model. In this model, there are two types of logical faults:
 Stuck-at-1 (abbreviated as SA1 or S@1)
 Stuck-at-0 (abbreviated as SA0 or S@0)
 The stuck-at-fault normally occurs due to the short circuit of the
gate of the MOS device to either the or to the ground and metal-
to-metal shorts.
 The number of fault sites in a circuit is given by
 The number of single stuck at-fault is equal to twice the number of

fault sites in the circuit.

Example
1. Find out the number of fault sites and the number of single stuck-at-fault for
the circuit shown in below
Solution :the circuit has 8 signal lines (p,q,r,s,t,u,v, and w)

Each of these lines can have SA0 or SA1 faults, thereby 16 possible
single stuck-at faults
2. Stuck-at-1 fault indicates that a node is shorted to ………

3. Stuck-at-0 fault indicates that a node is shorted to……….

Types of faults

Types Of Faults
 Permanent faults: changes the functional behavior of the chip in a time independent
(permanent ) way
 Design error
 Incorrect connection etc.
 Easier to detect
 Non- permanent faults: occurs randomly and at unpredictable times for
unpredictable time durations
 Difficult to detect
 The fault may not show up during testing
 Online testing is a popular method
 Transient faults are caused due to environmental conditions
 Charged particles ,Variation in pressure ,Vibrant, temperature etc.
 Example bit changed in RAMs caused by (called soft error; no permanent damage)
 Intermittent fault are caused by non environmental conditions and behave like
permanent faults during the duration of the failure
 Loose connection critical timing, change in parameter values etc.
 May require repeated testing for detection

Fault and fault enumeration
 Why fault models ?
 The number of physical defects in chip is too many
 Difficult to count and analyse all possible faults
 We abstract physical defects and define some logical fault models
 Drastically reduces the number of faults to be considered
 Makes test generation and fault simulation possible
 We can evaluate fault coverage and compare test sets

Test vectors for 4-to-1 MUX
 4 –to- 1 MUX
 Four data inputs and two select inputs and one out put function
 Test vectors can be generated directly from the function behaviour of
MUX

Test of Gate level circuits
 Circuit is specified as a netlist, typically at the level of gates and flip- flops
 The assumptions when we test gate level circuits
 The blocks (gates ) are fault free
 The interconnection between blocks can be faulty
 The basic idea is to ensure that the interconnections are fault free and are able to
carry both logic 0 and logic 1 signals
 Popular gate level fault modes are
 Stuck-at-0 fault model
 Stuck-at-1fault model
 Example 2-input xor function realized using 2-inpu NAND gates
 The circuits has 12 lines which are sites of faults and 24 stuck at faults

Types of stuck-at-faults
 There are two types of stuck-at faults, they are of
 Single stuck-at
 Multiple stuck-at
 Single stuck-at model is the most popular fault model
 Why single stuck-at faults
 Simpler to handle computationally
 Readable good fault coverage
 A test set for detecting single stuck-at faults detects large number of
multiple stuck-at faults as well.
 Three properties of single stuck-at faults
 Only one line is faulty at a time
 The faulty line is set to 1 or 0
 The fault can be at input or output of gate/ module

Types of stuck-at-faults

Signle stuck-at-faults

Cont…

Switch level fault Model
 Here the circuit is specified at transistor level

For example , a Netlist of CMOS gates
MOS transistors are considered as ideal switch in this model
→nMOS transistor is ON when the gate is at logic 1
→pMOS transistor is ON when the gate is at logic 0
 Two types of switch level fault models are common
 Stuck open fault : A transistor never turns ON (source drain opened )
 Stuck short fault : a transistor is always ON (source drain shorted )
 The stuck open and short faults can’t be detected by the stuck at
1 or 0 faults tests because they change the behavior the circuit
particularly

Stuck open fault model
 A transistor becomes permanently non-conducting due to some
faults
 The gate output may depend on its previous state
 We say that the circuit exhibits sequential behaviour
 Typically requires two test vectors that are to be applied in
sequence_ called 2-pattern test
 Sometimes the test vectors of a given single stuck at fault test
set rearranged so as to satisfy the 2-pattern test requirement
 We take the examples of a 2-input NOR gate.

 Consider stuck-open fault
 When output will be in
absence of fault
 In presence of the fault, the
output is floating and the
voltage at will depend on the
charge stored in the load
capacitor
 We apply two pattern:

Stuck short fault model
 A transistor is permanently conducting in the presence of a
fault
 Checking the logic value at the output may not be sufficient
 Both PUN and PDN networks may become conducting, thereby
causing the output to reach some indeterminate level (acting as
voltage divide )
 High current will be flowing from
 To detect this type of fault, we need to monitor the current
flowing
 Called testing
 Test vector causes a conducting path from in the presence of fault

 Consider stuck-short fault
 When output will be in absence of
fault (PDN conducts)
 In presence of the fault, the PUN
starts conducting, results in high
current from
 Output becomes indeterminate
(denoted as X)
 Observation:
 Testing is loosing relevance in sub-micron CMOS technology, as the
transistor leakage currents become comparable with current.

How to reduce number of faults
 Some properties of faults that occur in gates can help us in reducing the
effective number of faults to be considered
 Some techniques used for fault collapsing or reducing
 Fault equivalence
 Fault dominance
• Two fault in a circuit are said to be equivalent if the corresponding faulty
functions are identical
 Input stuck-at- 0 and out put stack-at-0 in AND gate
 Input stuck-at- 1 and out put stack-at-1 in OR gate
 For every such equivalence class, we retain only one fault and remove the
rest
 Called equivalence fault collapsing

Fault collapsing
 All single faults of a logic circuit can be divided in to disjoint
equivalence subsets
 All faults in a subset are mutually equivalent
 A collapsed fault set contains one fault from each equivalent subset
 Example 2-input and gate
 Here all sa0 faults are equivalent
 We can collapse two the three sa0 faults

 Here the broken line indicates equitant Faults

Fault equivalence

equivalence class

Fault dominance
 If all tests for some fault , also detect another fault ,then is said to
dominant ,denoted as .
 Output stuck –at-1 dominates input stack –at -1 in AND gate
• For every such dominance relation we retain and remove .
 Called dominant fault collapsing
• If two faults dominate each other, they are equivalent
• Example 3-input NAND gate

Fault dropping
• We carry out fault simulation to determine the faults that are
detected by a given test set
 Time complexity is a function of the number of faults that are possible
 Good if we can reduce the number of faults
• Fault dropping
 It refers to a technique where the faults detected by a test vector are
removed from the fault list prior to the fault simulation with any
subsequent vector
 Prevent repeat test generation for detected faults

Check points heuristic
 The primary inputs and fan-out branches of a combinational circuits
are called check points
 In the circuits as shown, check points are marked as RED
 Check points theorem

 A simple heuristic for fault collapsing (often used in practice )
 A test set that detects all single (multiple ) stuck-at faults on all check points of
a combinational circuit ,also detects all single (multiple ) stuck-at faults in that
circuits
• Note: the
non-red colour check points are collapsed by
equivalence and dominance faults
Fault simulation
 Fault simulation is simulating of a digital circuit in the presence of faults
 Its main goal is:
 Measuring the effectiveness of the test pattern
 Generating fault dictionaries
 Guiding the test pattern generator program
 Its output is:
 Fault coverage (i.e. fault detected by test vectors)
 Set of undetected fault
 Note: fault simulator affects the speed of the overall fault simulation.
Fault simulation
 Given
Circuit, fault model, test set
 Determine
Output response of the faulty circuits
Detects faults, undetected faults- fault coverage

Typical Flow of Fault simulation

Fault simulation
 Four types of fault simulation algorithms:
Serial fault simulation algorithm
 Fault free simulation + fault injection and simulation for each fault.
Parallel fault simulation algorithm
 Uses a bit parallelism of logical operation
Deductive fault simulation algorithm
 Deduce all signal values in each faulty circuit from
simulated fault free circuit.
Concurrent fault simulation algorithm
 All events of fault free and all faulty circuits are
implicitly simulated

Fault simulation
 Serial fault simulation algorithm:
 True-value simulation is performed across all vectors and outputs saved.
 Run fault free logic simulation store good outputs
 Faulty circuits are simulated one-by-one by modifying circuit and running
true-value simulator.
 For every fault: modify good circuit (faulty injection) to obtain a faulty circuit
 Compare faulty output with stored goof out puts
 Faulty is detected if they are different
 Simulation of faulty circuit stops as soon as fault is detected.
 Advantage:
 Easy to implement(regular logic simulator)
 Ability to simulate many fault models (stuck-at, delay, bridge,…)
 Disadvantage
 Long CPU time

Fault simulation
 Serial fault simulation algorithm…
 Disadvantage:
 Many simulation runs required „ CPU time prohibitive for VLSI
circuits

Fault simulation
 Serial fault simulation algorithm…
 Example:

Fault simulation
 Parallel fault simulation algorithm:
Assumption:
 The simulated circuit consists of only logic gates and all gates have
the same delays „
 Signals take only binary (0 and 1) values
Taking advantage of inherent parallel operation of computer
words to simulate faulty circuits in parallel with fault-free
circuit
Run parallel logic simulation with W-1(W is CPU word size )
Advantage:
 Straight forward and memory efficient

Fault simulation
 Parallel fault simulation algorithm…
Disadvantage:
 Lacking the capability to simulate accurate rise and fall delays of
signals „
 Not suitable for circuits with non-Boolean logic
Example: Consider w=3

Fault simulation
Example: Consider three faults: B/1, F/0, and J/0

Fault simulation
 Fault injection: inserting fault(s) in to circuits

Fault simulation
 Exercise :consider two faults use parallel fault simulation on test sets
 Solution :
 010 and 001 detects f
 100 detects g

Fault simulation
 Deductive fault simulation algorithm:
 Only the fault free circuit is simulated
Faulty circuit values are deduced from the fault-free values
It processes all faults in a single pass of true-value simulation,
i.e., it very fast!
 A vector is simulated in true-value mode.
A deductive procedure is then performed on all lines in level-
order from inputs to outputs
Fault lists are generated for each signal using the fault lists on
the inputs to the gate generating that signal

Fault simulation
 Deductive fault simulation algorithm: procedures
 Apply a test pattern perform fault free simulation
 A fault list are applied attached to each PI(primary input)
 Stuck at value opposite to its good value
 Fault list are propagated from PI to PO
 Rule depends on gate type and gate input
 A fault is detected if it is in fault list of a PO(primary output)

Fault simulation
Deductive fault simulation algorithm…
 Rules for fault list propagation:
 Where:
 La and Lb indicates
the error produced
in line a and b
respectively.
 C1 and C0 indicates
an internal faults
producing incorrect
output

Fault simulation
 Deductive fault simulation algorithm…
Note: from probability concept
Suppose: A = {1,2,3}, B = {3, 4, 5}

A u B: all elements of A and B
A n B: elements found in both A and B
A/B: elements which is found in A not in B
A Δ B: opposite of intersection
A’: the elements which are not found in set A

Fault simulation
c. Deductive fault simulation algorithm
Example:

Fault simulation
Exercise: fault list propagation rule for OR gate
 Exercise :total 18 uncollapsed faults (for explanation purpose )

Set of test vectors
7 faults are detected by P1
Detected faults are dropped
18-7=11 remained faults which are undetected

Fault simulation
 Considering the second test pattern one more fault is detected
and 11-1=10 are remained

Fault simulation
 Considering the third test pattern one more fault is detected
and 10-3=7 are remained

Fault simulation
 Boolean difference
 Consider say for example a four variable function f
given as
 Boolean difference of f with respect to A is defined as
Boolean difference example

Find the test vector for node-a if it is stuck-at-0 and
stuck-at-1

Fault simulation: Boolean difference

Fault simulation
 Concurrent fault simulation algorithm:
Event-driven simulation with fault-free and faulty
circuits simulated altogether
A list per gate containing copies of the gate from
all faulty circuits in which this gate differs
Event-driven simulation is carried out.
Good-events and fault-events make good-gates
active
for evaluation.
Good-events also make bad-gates active for
evaluation
Faster than other methods, but uses most memory

Cont…

Cont…

Cont…

Cont…example

Cont…example

Cont…example

Bad event

Bad event

Fault simulation
 Concurrent fault simulation algorithm…
 Example:

Vlsi Design 21

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Vlsi Design 21

Uploaded by

Copyright:

Available Formats

“THE BEST WAY TO LEARN IS BY DOING”

05/02/2024 ECEg4191 VLSI DESIGN 5

05/02/2024 ECEg4191 VLSI DESIGN 6

05/02/2024 ECEg4191 VLSI DESIGN 8

05/02/2024 ECEg4191 VLSI DESIGN 9

05/02/2024 ECEg4191 VLSI DESIGN 10

Cell based Array based

05/02/2024 ECEg4191 VLSI DESIGN 11

05/02/2024 ECEg4191 VLSI DESIGN 12

05/02/2024 ECEg4191 VLSI DESIGN 13

05/02/2024 ECEg4191 VLSI DESIGN 14

05/02/2024 ECEg4191 VLSI DESIGN 15

05/02/2024 ECEg4191 VLSI DESIGN 16

05/02/2024 ECEg4191 VLSI DESIGN 17

05/02/2024 ECEg4191 VLSI DESIGN 18

05/02/2024 ECEg4191 VLSI DESIGN 19

05/02/2024 ECEg4191 VLSI DESIGN 20

 The design methodology that uses standard cells is known as cell

 Standard cells are the basic building blocks of cell-based IC design

 A standard cell is designed either to store information or perform a

05/02/2024 ECEg4191 VLSI DESIGN 21

05/02/2024 ECEg4191 VLSI DESIGN 25

05/02/2024 ECEg4191 VLSI DESIGN 26

05/02/2024 ECEg4191 VLSI DESIGN 27

05/02/2024 ECEg4191 VLSI DESIGN 28

05/02/2024 ECEg4191 VLSI DESIGN 29

05/02/2024 ECEg4191 VLSI DESIGN 30

05/02/2024 ECEg4191 VLSI DESIGN 31

05/02/2024 ECEg4191 VLSI DESIGN 32

05/02/2024 ECEg4191 VLSI DESIGN 33

05/02/2024 ECEg4191 VLSI DESIGN 34

 The other features of CMOS transistors are as follows:

05/02/2024 ECEg4191 VLSI DESIGN 35

05/02/2024 ECEg4191 VLSI DESIGN 38

 Here in this discussion we have to consider the following conditions

05/02/2024 ECEg4191 VLSI DESIGN 39

05/02/2024 ECEg4191 VLSI DESIGN 40

05/02/2024 ECEg4191 VLSI DESIGN 41

05/02/2024 ECEg4191 VLSI DESIGN 42

05/02/2024 ECEg4191 VLSI DESIGN 43

05/02/2024 ECEg4191 VLSI DESIGN 44

05/02/2024 ECEg4191 VLSI DESIGN 45

05/02/2024 ECEg4191 VLSI DESIGN 46

05/02/2024 ECEg4191 VLSI DESIGN 47

• We first consider the CMOS gate that realizes the two-

05/02/2024 ECEg4191 VLSI DESIGN 48

• The two-input NAND function is described by the

05/02/2024 ECEg4191 VLSI DESIGN 49

05/02/2024 ECEg4191 VLSI DESIGN 50

 Obtaining the PUN form PDN

05/02/2024 ECEg4191 VLSI DESIGN 51

1. The PDN can be most directly synthesized by

END OF CHAPTER ONE

05/02/2024 ECEg4191 VLSI DESIGN 53

05/02/2024 ECEg4191 VLSI DESIGN 54

 Standard logic devices refers to the basic functional digital

05/02/2024 ECEg4191 VLSI DESIGN 57

05/02/2024 ECEg4191 VLSI DESIGN 58

05/02/2024 ECEg4191 VLSI DESIGN 59

 Simple programmable logic devices (SPLDs),

 Together, CPLDs and FPGAs are often referred to as high- capacity

05/02/2024 ECEg4191 VLSI DESIGN 60

 Programmable link process technology