Digital Electronics

REC202
(Sequential Circuit)
Unit-V
 Combinational Logic

Combinational Logic:
• Output depends only on current input
• Has no memory
• In combinational circuits, the outputs at any
instant of time are entirely dependent upon the
input present at that time.
 Sequential Logic
Sequential Logic:
• Output depends not only on current input but
also on past input values, e.g., design a counter.
• Need some type of memory to remember the
past input values.
• Although every digital system have
combinational circuits, most systems include
memory elements. Theses circuits are known as
sequential circuits.
• The storage elements are circuits that are
capable of storing binary information: memory.
 Sequential Circuits
Circuits that we Information Storing
have learned Circuits
so far

Timed “States”

May 8, 2024 Sequential Circuits

 Synchronous Sequential Circuits:
Flip flops as state memory

 The flip-flops receive their inputs from the

combinational circuit and also from a clock signal
with pulses that occur at fixed intervals of time,
as shown in the timing diagram.
May 8, 2024 Sequential Circuits
 Block diagram of sequential circuit

• A block diagram of a sequential circuit is shown in Figure . It consists of a

combinational circuit to which storage elements are connected to form a
feedback path. The storage elements are devices capable of storing binary
information. The binary information stored in these elements at any given
time defines the state of the sequential circuit at that time.
• The sequential circuit receives binary information from external inputs that,
together with the present state of the storage elements, determine the
binary value of the outputs. These external inputs also determine the
condition for changing the state in the storage elements. The block diagram
demonstrates that the outputs in a sequential circuit are a function not only
of the inputs, but also of the present state of the storage elements. The
next state of the storage elements is also a function of external inputs and
the present state. Thus, a sequential circuit is specified by a time sequence
of inputs, outputs, and internal states . In contrast, the outputs of
combinational logic depend only on the present values of the inputs.
 Types of sequential circuits
• There are two main types of sequential circuits, and their classification is a function
of the timing of their signals. A synchronous sequential circuit is a system whose
behavior can be defined from the knowledge of its signals at discrete instants of
time. The behavior of an asynchronous sequential circuit depends upon the input
signals at any instant of time and the order in which the inputs change. The storage
elements commonly used in asynchronous sequential circuits are time-delay
devices.

• A synchronous sequential circuit employs signals that affect the storage elements
at only discrete instants of time. Synchronization is achieved by a timing device
called a clock generator.
• Synchronous sequential circuits that use clock pulses to control storage elements
are called clocked sequential circuits and are the type most frequently encountered
in practice. They are called synchronous circuits.
 Synchronous vs. Asynchronous

There are two types of sequential circuits:

• Synchronous sequential circuit: circuit output

changes only at some discrete instants of time. This
type of circuits achieves synchronization by using a
timing signal called the clock.

• Asynchronous sequential circuit: circuit output can

change at any time (clockless).
 Flip-flops
• The storage elements (memory) used in clocked sequential circuits are called
flipflops.
• A flip-flop is a binary storage device capable of storing one bit of information
In a stable state, the output of a flip-flop is either 0 or 1.
• A sequential circuit may use many flip-flops to store as many bits as necessary.
• The outputs are formed by a combinational logic function of the inputs to the
circuit or the values stored in the flip-flops (or both).
• The value that is stored in a flip-flop when the clock pulse occurs is also
determined by the inputs to the circuit or the values presently stored in the
flip-flop (or both).
• The new value is stored (i.e., the flip-flop is updated) when a pulse of the clock
signal occurs.
• The major differences among various types of storage elements are in
the number of inputs they possess and in the manner in which the
inputs affect the binary state.
• Storage elements that operate with signal levels (rather than signal
transitions) are referred to as latches ; those controlled by a clock
transition are flip-flops .
• Latches are said to be level sensitive devices; flip-flops are edge-
sensitive devices.
• The two types of storage elements are related because latches are
the basic circuits from which all flip-flops are constructed.
• Although latches are useful for storing binary information and for the
design of asynchronous sequential circuits, they are not practical for
 Basic flip-flop or SR Latch
• The SR latch is a circuit with two cross-coupled NOR gates
or two cross-coupled NAND gates, and two inputs labeled
S for set and R for reset. The SR latch constructed with two
cross-coupled NOR or NAND gates are shown in Figures.
We must remember that the output of a NOR gate is 0 if any input is 1,
and that the output is 1 only when al inputs are 0. As a starting point,
assume that the set input is 1 and the reset input is 0. Since gate 2 has an
input of 1, its output Q’ must be 0, which puts both inputs of gate 1 at 0,
so that output Q is 1. When the set input is returned to 0, the output
remains the same, because output Q remains a 1, leaving one input of
gate 2 at 1. That causes output Q’ to stay at 0, which leaves both inputs of
gate number 1 at 0, so that output Q is a 1. In the same manner it is
possible to show that a 1 in the reset input changes output Q to 0 and Q’
to 1. When the reset input returns to 0, the outputs do not change.
When a 1 is applied to both the set and the reset inputs, both Q
and Q’ outputs go to 0. This condition violates the fact that outputs Q and
Q’ are the complement of each other. In normal operation this condition
must be avoided by making sure that 1’s are not applied to both inputs
simultaneously.
The latch has two useful states. When output Q = 1 and Q’ = 0, the
latch is said to be in the set state. When Q = 0 and Q’ = 1, it is in the reset
state . Outputs Q and Q’ are normally the complement of each other
RS flip-flop

0 1 0
0 1 1
0 0 1
0
1
 Latches with control input

• SR latch

• D(Transparent or Data) latch

Clock response in latch and flip-flop
D flip-flop
JK flip-flop
T (Toggle) flip-flop
Graphical symbol of flip-flops
 Flip-flops characteristic and excitation tables
Characteristic tables (short form) Excitation tables

Characteristic tables
Q S R Q(t+1) Q J K Q(t+1) Q D Q(t+1) Q T Q(t+1)
0 0 0 0 0 0 0 0 0 0 0 0 0 0
0 0 1 0 0 0 1 0 0 1 1 0 1 1
0 1 0 1 0 1 0 1 1 0 0 1 0 1
0 1 1 X 0 1 1 1 1 1 1 1 1 0
1 0 0 1 1 0 0 1
1 0 1 0 1 0 1 0
1 1 0 1 1 1 0 1
1 1 1 X 1 1 1 0
 Triggering of flip-flops
• The state of flip-flop is switched by a momentary change in
the input signal. This momentary change is called a trigger
and the transition it causes is said to trigger the flip-flop.
• Asynchronous circuits (latch) are triggered by signal level.
This level must be returned to its initial value (0 in NOR and
1 in NAND latch) before a second trigger is applied.
• Synchronous circuits (flip-flop) are triggered by pulses. A
pulse starts from an initial value of 0, goes momentary to 1,
and after a short time, returns to its initial 0 value.
• There are two types of flip-flops based on triggering :
Master slave flip-flop and Edge triggered flip-flops.
 Registers

A register is a group of flip‐flops, each one of

which shares a common clock and is capable of
storing one bit of information. An n‐bit register
consists of a group of n flip‐flops capable of
storing n bits of binary information.
 SHIFT REGISTERS

• A register capable of shifting the binary information

held in each cell to its neighboring cell, in a selected
direction, is called a shift register. The logical
configuration of a shift register consists of a chain of
flip‐flops, with the output of one flip‐flop connected to
the input of the next flip‐flop. All flip‐flops receive
common clock pulses, which activate the shift of data
from one stage to the next.
Serial Transfer
 Universal Shift Register
• The most general shift register has the following capabilities:
1. A clear control to clear the register to 0.
2. A clock input to synchronize the operations.
3. A shift‐right control to enable the shift‐right operation and the serial
input and output lines associated with the shift right.
4. A shift‐left control to enable the shift‐left operation and the serial
input and output lines associated with the shift left.
5. A parallel‐load control to enable a parallel transfer and the n input
lines associated with the parallel transfer.
6. n parallel output lines.
7. A control state that leaves the information in the register unchanged
in response to the clock. Other shift registers may have only some of
the preceding functions, with at least one shift operation.
• A register capable of shifting in one direction only is a unidirectional
shift register. One that can shift in both directions is a bidirectional
shift register. If the register has both shifts and parallel‐load
capabilities, it is referred to as a universal shift register.
 COUNTER

A counter is essentially a register that goes through a

predetermined sequence of binary states. The gates in
the counter are connected in such a way as to produce
the prescribed sequence of states. Although counters are
a special type of register, it is common to differentiate
them by giving them a different name.
 COUNTERS

A register that goes through a prescribed sequence

of states upon the application of input pulses is
called a counter . The input pulses may be clock
pulses, or they may originate from some external
source and may occur at a fixed interval of time or
at random. The sequence of states may follow the
binary number sequence or any other sequence of
states. A counter that follows the binary number
sequence is called a binary counter . An n ‐bit binary
counter consists of n flip‐flops and can count in
binary from 0 through 2n - 1.
 Types of COUNTERS

Counters are available in two categories: ripple

counters and synchronous counters.

Ripple counters :-
In a ripple counter, a flip‐flop output transition
serves as a source for triggering other flip‐flops. In
other words, the CP input of some or all flip‐flops are
triggered, not by the common clock pulses, but
rather by the transition that occurs in other flip‐flop
outputs. In a synchronous counter, the CP inputs of
all flip‐flops receive the common clock.
Four‐bit binary ripple counter
BCD ripple counter
 Ring Counter

Timing signals that control the sequence of operations in a

digital system can be generated by a shift register. A ring
counter is a circular shift register with only one flip‐flop being
set at any particular time; all others are cleared. The single bit is
shifted from one flip‐flop to the next to produce the sequence
of timing signals. Figure (a) shows a four‐bit shift register
connected as a ring counter. The initial value of the register is
1000 and requires Preset/Clear flip‐flops. The single bit is
shifted right with every clock pulse and circulates back from T3
to T0. Each flip‐flop is in the 1 state once every four clock cycles
and produces one of the four timing signals shown in Figure (b).
Each output becomes a 1 after the negative‐edge transition of a
clock pulse and remains 1 during the next clock cycle.
 Johnson Counter

• A k ‐bit ring counter circulates a single bit among the

flip‐flops to provide k distinguishable states. The
number of states can be doubled if the shift register is
connected as a switch‐tail ring counter. A switch‐tail
ring counter is a circular shift register with the
complemented output of the last flip‐flop connected to
the input of the first flip‐flop.
• A Johnson counter is a k ‐bit switch‐tail ring counter
with 2 k decoding gates to provide outputs for 2 k
timing signals. The decoding gates are not shown in
Figure, but are specified in the last column of the table.
The eight AND gates listed in the table, when connected
to the circuit, will complete the construction of the