Course Title: DIGITAL LOGIC & MICROPROCESSOR

Course Code: ISWE201P

DIGITAL ASSIGNMENT-1

Name of the Student: NARRAVULA VENKATA LOKESWAR REDDY

Registration Number: 23MIS0283
Programme: M.Tech-Software Engineering
School: School of Computer Science Engineering and Information Systems(SCORE)
1. Verification of Logic gates
a) Verify the working of OR gate with its truth table

b) Verify the working of AND gate with its truth table

c) Verify the working of NOT gate with its truth table
d) Verify the working of NOR gate with its truth table
e) Verify the working of NAND gate with its truth table
f) Verify the working of X- OR gate with its truth table
g) Verify the working of X-NOR gate with its truth table
OR GATE OUTPUT:

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AND GATE OUTPUT:

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NOT GATE OUTPUT:

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NAND GATE OUTPUT:

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NOR GATE OUTPUT:

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XOR GATE OUTPUT:

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XNOR GATE OUTPUT:

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2. Verification of Boolean Expressions
a) X+X’Y=X+Y
OUTPUT:

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b) X’+XY=X’+Y
OUTPUT:

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c) AB+A’C+BC=AB+A’C
OUTPUT:

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d) PQ+Q’R+WPRQ=PQ+Q’R
OUTPUT:

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3. Design a logic circuit to check whether the given 4 bit binary number
is prime or not.
OUTPUT:

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4. You are asked to design the following circuit for your car. The
warning signal W should be set to high voltage (logical 1) if:
a) the engine is running, and door is open; or
b) With the engine running, somebody is sitting in the driver’s seat
and the belt is not fastened.
Otherwise output of the circuit is „0‟. The circuit should rely on the
following sensors:
sensors from engine (C=„1‟ if engine is running, otherwise it is „0‟)
Seat sensor (S=1 if somebody is sitting on the seat, otherwise „0‟)
Door sensor (D=1 if the door is closed, otherwise „0‟)
Belt sensor (B=1 if the belt is fastened, otherwise „0‟)
OUTPUT:

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5. Design a Half adder, Full adder, Half Subtractor and Full Subtractor.
HALF ADDER:
OUTPUT:

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Full adder:
OUTPUT:

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Half Subtractor
OUTPUT:

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Full Subtractor
OUTPUT:

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6. Find the sum and the difference of the following two
binary numbers.
A=1101 B=1010

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7. Implement the following function using 8x1 Multiplexer F(A,B,C,D)=Σ (0,1,3,4,8,9,15)
OUTPUT:

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8. Design Full Adder using i) 4:1 MUX ii) 8:1 MUX
i) 4:1 MUX OUTPUT:

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ii) 8:1 MUX

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9. Design a BCD to Excess-3 code converter.
OUTPUT:

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10.Design a circuit using decoder that counts the number of 1’s present in 3 inputs A,
B and C. Its output is a two-bit number X1X0, representing that count in binary.
OUTPUT:

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11.An ABCD to seven segment decoder is a combinational circuit that converts a decimal digit in BCD to an
appropriate code for the selection of segments in an indicator used to display the decimal digit in a similar
form. The seven outputs of the decoder (a, b, c, d, e, f, g) select the corresponding segments in the display
as shown in the Figure
a) The numeric display chosen to represent the decimal digit is shown in the Figure
b) Using a truth table and k maps, design the BCD to seven segment decoder using a minimum number of
gates. The six invalid combinations should result in a blank display.
OUTPUT:

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12. Design a 2 bit magnitude Comparator whose inputs are A(A1 A0) and B(B1 B0).
OUTPUT:

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