Actel FPGAs

The basic architecture of Actel FPGAs, depicted in Figure 1,

is similar to that found in MPGAs, consisting of rows of
programmable cells, called Logic Modules (LMs), with
horizontal routing channels between the rows. Each routing
switch in these FPGAs is implemented by a novel device
called an anti-fuse which normally resides in a high-
impedance state but takes on a low resistance (about 500
ohms) when "programmed" by a high voltage pulse. Actel
currently has three generations of FPGAs, called the Act-
1,Act-2 and Act-3
General Architecture of Actel FPGAs

Figure.1
 Actel Act-1
• The Act-1 LM that is shown in Figure. 2
illustrates a very different approach from that
found in Xilinx FPGAs., while Xilinx utilizes a
large, complex CLB,
• Actel advocates a small, simple LM. the Act-1
LM is based on a configuration of multiplexers,
which can implement any function of two
• variables, most functions of three or four
variables as well.
Architecture of Act-1 FPGA

Figure.2
 Architecture of Act-1 FPGA
• The Act-1employs four distinct types of
routing resources:
• Input segments
• Output segments
• Clock tracks
• Wiring segments.
 Architecture of Act-1 FPGA
• Input segments connect four of the LM inputs to the
Wiring segments above the LM and four to those below.
• Output segment connects the LM output to several
channels, both above and below the module.
• The Wiring segments consist of straight metal lines of
various lengths that can be connected together through
anti-fuses to form longer lines.
• The Act-1 features 22 tracks of Wiring segments in each
routing channel and, although not shown in the figure, 13
vertical tracks that lie directly on top of each LM
column. Clock tracks are special low-delay lines that are
used for signals that must reach many LMs with
minimum skew.
Architecture of Act-1 FPGA
 Routing in Actel FPGAs

Figure (a) shows an example of routing in which the connections C1 to C4

are to be routed.

Figure (b) indicates how the connections might be routed in mask-

programmed channel, where there is complete freedom for placing the wire
segments. The Channel is divided into columns as shown by placing vertical
segments . Some columns represent logic block pins and others are vertical
feed-throughs.
 Routing in Actel FPGAs

Figure (c) depicts one extreme for track segmentation, in which track is
fully segmented. In this case each segment spans only one column,
meaning that multiple segments are required for every connection. A
routing solution can be obtained using straight-forward algorithm, such as
left-edge algorithm. In this algorithm, the connections are first sorted in
ascending order accordingly left most pins. Each connection is then
assigned to the first track that is available.
 Routing in Actel FPGAs

Figure (d) shows a channel in which each track contain

contains only one segment for its entire length. In this case,
the number of tracks required for routing is always equal to
the number of connections. No routing algorithm is necessary
since any choice of track for a connection will do. The problem
with this segmentation is that access area is required for large
number of tracks and each connection will be subjected to a
large capacitive load due to the long segments.
 Routing in Actel FPGAs

An intermediate approach to channel segmentation is

shown in Figure (e) where the tracks have segments
of various lengths. Each connection must be routed in
single segment, since no switches are available where
segments in a same track meet. This 1-segment
problem is a special case of segmented routing and
can be solved using simple algorithm.
 Routing in Actel FPGAs

Another flexibility in the channels can be added by

allowing segments to be joined by switches as shown
in Figure (f). This implies that the connections can
occupy more than one segments.