Day 9- LCD ,Seven Segment Interface

Quote of the Day

Imagination and Visualization is more
important than knowledge
What you will Learn Today
 Interface LCD with FPGA
 Seven Segment Interface with FPGA
 About pantechsolutions
● Manufacturers of Lab equipment's(ECE &EEE) and
Sensor Interface
● Manufacturer of Brainsense EEG Headset
● Reconfigurable Algorithms on AI
● Manufacture of AI development Boards
Vision: To help 10 millions students to learn technology
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 About me

My Primary Expertise
Microcontroller Architecture: 8051,PIC,AVR,ARM,MSP430,PSOC3
DSP Architecture: Blackfin,C2000,C6000,21065L Sharc
FPGA: Spartan,Virtex,Cyclone
Image Processing Algorithms: Image/Scene Recognition, Machine Learning, Computer Vision, Deep Learning,
Pattern Recognition, Object Classification ,Image Retrieval, Image enhancement and denoising.
Neural Networks : SVM,RBF,BPN
Cryptography :RSA,DES,3DES,Ellipti curve,Blowfish,Diffe Hellman
Compilers: Keil,Visual DSP++,CCS, Xilinx Platform studio,ISE, Matlab, Open CV

www.pantechsolutions.net https://www.linkedin.com/in/jeevarajan/
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Spartan 6 FPGA Board

● Xilinx’s Spartan®-6
XC6SLX16-2FTG256C
● MT41J128M16JT-25(DDR3)
● 50MHz Clock
● M25P80 SPI Flash
Board Specifications
● On-Board FPGA: XC6SLX16-2FTG256C;
● On-Board FPGA external crystal frequency: 50MHz;
● XC6SLX16-2FTG256C has rich block RAM resource up to 576Kb
● XC6SLX16-2FTG256C has 14,579 logic cells;
● On-Board M25P80 SPI Flash ， 1M bytes for user configuration code;
● On-Board 256MB Micron DDR3, MT41J128M16JT-125
● On-Board 3.3V power supply for FPGA by using MP2359 wide input range DC/DC
● XC6SLX16 development board has two 64p, 2.54mm pitch headers for extending user IOs.
● All IOs are precisely designed with length matching
● XC6SLX16 development board has 3 user switches
● XC6SLX16 development board has 4 user LEDs;
● XC6SLX16 development board has JTAG interface, by using 6p, 2.54mm pitch header;
● XC6SLX16 development board PCB size is: 6.7cm x 8.4cm;
● Default power source for board is: 1A@5V DC, the DC header type: DC-050, 5.5mmx2.1mm
JTAG Interface –To Program FPGA & UART TO
USB
 PIN DETAILS
PIN NO DESCRIPTION PIN NO DESCRIPTION PIN NO DESCRIPTION
1 GND 11 F13 21 K12
2 VCC 12 G14 22 M16
3 GND 13 H16 23 N16
4 E13 14 G11 24 M14
5 B16 15 H14 25 C13
6 C16 16 J16 26 P16
7 D16 17 J12 27 R16
8 E16 18 J13 28 T15
9 F16 19 K16 29 T14
10 F12 20 L14 30 R12
31 GND
32 VCC
Schematic for Seven Segment Interface

Each of the seven segment contains LEDs can be turned on by sending active low signal.
Seven Segment Display
X g f e d c b a HEX DIGIT
1 1 0 0 0 0 0 0 C0 0
1 1 1 1 1 0 0 1 F9 1
1 0 1 0 0 1 0 0 A4 2
1 0 1 1 0 0 0 0 B0 3
1 0 0 1 1 0 0 1 99 4
1 0 0 1 0 1 1 0 92 5
1 0 0 0 0 0 1 0 82 6
1 1 1 1 1 0 0 0 F8 7
1 0 0 0 0 0 0 0 80 8
1 0 0 1 1 0 0 0 98 9
1 0 0 0 1 0 0 0 88 A
1 0 0 0 0 0 0 0 80 B
1 1 0 0 0 1 1 0 C6 C
1 1 0 0 0 0 0 0 C0 D
1 0 0 0 0 1 1 0 86 E
1 0 0 0 1 1 1 0 8E F
Schematic for LCD Connection with FPGA
LCD Command
"38",X"0c",X"06",X"01",X"C0",
Character Display LCD

0011 0001 -X”31”

0011 0010 -X”32”

LCD
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity lcd is
port ( clk : in std_logic; ----clock i/p

lcd_e : out std_logic; ----enable control

lcd_rs : out std_logic; ----data or command control
data : out std_logic_vector(7 downto 0)); ---data line
end lcd;
constant N: integer :=22;

type arr is array (1 to N) of std_logic_vector(7 downto 0);

constant datas : arr :=

(X"38",X"0c",X"06",X"01",X"C0",X"31",X"32",X"33",X"34",X"35",X"36",x"37",x"38",x"39",x"41",x"42",x"43",

x"44",x"45",x"47",x"48",x"49"); --command and data to display

begin
process(clk)
variable i : integer := 0;
variable j : integer := 1;
begin
if clk'event and clk = '1' then
if i <= 1000000 then
i := i + 1;
lcd_e <= '1';
data <= datas(j)(7 downto 0);
elsif i > 1000000 and i < 2000000 then
i := i + 1;
lcd_e <= '0';
elsif i = 2000000 then
j := j + 1;
i := 0;
end if;
if j <= 5 then
lcd_rs <= '0'; ---command signal
elsif j > 5 then
lcd_rs <= '1'; ----data signal
end if;
if j = 22 then ---repeated display of data
j := 5;
end if;
end if;
end process;
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