FEATURES OF 8086 MICROPROCESSOR

 16 bit microprocessor
 20 address lines i.e 220=1MB memory addressed.

 16 bit address and data bus multiplexed i.e AD0-AD15 to

minimize no of pin on IC
 Clock frequency between 5Mhz-10Mhz

 Arithmetic operation on 8 bit or 16 bit signed or unsigned

data including multiplication & division
 Operate in single processor or multiprocessor

 256 interrupt

 Operate in max& min mode to achieve high performance

Block diagram of 8086

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BLOCK DIAGRAM OF 8086
BLOCK DIAGRAM OF 8086

 The architecture of 8086 microprocessor is composed of

2 major units
 1) BIU (Bus Interface Unit ) and

 2) EU (Execution Unit)
BUS INTERFACE UNIT (BIU)
BIU
 An 8086 microprocessor exhibits the property of pipelining the
instructions in a queue while performing decoding and
execution of the previous instruction.
 This saves the processor time of operation by a large amount.

 This pipelining is done in a 6-byte queue.

BIU

 Also, the BIU contains 4 segment registers. Each

segment register is 16-bit.
 The segments are present in the memory and these
registers hold the address of the segments.
 These registers are as follows:

 1. Code segment register (CS)

 2. Stack segment register (SS)

 3. Data segment register (DS)

 4. Extra segment register (ES)

 The IP is the instruction pointer

BIU

 Bus Interface unit :

- It acts as interface between system bus and the execution unit.
 Fetches instruction from memory.
 Reads data from I/O ports and memories.
 Writes data to I/O ports and memories
 Supports pipelining.
- BIU handles transfer of data on all the buses for the execution
unit.
1) Queue:
- To speed up the program execution BIU fetches as many as 6
instruction bytes from memory .
- These pre-fetched instruction byte for execution unit in FIFO
group of registers called a QUEUE.
 THE
THE QUEUE
QUEUE (Q)
(Q)

• The BIU uses a mechanism known as an

instruction stream queue to implement a
pipeline architecture.

• This queue permits pre-fetch of up to 6

bytes of instruction code.

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 THE QUEUE (Q)

• Whenever the queue of the BIU is

not full, it has room for at least two
more bytes and at the same time the
EU is not requesting it to read or
write operands from memory, the
BIU is free to look ahead in the
program by pre-fetching the next
sequential instruction.

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• These pre-fetching instructions are held in its
FIFO queue.

• With its 16 bit data bus, the BIU fetches two

instruction bytes in a single memory cycle.

• After a byte is loaded at the input end of the

queue, it automatically shifts up through the
FIFO to the empty location nearest the
output.

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• The EU accesses the queue from
the output end. It reads one
instruction byte after the other from
the output of the queue.

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EXECUTION UNIT

The execution unit of 8086 informs BIU about

address of instruction &
data needed for execution &
execute it.
EXECUTION UNIT (EU)
FUNCTIONAL BLOCK OF EU

Control circuit ,instruction decoder , ALU

 The execution unit contain control circuit that
direct all internal operation.
 The execution unit has 16 bit ALU block that
perform arithmetic & logical operation like +,
- , *,AND , OR ,NOT
 The instruction decoder in EU that translates
the instruction fetch from memory into a
series of action that EU carried out.
Software Model of the 8086 Microprocessors

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8086/88
8086/88internal
internalregisters
registers16
16bits
bits(2
(2bytes
byteseach)
each)

AX, BX, CX and DX are two

bytes wide and each byte can
be accessed separately

These registers are used as

memory pointers.

Flags will be discussed later

Segment registers are used

as base address for a segment
in the 1 M byte of memory
 The execution unit has 8 general purpose register labeled as
AH, AL, BH, BL, CH, CL, DH, DL
o These register can be used for temporary storage of 8 bit data &
16 bit data
- AH-AL pair is referred as AX , BH- BL pair is referred as BX ,
CH-CL pair is referred as CX , DH-DL pair is referred as DX.
 1) Stack pointer register: (SP)
 It contain a 16 bit offset
 Its offset address is relative to the stack segment.
 It is used to point the current top value of stack
2) Base pointer register:(BP)
It is of 16 bits.
act as an offset to point data in the stack segment.
 It is primarily used in accessing parameters passed by the
stack
Unlike SP, we can use BP to access data in the other
segments.
3) Source index register: (SI)
-The source index register is used to hold the 16 bit offset of a data
word in data segment .

4) Destination index register:(DI)

-It is used to hold the 16 bit offset of a data word in extra segment
while executing string instruction
 8086 Registers
General Purpose Index
AH AL
BP
AX

SP
BH BL
BX
SI

CH CL
DI
CX

DH DL
DX Segment

CS

Status and Control SS

Flags DS

IP ES

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 8086 REGISTERS
1)Data Registers
AX,BX,CX,DX
2)Address Registers
a> Base registers: BX,BP
Index registers :SI,DI
Instruction pointer: IP
b> Segment registers
CS,SS,DS,ES
3)Flag register (PSW)
 General Purpose Registers

AX - the Accumulator
BX - the Base Register
CX - the Count Register
DX - the Data Register

• Normally used for storing temporary results

• Each of the registers is 16 bits wide (AX, BX, CX, DX)
• Can be accessed as either 16 or 8 bits AX, AH, AL
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 General Purpose Registers
• AX
– Accumulator Register
– Preferred register to use in arithmetic, logic and data
transfer instructions because it generates the
shortest Machine Language Code
– Must be used in multiplication and division
operations
– Must also be used in I/O operations

• BX
– Base Register
– Also serves as an address register

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 General Purpose Registers
• CX
– Count register
– Used as a loop counter
– Used in shift and rotate operations

• DX
– Data register
– Used in multiplication and division
– Also used in I/O operations

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 Pointer and Index Registers

• All 16 bits wide, L/H bytes are not accessible

• Used as memory pointers

– Example: MOV AH, [SI]
• Move the byte stored in memory location whose address is contained in
register SI to register AH

• IP is not under direct control of the programmer

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8086 Microprocessor
Architecture Bus Interface Unit (BIU)

Segment Instruction Pointer

Registers
16-bit

Always points to the next instruction to be executed within

the currently executing code segment.

So, this register contains the 16-bit offset address pointing

to the next instruction code within the 64Kb of the code
segment area.

Its content is automatically incremented as the execution of

the next instruction takes place.

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• Concept of Memory
Segmentation in 8086
&
Physical address calculation

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• The 1Mbyte memory is divided into segments
• We have 16-bits logical address (because the
registers are in 16-bits), so we have maximum
memory size locations which are addressed by
16-bits as below:
• 216 = 65,536 = 64K
• Thus, any location within the segment can be
accessed using 16-Bits.
• The 8086 allows only four active segments at a
time
• For the selection of four active segments the 16-
bit segment registers are provided
The four segment registers are:

 Code Segment (CS) Register

 Data Segment (DS) Register
 Stack Segment (SS) Register
 Extra Segment (ES) Register

These are used to hold the upper 16-bits of the starting

addresses of the four memory segments.

The starting address also called base address or segment

address.
• Functions of Segment Registers

 The CS register holds the upper 16-bits of the

starting address of the segment from which
the BIU is currently fetching the instruction
code byte.
 The SS register is used for the upper 16-bits of the starting address for the
program stack (all stack related instructions will operate on stack).

 ES register and DS register are used to hold the upper 16-bits of the starting
address of the two memory segments which are used for data.
• Note:
• By default BX, SI and DI registers work with DS
segment register
• BP and SP work with SS segment register.
• IP work with CS segment register.
 Program Segments
Code segment
• The 8086 fetches the instructions (opcodes and
operands) from the code segments.

• The 8086 address types:

• Physical address
• Offset address
• Logical address
• Physical address
• 20-bit address that is actually put on the
address pins of 8086
• Decoded by the memory interfacing circuitry
• A range of 00000H to FFFFFH
• It is the actual physical location in RAM or
ROM within 1 MB mem. range
• Offset address:
• A location within a 64KB segment range
• A range of 0000H to FFFFH

• Logical address:
• consist of a segment value and an offset
address
• Logical address:
– Consist of a CS (code segment) and an IP (instruction
pointer)
• format is CS:IP

• Offset address
– IP contains the offset address

• Physical address
– generated by shifting the CS left one hex digit and then
adding it to the IP
– the resulting 20-bit address is called the physical
address
Suppose we have:
CS 2500
IP 95F3

• Logical address:
– Consist of a CS (code segment) and an IP (instruction pointer)
format is CS:IP 2500:95F3H

• Offset address
– IP contains the offset address which is 95F3H

• Physical address
– generated by shifting the CS left one hex digit and then adding it to the
IP
25000 + 95F3 = 2E5F3H
41
 • The following examples shows the
CS:IP scheme of address
formation:
CS IP 8AB4
34BA Code
34BA0
segment
Inserting a hexadecimal 0H (0000B)
with the CSR or shifting the CSR
8AB4
four binary digits left
(offset)
3D654

34BA0(CS)+
8AB4(IP)
3D65 4 (next address)
44B9F
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Example: The following operation illustrates the generation of 20-bit physical address from
CS and IP registers.

Let: CS = 3 4 8 A H , IP= 4 2 1 4 H

Therefore,
Physical Address = Offset + Segment Register (Shifted by 1 digit in Hexadecimal)
Example:
If CS=24F6h & IP=634Ah, show the;
1- The logical address
2- The offset address
3- The physical address
4- The lower range of the segment
5- The upper range of the segment

Solution:
1- The logical address is the CS: IP content which is: 24F6:634A
2- The offset address is the content of the IP register which is: 634A
3- The physical address:
4- The lower range of the segment:

5- The upper range of the segment:

Default Registers Assigned to store offset
values for different segments

CS DS ES SS

BX,
SI, SP,
IP DI
DI BP

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Segment
Segment and
and Address
Address register
register combination
combination

• CS:IP

• SS:SP SS:BP
• DS:BX DS:SI
• DS:DI (for other than string
operations)
• ES:DI (for string operations)

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 Flag Register

Overflow Carry
Direction Parity

Interrupt enable Auxiliary Carry

Trap Zero
6 are status flags
Sign
3 are control flag
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 8086 Microprocessor
Architecture Execution Unit (EU)
Auxiliary Carry Flag
Carry Flag
Flag Register This is set, if there is a carry from the
This flag is set, when there is
lowest nibble, i.e, bit three during
addition, or borrow for the lowest a carry out of MSB in case of
nibble, i.e, bit three, during addition or a borrow in case
subtraction. of subtraction.

Sign Flag Zero Flag Parity Flag

This flag is set, when the This flag is set, if the result of This flag is set to 1, if the lower
result of any computation the computation or comparison byte of the result contains even
is negative performed by an instruction is number of 1’s ; for odd number
zero of 1’s set to zero.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

OF DF IF TF SF ZF AF PF CF

Trap Flag
Over flow Flag If this flag is set, the processor
This flag is set, if an overflow occurs, i.e, if the result of a signed
enters the single step execution
operation is large enough to accommodate in a destination
mode by generating internal
register. The result is of more than 7-bits in size in case of 8-bit
signed operation and more than 15-bits in size in case of 16-bit interrupts after the execution of
sign operations, then the overflow will be set. each instruction

Direction Flag Interrupt Flag

This is used by string manipulation instructions. If this flag bit
is ‘0’, the string is processed beginning from the lowest Causes the 8086 to recognize
address to the highest address, i.e., auto incrementing mode. external mask interrupts; clearing IF
Otherwise, the string is processed from the highest address disables these interrupts.
towards the lowest address, i.e., auto incrementing mode. 49
 Source Block Destination Block

DS:SI 11 DS:4000H ES:7000H

ES:DI 00
22 :4001H 00 7001H
33 4002H 00 7002H
44 4003H 00 7003H
55 4004H 00 7004H
66 4005H 00 7005H
77 4006H 00 7006H
88 00 7007H
4007H

DF = 0 Lowest address to highest address

DF = 1 Highest address to lowest address

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8086 Microprocessor
Architecture

8086 registers
categorized 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

into 4 groups OF DF IF TF SF ZF AF PF CF

Sl.No. Type Register width Name of register

1 General purpose register 16 bit AX, BX, CX, DX

8 bit AL, AH, BL, BH, CL, CH, DL, DH

2 Pointer register 16 bit SP, BP

3 Index register 16 bit SI, DI

4 Instruction Pointer 16 bit IP

5 Segment register 16 bit CS, DS, SS, ES

6 Flag (PSW) 16 bit Flag register

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8086 Microprocessor
Architecture Registers and Special Functions

Register Name of the Register Special Function

AX 16-bit Accumulator Stores the 16-bit results of arithmetic and logic

operations

AL 8-bit Accumulator Stores the 8-bit results of arithmetic and logic

operations

BX Base register Used to hold base value in base addressing mode

to access memory data

CX Count Register Used to hold the count value in SHIFT, ROTATE

and LOOP instructions

DX Data Register Used to hold data for multiplication and division

operations

SP Stack Pointer Used to hold the offset address of top stack

memory

BP Base Pointer Used to hold the base value in base addressing

using SS register to access data from stack
memory

SI Source Index Used to hold index value of source operand (data)

for string instructions

DI Data Index Used to hold the index value of destination

operand (data) for string operations 52
 8086 Programmer’s Model
ES Extra Segment
CS Code Segment
BIU registers SS Stack Segment
(20 bit adder)
DS Data Segment
IP Instruction Pointer

AX AH AL Accumulator
EU registers BX BH BL Base Register
CX CH CL Count Register
DX DH DL Data Register
SP Stack Pointer
BP Base Pointer
SI Source Index Register
DI Destination Index Register
FLAGS

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