Digital design 1

Les van vandaag (Week 4)

• Ffs
– Adder/substractor
– Comparator
• CPU design
– ALU design
• Sequential logic
– Introduction

Digital design 1
Design een 16 bits adder/subtractor circuit

Sel=0 Add
Sel=1 Sub

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 Oefening VHDL: library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
A B entity ADD_SUB is
port (
A, B: in std_logic_vector(15
Symbol: sel
downto 0);

Result CoBo sel: in std_logic;

Result: out std_logic_vector(15 downto 0);
A B CoBo: out std_logic);
end ADD_SUB;
architecture RTL of ADD_SUB is

begin
ADD: process ( )
begin
Add Sub -- add process
end process;
S1 Co S2 Bo SUB: process ( )
begin
-- sub process
Sel Select end process;
SELECT: process( )
begin
-- select process
end process;
Result CoBo end behavior;

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N-bits Digital Comparator

A Eq

B Gt
St
 Het is combinatorisch

 Het heeft twee inputs van eender welke grootte

 Het kan meerdere outputs hebben (hangt af van wat er gevraagd

wordt)
 Een digital comparator gaat twee inputs vergelijken en geeft aan

of A<B, A=B of A>B

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Schrijf een code die de input A en B gaat vergelijken

A 3
2- VHDL
3 Eq
B library ieee;
use ieee.std_logic_1164.all;

entity comp is
1- Truth Table, minimization etc.. port (
A, B: in std_logic_vector(2 downto 0);
A2A1A0 B2B1B0 Eq Eq: out std_logic
);
000 000 1 end comp;
000 001 0
000 010 0 architecture behavior of comp is
Begin
000 011 0
000 100 0 process( )
000 101 0 begin
……………… …
…………….. … end process;
100 10 1 End behavior;
0 …
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…………….. …
……………..
 A7 Epar

Parity generator A0

1- Truth table 2- VHDL

library ieee;
use ieee.std_logic_1164.all;

entity comp is
port (
A7, A6, A5, A4, A3, A2, A1, A0: in
std_logic; par: out std_logic
);
end comp;

architecture behavior of comp is

begin

process()
begin

end process;
end behavior;
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ALU design

Digital design 1
8
Computer architecture

 CPU

 Memory Central
Input
Processing Memory
 Input
Unit (CPU) Output
 Output

9
Central Processing Unit

Central Processing Unit

Control Arithmetic
Unit (CU) Logic
Unit
(ALU)
1
0
Arithmetic Logic Unit (ALU)
• Een arithmetic logic unit (ALU) is een digitale circuit die gebruikt wordt om
aritmetische en logische operaties toe te passen.
• Het representeert een fundamenteel blok voor een central processing unit
(CPU) van een computer.
• Moderne CPUs hebben een complexe en krachtige ALUs. Daarbij hebben
moderne CPUs ook een control unit (CU).
• Je kan eender welke functie toevoegen aan de ALU.

11
ALU design oefening

Oefening: Design een ALU met de volgende

functies:
- Input A en B met 4 bits
- Functies OR, AND, Addition en substractor

12
ALU design oefening
1- Select function
ALU design oefening
1- Subfunctions block diagram
ALU with the functions OR, AND, SUB and ADD
3- Truth table of VHDL library ieee;
use ieee.std_logic_1164.all;

entity ALU is
port ( A,B: in std_logic_vector(3 downto 0);
Sel : in std_logic_vector (1 downto 0);
result: out std_logic_vector (3 downto 0)
);
end ALU ;

architecture behavior of ALU is

begin
process( ) begin

end process;
end behavior;

9
Sequential design

Digital design16
1
Computer architecture

 CPU

 Memory Central
Input
Processing Memory
 Input
Unit (CPU) Output
 Output

1
7
 System
Sequential Systems
Feedback

C ABC Q

& 010 0
A
& Q
011 0
111 1
B 110 0

AB Q

A & 01 0

B
& Q
11 0

10 1
11 1
10
Sequential vs. combinational

Inputs Outputs
Inputs
# Outputs

Outputs = f (current Inputs) Outputs = f (current Inputs,

Combinational systems zijn memoryless inputs from the past)

 Output hangt af van current input en past inputs

 Nodig om deze inputs te splitsen in previous,
current, future
 Past inputs moeten opgeslagen worden – memory!
(ook states)
19
Moore Machine

Embedded Connectivity 20
Exercise 1: Parity generator
•In serial data transmission, a common format is 8 data bits, a parity bit (odd or even), a start bit and
one or two stop bits. Hence a parity generator is needed at the sender side and a parity checker is
needed at the receiver side (Example: UART). Parity bits are used as the simplest form of error
detecting code.
•Design a circuit that detects whether there are an odd number of 1s in an input bit stream. Assume
that the rate of inputs is 1 every clock cycle.

21
Exercise 1
1
0
S1

IsOdd=0
S2

IsOdd=1
rst
0
1

bit
# IsOdd

Exercise: Give the VHDL code for the odd

parity generator rst clk

22
Exercise 1

ARCHITECTURE parity_check_architecture OF parity_check IS

--signals goes here
type t_State is (odd, even);
signal ps, ns : t_state;
BEGIN

Digital design 1 23
Exercise 1
Exercise 1

Digital design 1 25
Exercise 1 ARCHITECTURE parity_check_architecture OF parity_check IS
--signals goes here
type t_State is (odd, even);
signal ps, ns : t_state;
BEGIN

next_state_decoder: process(ps, data_in) begin

case ps is
when odd => if data_in = '1' then ns <= even; else ns <= odd; end if;
when even => if data_in = '1' then ns <= odd; else ns <= even; end if;
when others => null;
end case;
end process;

memory: process( nrst,clk) begin

if nrst = ‘0' then ps <= even;
elsif rising_edge(clk) then ps<=ns;
end if;
end process;

output_decoder: process(ps) begin

case ps is
when odd => is_odd <= '1';
when even => is_odd <= '0';
when others => null;
end case;
end process;

END parity_check_architecture;

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