A PRESENTATION ON INTERNSHIP AT

Guided By : Prof . Rohit Parmar

Subject Name : Industrial Internship
Subject Code : 102000801
Presented By : Tanish Shah
Enroll No. : 12002060501028
Agenda

• Brief Profile of Company

• Timeline
• Verilog
• System Verilog
• Project
• Summary
Brief Profile of Company
• Headquartered in Silicon Valley, California, Scaledge has development
centers in Canada, the United Kingdom, and India. Since its inception,
Scaledge's robust team of specialists have been assisting customers in
bringing advanced products to markets quickly and efficiently.
• We specialize in developing integrated hardware and software solutions that
support the semiconductor, AI/ML, and IoT industries across many domains
such as consumer durables, storage, automotive, wireless, and data center.
• Our competence in VLSI across processors, SoCs, and sub-systems, and our
maturity in providing solutions in AI/ML and embedded software,
distinguishes us as a "Partner of Choice" for our customers.
• Our vision is to be the world’s best Technology Design Center by being the
first choice for leading companies who want to build innovative products,
and being the top choice for talents who want to steer their successful
journey for knowledge and growth.
TimeLine

January
Digital Electronics Basic Linux & GVIM

February
Verilog (Hardware Description Language)

March & April

System Verilog (Hardware Verification Language)
Verilog
Verilog HDL​
Implemented Digital Circuits ​
Memory Design & Verification​
Single Port​
Real Dual Port​
Dynamic Memory Controller
True Dual Port ​
Finite State Machine​
Seq. Detector​
Vending Machine​
Self-Checking Test-bench​
Code Coverage​
Regression
Mini-Projects
Asynchronous FIFO​
• Designed RTL​
• Verified Test-Cases​
• Self-Checking Test-bench​
• Achieved 100%
Code Coverage​
• Regressions​
Round Robin Arbiter​
• Designed RTL​
• Verified Test-Cases​
• Self-Checking Testbench​
• Achieved 100%
Code Coverage​
• Regressions​
System Verilog

Data Types​

Structure & Union​

Casting​ Object Oriented Programming concepts​

Arrays​
Inheritance​
Static array​

Dynamic array​ Polymorphism​

Associative array​
Encapsulation​
Queue array
Enumeration
System Verilog

Inter Process Communication​ Constraint &​

Mailbo Randomization
x​ • System Verilog allows users to specify
Event​ constraints in a compact, declarative
way which are then processed by an
internal solver to generate random
Semaphore​ values that satisfy all conditions.
SV Layered TB
APB TO I2C bridge

 APB to I2C Bridge helps to communicate between two protocols i.e.,

• Advanced peripheral Bus Protocol (APB Protocol )
• Inter Integrated Communication (I2C Protocol )
 Requirement of Bridge
• APB and I2C protocols works on different clock frequency.
• APB performs parallel data transfer while I2C performs serial data transfer.
 Project in three phase
• APB slave RTL design and verification
• I2C master and slave RTL design and verification
• Combining both as bridge and verifying the RTL design.
Activities

1. Verilog HDL programming

• Deep learning of the hardware language.
2. Pre-requisites for the project
• APB and I2C protocol specification.
• Asynchronous FIFO design and verification.
3. APB development and verification
• APB Slave RTL design and verification.
4. SPI development and verification
• I2C Master - Slave RTL design and verification.
5. Bridge development and verification
• Combining APB Slave, I2C master and Asynchronous FIFO as Bridge.
Block Diagram
FIFO Observation
APB Observation
I2C observation
Conclusion

• During the training, learned about Verilog Hardware Language and

understood concepts about the verification part in VLSI industry.
• Designing synthesizable RTL designs and further verifying them to
ensure proper working of the design.
• APB to I2C Bridge helps to perform data transfer between two protocols
working at different frequencies and working with different peripherals.
• The verification phase was crucial as it confirmed that my design is both
reliable and functional.
Q&A
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