Professional Documents
Culture Documents
Comb Cir
Comb Cir
Arithmetic / logic circuit Comparators / parity generators Multiplexers / demultiplexers Encoders / decoders
5/2/2012
B
0 1
SUM
0 1
CY
0 0
1
1
0
1
1
0 1 0
0
1 0 1
Cy 1= AB
1
5/2/2012
1
1
Digital Logic Version 1.0
0
1
1
1
2
Carry
AND
5/2/2012 Digital Logic Version 1.0 3
Full Adder
Full Adder with input A, B and C. Outputs are Sum and Carry.
A
0
B
0
C
0
SUM
0
CY
0
0
0 0 1
0
1 1 0
1
0 1 0
1
1 0 1
0
0 1 0
1
1 1
5/2/2012
0
1 1
1
0 1
Digital Logic Version 1.0
0
0 1
1
1 1
4
00
0
A`B 01
0
AB
AB`
11 1
10
0
C 1
Cy = AB + BC + AC
5/2/2012 Digital Logic Version 1.0 5
Full adder
A B C EXOR SUM
EXOR
Cy
AND
AND
5/2/2012 Digital Logic Version 1.0
OR
6
An N Bit Adder
An Bn Cn-1 A2 B2 C1 A1 B1 C0 A0 B0
FA
Over Flow
C2
FA
FA
C1
HA
C0
Sum n
Sum2
Sum1
Sum0
5/2/2012
The adder-subtracter
A7 B7 A6 B6 A5 B5 A4 B4 A3 B3 A2 B2 A1 B1 A0 B0
Sub
FA S7 Carry
5/2/2012
FA S6
FA
FA
FA
FA
FA S1
FA S0
8
Assignment
Q.Design a seven segment LED display
5/2/2012
Comparator
To compare relative magnitude of two binary numbers Assume two bit input A and B Outputs
A > B ( A greater than B) A < B ( A less than B) A = B ( A is equal to B)
5/2/2012
10
A0
0 0 0 0 1 1 1 1 0
B1
0 0 1 1 0 0 1 1 0 0
B0
0 1 0 1 0 1 0 1 0 1
A>B
0 0 0 0 1
A=B
1 0 0 0 0
A<B
0 1 1 1 0
0
0 0 1 1 0 0 1 1 1 0
1
0 0 0 0 1 0 0 0 0 1
0
0 1 0 0 0 0 0 0 0 0
1
1 1 1 1 1 1
0
0 0 1 1 1 1
1
1 0 0 1 1
0
1 0 1 0 1
5/2/2012
11
A>B
B1B0 A1A0
00 0 0
01 1 0
11
10 1 1
00
1
1
01
11
10
5/2/2012
0
12
A=B
B1B0 A1A0
00
01
11
10
00
1
0
0
1
0
0
0
0
01
11
10
5/2/2012
1
13
A<B
B1B0 A1A0
00
01
11
10
00
0
1
0
0
0
0
0
0
01
11
10
5/2/2012
0
14
A>B
5/2/2012
A<B
Digital Logic Version 1.0
A=B
15
Assignment
Design a 4-bit magnitude comparator
5/2/2012
16
Multiplexers
Data selectors Muxes are widely used in circuits select one input from many
N inputs
MUX
1 Output
M
2 =N M select inputs
5/2/2012 Digital Logic Version 1.0 17
2 to 1 Multiplexer
Sel 0 0 0 0 1 1 1 1 A 0 0 1 1 0 0 1 1 B 0 1 0 1 0 1 0 1 O 0 0 1 1 0 1 0 1
AB
Sel 0 1
00 0 0
01 0 1
11 1 1
10 1 0
5/2/2012
18
2 to 1 MUX. Circuit
O = Sel. A + sel.B A AND
Sel
O B AND
Digital Logic Version 1.0 19
OR
NOT
5/2/2012
Boolean functions of N+1 variables can be N implemented using 2 -to- 1 Multiplexer N of the these variables used as selection lines of the MUX and remaining single variable of the function is used for the inputs of the MUX.Suppose A is this single variable , inputs of the MUX to be chosen to be either A or A`or 0 or 1 In this way ,it is possible to generate any N function of N+1 variables with a 2- to-1 Multiplexer
5/2/2012 Digital Logic Version 1.0 20
Example
Demonstrate this procedure with a example : F(A,B,C) = (1, 3, 5, 6)
Solution:
Assume that ordered sequence of variables chosen for the minterms is ABCD , where A is the leftmost variable in ordered sequence of n variables and BCD . . .are the remaining n-1Digital Logic Version 1.0 . variables 5/2/2012 21
Procedure
Connect the n-1 variables to the selection lines of the Multiplexer , with B connected to the highorder selection line ,C to the next lower selection lines of Multiplexer and so on down to the last variable , which is connected to the lowest-order selection line s0 .
Digital Logic Version 1.0 22
5/2/2012
Procedure
Consider now the single variable A, since this variable is in the highestorder position in the sequence of variables, it will be complemented in minterms 0 to (2/2) - 1, which comprise the first half in the list of minterms The second half of minterms will have their A variable uncomplemented
5/2/2012 Digital Logic Version 1.0 23
Procedure
For a three-variable function, A,B,C we have eight minterms.Variable A is complemented in minterms 0 to 3 and uncomplemented in minterms 4 to 7 List the inputs of MUX and under them list all the minterms in two terms
5/2/2012 Digital Logic Version 1.0 24
Procedure
The first row lists all those minterms here A is complemented Second row minterms with A uncomplemented Circle all the minterms of the function and inspect each column separately according the following rules
5/2/2012 Digital Logic Version 1.0 25
Rules
If the two minterms in a column are not circled , apply 0 the corresponding Multiplexer input If the two miniterms are circled , apply 1 to the corresponding Multiplexer input
5/2/2012 Digital Logic Version 1.0 26
Rules
If the bottom minterm is circled and the top is not circled, apply A to the corresponding Multiplexer input If the top minterm is circled and the bottom is not circled ,apply a` to the corresponding Multiplexer input
5/2/2012 Digital Logic Version 1.0 27
Truth table
Minterm
A 0 0 0 0 1
B 0 0 1 1 0 0 1 1
C 0 1 0 1 0
F 0 1 0 1 0 1 1 0 (c ) Implementation table I0 I1 I2 I3
0 1 2 3 4
A`
A
0
4 0
1
5 1
2
6 A
3
7 A`
5
6 7
1
1 1
1
0 1
LOGIC DIAGRAM
1 A A`
4X1 MUX
B C MUX Implementation
5/2/2012 Digital Logic Version 1.0 29
Demultiplexers
Logic circuit with one input and many outputs. Can steer the input to one of the output.
N Output signals
1 input signal
DMUX
. . 2=N
M
. . . M control signals
5/2/2012 Digital Logic Version 1.0 30
2 to 4 Demultiplexer
Data A Data A B O[0:3] B
1 1 1 1
0 0 1 1
0 1 0 1
1 2 4 8
O[0]
O[1]
O[2]
O[3]
5/2/2012 Digital Logic Version 1.0 31
Assignment
Design a 8-to-1 Multiplexer using 2-to-1 Multiplexer
Decoder
Multiple outputs and inputs For n inputs and m outputs then m <=2n One of the output will respond to a permissible combination of inputs Also known as minterm recognizer
5/2/2012 Digital Logic Version 1.0 33
2 to 4 Decoder
Sel A B
Sl
B O[0:3]
O[0]
1 X 0 0 0 0 0 1 0 1
5/2/2012
X 0 1 0 1
0 1 2 4 8
Digital Logic Version 1.0
O[1]
O[2]
O[3]
34
BCD-to-DECIMAL Decoder
Convert binary coded decimal (BCD) to decimal . The input ranges from . Also called 1-of-10 decoder.
5/2/2012
35
BCD-to-DECIMAL Decoder
A B C D
O[0]
O[1]
O[2]
. . .
O[9]
5/2/2012 Digital Logic Version 1.0 36
Assignment
Design a 4-to-16 decoder using 3-to-8 decoder
5/2/2012
37
Encoder
Generates code based on inputs For an m output code , the input should satisfy 2m >= n Only one input is asserted at a time Priority encoder - each input assigned a priority with respect to other inputs
5/2/2012 Digital Logic Version 1.0 38
Decimal-to-BCD Encoder
Convert decimal active input signal to binary coded decimal output signal.
Decimal-to-BCD Encoder
N inputs
. .
.... M outputs
5/2/2012 Digital Logic Version 1.0 39
8 9
A
5/2/2012 Digital Logic Version 1.0
D
40
Priority Encoder
E2 Highest, E1 middle and E0 low E2 encoded as 01, E1 as 10 and E0 as 11 Other conditions 00
E2 0 0 0 0 1 E1 0 0 1 1 d E0 0 1 0 1 d O1 O2 0 1 1 1 0 0 1 0 0 1
Truth Table
5/2/2012
41
0 1
E2 E1 00
1 1
0 0
0 0
O1 = (E2E1 + E2E0)
E0 0
01
11
10
0 1
5/2/2012
0
0
1
1
1
1
O0 =( E1E0 + E2)
42
O1
O2
5/2/2012
43
Assignment
TOMMOROW
5/2/2012 Digital Logic Version 1.0 44
PARITY
Even parity: N-bit input has an even
numbers of 1s.
PARITY GENERATOR
An extra bit that is generated and attached to a binary number is known as parity generation. The logic circuit responsible for the generation is known as parity generator.
5/2/2012 Digital Logic Version 1.0 46
PARITY CHECKERS
The logic circuit which checks binary bits at the receiving end is parity checker. Exclusive-OR gates are ideal for generating and checking the parity of a binary number.
5/2/2012 Digital Logic Version 1.0 47
Odd-parity Generation
X7 X6 X5 X4 X3 X2 X1X0
Practical Application
Because of transients,noise and other disturbances, 1-bit errors can occur when binary data is transmitted. Parity generator at the transmitting and parity checker at the receiving end can be used to check 1-bit errors. Parity generator and checker can be odd or even .
5/2/2012 Digital Logic Version 1.0 49
Example
You want to send 0100 0011 Enter the data to a odd parity generator The data to be transmitted will be 0 0100 0011 Send the data 0 0100 0011 to some destination. If no errors occur in transmission , the odd-parity checker at the receiving end will produce a high output Means the received number has odd parity
5/2/2012 Digital Logic Version 1.0 50