BITS Pilani

presentation
R.K.Tiwary
BITS Pilani EEE
Pilani Campus Rk.Tiwari@pilani.bits-pilani.ac.in
 BITS Pilani
Pilani Campus

MEL ZG625, ADV ANALOG & MIXED SIG

DESIGN
Lecture No.8 (Sample and Hold circuit)
MOSFET parameters

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 CHARGE-INJECTION ERRORS(Example)
Assume that a resolution of ±2mV is required from the circuit of Fig.. The following
values are given: C=2pF, Cox=2.1fF/µm2 ,(W/L)3=10µm/0.9µm ,Lov=0.1um,Vtn=0.8V
,VDD=2.6v and Vss=-2.6v. What is the
a. Voltage change due to channel charge?
b. Voltage change due to overlap capacitance
c. Total Voltage change due to both

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CHARGE-INJECTION ERRORS(Example)

additional measures should be taken to

minimize the effects of charge-injection if this
resolution is required

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Minimizing Errors Due to Charge-Injection
 The simplest way to reduce errors due to charge-injection is to use larger capacitors
( slow down the circuits).

 The deleterious effects of charge-injection can be reduced by using “advanced” clocks which
open-circuit the discharge paths through which signal-dependent charge-injection flows.
 When Q2 opens , no path for the charge injected by Q2 to flow

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Minimizing Errors Due to Charge-Injection
Use fully differential design techniques for comparators,

 Clock feedthrough of reset switch Q3a

= that of Q3b
 Differential input voltage is unaffected
 Only errors due to mismatches in the clock
feedthrough of the two switches,
 At least 10 times smaller

A clock generator suitable for generating the

desired clock waveforms for the
comparator

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 In class Exercise 2
The CMOS transmission gate shown in Fig. has an input voltage of 2.5 V when it turns off. The
W/L of the n-channel is 5 μm/0.8 μm and the W/L of the p-channel is 15 μm/0.8 μm. Assume the
total parasitic capacitance between the output node and ground is 50 fF, V DD = 5 V, and that the
clock signals change very fast. Also ignore changes due to overlap capacitance. Estimate the
change in output voltage due to charge-injection. What will the final output voltage be?
Vtn = 0.8 V, γn = 0.5 V1/2 ; Cox = 1.9 × 10–3 pF / μm 2 ; φFn= 0.7v, φFp = 0.8V. (if not given) γp = 0.8
V1/2

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

In class Exercise 2 Contnd.

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

In class Exercise 2 Contnd

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Calculation of the Propagation Delay Time of a Two-
Stage, Open-Loop Comparator
vo1 = +2.5V and vout = -2.5V

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Calculation of the Propagation Delay Time of a Two-
Stage, Open-Loop Comparator

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Calculation of the Propagation Delay Time of a Two-
Stage, Open-Loop Comparator

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Calculation of the Propagation Delay Time of a Two-
Stage, Open-Loop Comparator

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Calculation of the Propagation Delay Time of a Two-Stage,
Open-Loop Comparator

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 In class example 3
What is the gain and -3dB bandwidth (in Hz) of Fig. if CL = 1pF?

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 In class example 3
What is the gain and -3dB bandwidth (in Hz) of Fig. if CL = 1pF?

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Explanation

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 Other Open-Loop Comparator

Evolution of Complementary Self-Biased CMOS Differential

Amplifiers(CSDA

The circuit configurations of both amplifiers differ from those of conventional CMOS differential-
amplifier configurations in two important ways
 The amplifiers are completely complementary, i.e., each n-type device operates in push-pull
fashion with a corresponding p-type device;
 the amplifiers are self-biased through negative feedback.

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 Other Open-Loop Comparator
(a) Two differential amplifiers (b) Evolution of (a) into the self-biased
loading each other differential amplifier.

 ability to sink and source large amounts of current

 When the positive input voltage,v in+ , is increased, the drains of M 1 and M3 fall and turn on M6 to a
large current,
 IM6 is sourced to the output capacitance connected to the drains of M 2 and M4 through M4.

 During this condition, the current in M 5 is zero.

 When vin+ is decreased, M5 turns on and a large current is sunk through the output capacitance via M 2
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
 Complementary Self-Biased CMOS Differential
Amplifiers(CSDA)

 These two differences in the amplifier configurations result in several

performance enhancements:
 less sensitivity of active-region biasing to variations in processing,
temperature, and supply
 capability of supplying switching currents that are significantly greater than
the quiescent bias current
 nominal doubling of differential-mode gain ( + 6 dB).
 A disadvantage of the circuit is that the delay time vin+ from to the output is

slower than from vin- to the output.

 the fall time of the CSDA in this application was significantly better than
the rise time,

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Track-and-hold (T/H) and sample-and-hold (S/H) circuits
 A sample-and-hold circuit is commonly used at the interface between analog and
digital systems to hold a sample of the time-varying signal for a period of time so
that the high-frequency operation is facilitated.
 Realized by combining switching devices, MOS transistors, and capacitors.
 A sample-and-hold circuit takes a sample of the input signal in zero time and holds
the sample value during a period T
The impulse response: h(t) = us(t) − us(t − T )
By computing the s-transform of the impulse response

Hid(s) = [h(t)] = [us(t)} − [us(t − T ) ]

= (1 − e −Ts) [[us(t)] = (1 − e −T s )/s

Using s = jω and the relationship, sin(ωT /2) = (ejωT /2 − e −jωT /2 )/2j,

Hid(jω) = (1 − e −jωT )/jω = [T sin(ωT /2) e −jωT /2 ] /(ωT /2)

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Track-and-hold (T/H) and sample-and-hold (S/H) circuits
Assuming that T = 2π/ωs, we have

Hence, the magnitude and phase of the transfer function, Hid, are given by

Frequency responses of an ideal sample-

and-hold circuit

 Also transfers the aliased frequency

components
 Attenuated by an appropriate filter

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MOS sample-and-hold circuits

MOS sample-and-hold circuit (S/H) or track-and-hold

Used at
 the front end of analog-to-digital (A/D) converters
 back end of digital-to-analog (D/A) converters
 precision analog integrated circuits are mostly implemented by sampled-data
circuits To avoid disturbing the signal source with the
charging current of the capacitor, a frontend
Sample-and-hold basics
buffer is often added before the sample-and-hold
module.
Additionally, a buffer is also frequently placed at
the output to reduce the loss of the stored charge
due to leakage currents

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 Frequency limitations of a non-sampling A/D
converter
Assume that the input to the converter is a sine wave with peak-to-peak amplitude

equal to the full-scale voltage VFS, i.e.

The maximum rate of change of the input signal is

During the conversion time, the maximum acceptable voltage variation is

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Frequency limitations of a non-sampling A/D converter

Considering a 12-bit converter with sampling rate of 100 k Samples/s, the maximum frequency

For simplicity, that the conversion time dt is equal to the inverse of the sampling
frequency fs, rather than less, as is the case in reality

Clearly, this maximum frequency is orders of magnitude lower than the Nyquist rate of 50 kHz.
To avoid this severe frequency limitation, a sample-and-hold function is added at the front end
of the converter. performs the conversion during the hold time in which the signal is constant

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 Different Errors
 Hold-to-track delay, , is the time elapsed from the
initiation of the signal sample acquisition to the instant
when the output starts to change in response to the
input signal.
settling time
 Acquisition time, , is the maximum time required to
acquire the input signal sample to within a specified
error band (e.g., ±0.1% or 1/2 least significant bit for
acquisition time
data converter applications) around the final value of the
output

 Effective aperture delay, , can be defined as the track-to-hold switching delay. It is

the time difference between the propagation delays of the input signal and control
signal up to the switching instant or can be defined as finite time for the switch to
open.
BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956
MOS SAMPLE-AND-HOLD BASICS

 Track-to-hold settling time, τs, is the time necessary for the

track-to-hold switching transient to settle to within a given

error band around its final value

 Droop rate is the variation of the output as a function of

the time due to leakage from the hold capacitor. It is

generally specified in the hold mode with the input held at

a constant dc value.

 Feedthrough attenuation ratio is the fraction of the input

signal that can appear at the output during the hold mode.

It is a measure of the achieved isolation to prevent

undesirable coupling of the input signal to the output.

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 Capacitor values for High resolution
In addition to drift errors, the accuracy of the S/H circuit can be affected by amplifier
offset voltages and various noise sources.
 The switch is modeled by a thermal noise source with the spectral density, ,
associated with the on-resistance, Ron.
 Based on the assumption that the noise signal is filtered
by the transfer function, H(j2πf), the noise spectral density
at the T/H output is given by

 where , , k is Boltzmann’s constant, and T temperature in Kelvin

 The filter transfer function can be expressed as

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 Nosie error
Hence,

By making the output noise spectral density equal to the quantization noise, the capacitor value
can be related to a given resolution.

For applications requiring a high resolution, the capacitor can become impractical to integrate
due to the exponential increase of its value with the number of bits

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 Quantization noise
 Quantization noise is the inherent uncertainty in digitizing an analog value with a finite
resolution converter.
 The quantization noise (or error) is equal to the analog output of the infinite-bit DAC minus the
analog output of the finite-bit DAC
 the quantization noise is a sawtooth
waveform having a peak to-peak value of
1LSB

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 Quantization noise
 The rms value of the quantization noise can be found by taking the root mean square of the
quantization noise

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 Charge Feed through
(sampling pedestal or a hold step.)
sample-and-hold circuits exhibit nonidealities typically
characterized in terms of their sampling pedestal, input
isolation, tracking bandwidth, slew rate, droop rate
 V’=Vin
 V’ has a negative going hold step

The charge flowing to the junction labelled V’

Veff-1 = = VGS1 – Vtn = VDD –– Vtn –– Vin

Here, Vin is the input voltage at the instance Q1 turns off

∆V’, is also linearly related to Vin , which is nonlinearly related to the input signal, V in , due to
variations in the source-substrate voltage triggering a body effect

it is signal independent

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Transfer characteristic considering charge injection
∆V’,is linearly related to Vin, which results in a gain error for the
overall sample-and-hold circuit

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 Sizing of Ron
Applying Kirchhoff’s voltage law around the loop of the S/H
equivalent model with the noise source short-circuited yields

For data converter applications, where the S/H circuit should settle to within the error band of
±0.5 LSB in ts =εT , it is required that

where ε denotes a percentage (usually 50%) of the clock signal period, T

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Sizing of Ron

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 Design Example
Consider a S/H circuit consisting of an NMOS transistor and a hold capacitor of 2 pF. The gate of the
transistor is driven in such a way that the V GS is fixed at 6V, during the track mode. The track mode
duration is 600ps. Find the aspect ratio of the transistor required to limit the error in sampling below
0.2% when the S/H output respond from zero for an input of 3V. Assume µ ncox = 110 µA/V2 ; Vtno= 0.8V

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 Design Example
Consider a S/H circuit consisting of an NMOS transistor and a hold capacitor of 2 pF. The
gate of the transistor is driven in such a way that the V GS is fixed at 6V, during the track
mode. The track mode duration is 600ps. Find the aspect ratio of the transistor required to
limit the error in sampling below 0.2% when the S/H output respond from zero for an input
of 3V. Assume µncox = 110 µA/V2 ; Vtno= 0.8V

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 MOS SAMPLE-AND-HOLD max sampling frequency
We assume that, for appropriate settling, the sampling clock half-period must be larger than five
time constants, therefore

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MOS SAMPLE-AND-HOLD max sampling frequency

I ended here

since the frequency limit is inversely proportional to L2 , switches must be

implemented with the minimum available channel length of the technology

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956