BITS Pilani

presentation
R.K.Tiwary
BITS Pilani EEE
Pilani Campus Rk.Tiwari@pilani.bits-pilani.ac.in
 BITS Pilani
Pilani Campus

MEL ZG625, ADV ANALOG & MIXED SIG DESIGN

Lecture No.6 (Comparator characteristics & Design)
MOSFET parameters

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 Hysteresis

For example, if one has a "low fuel" warning light you don't
want this light to flicker on and off as the fuel sloshes in the
tank
so one sets the threshold to a low level as the fuel is
consumed and to a higher level as the tank is filled

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 Loop Gain Evaluation EXAMPLE 6.1
Assume that all transistors in Fig. are operating in the saturation mode. What is the gain of the
positive feedback loop, M6-M7 using the W/L values and currents of previous excercise

I5 = 50µA

(W/L)1 = (W/L)2 = 5 , (W/L)6 = (W/L)7 = 10 ,

(W/L)3= (W/L)4 = 2

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Loop Gain Evaluation
I5 = 50µA

(W/L)1 = (W/L)2 = 5 , (W/L)6 = (W/L)7 = 10 ,

(W/L)3= (W/L)4 = 2

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Loop Gain Evaluation
I5 = 50µA

(W/L)1 = (W/L)2 = 5 , (W/L)6 = (W/L)7 = 10 ,

(W/L)3= (W/L)4 = 2

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Loop Gain Evaluation

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Propagation Delay Time of a Comparator
Propagation delay time of a noninverting comparator
 Delay between the input excitation and the
output response
 Very important parameter
 Speed limitation in the conversion rate of an A/D
converter
 Varies as a function of the amplitude of the input
 Larger input results in a smaller delay
 Upper limit set by slew rate.
 Normally, the Av(0) and ωc of the comparator are
smaller and larger, respectively, than for an op
differential voltage gain, Av
amp
 Av(0) is the dc gain

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Propagation Delay Time
Rising propagation delay time+ Falling propagation delay time

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Linear Frequency Response – Dominant Single-Pole :

Model:

where Vin = the magnitude of the step input

Slope of the step response

The maximum slope occurs at t = 0 giving,

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Propagation Time Delay
The rising propagation time delay for a single-pole comparator is:

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Propagation Time Delay

Define the minimum input voltage to the comparator as,

Define k as the ratio, Vin, to the minimum input voltage, Vin(min),

Obviously, the more overdrive applied to the input, the smaller the propagation delay time.
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Dynamic Characteristics - Slew Rate of a Comparator :
large signal mode of operation
If the rate of rise or fall of a comparator becomes large, the dynamics may be
limited by the slew rate.
Slew rate comes from the relationship : i = C dv/dt

where i is the current through a capacitor and v is the voltage across it.
If the current becomes limited, then the voltage rate becomes limited. Therefore for
a comparator that is slew rate limited we have

where SR = slew rate of the comparator.

If SR < |maximum slope|, then the comparator is slewing

maximum slope =

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 In class Example_6.2: Propagation Delay Time of a
Comparator
Find the propagation delay time of an open loop comparator that has a dominant pole at 10 3
radians/sec, a dc gain of 104, a slew rate of 1V/µs, and a binary output voltage swing of 1V.
Assume the applied input voltage is 10mV
Solution:
The input resolution for this comparator is 1V/10 4 or 0.1mV.
Therefore, the 10mV input is 100 times larger than v in(min) giving a k of 100. Therefore, we get

For slew rate considerations, we get

Therefore, the propagation delay time for this case is limited by the linear response and is
5.01µs.
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 In class Example_6.3: Performance of a Two-Stage
Comparator
Evaluate VOH, VOL, Av(0), Vin(min), p1, p2, for the
two-stage comparator shown. The large signal
model parameters are KN’ = 110µA/V2 , KP’ =

50µA/V2 , VTN = |VTP| = 0.7V, λN = 0.04V-1 and λP

= 0.05V-1. Assume that the minimum value of VG6

=Solution:
0V and that CI = 0.2pF and CII = 5pF.

VOL is -2.5V. The gain can be found as Av (0) = 7600.

Therefore, the input resolution Vin(min) = (VOH-VOL)/Av(0) = 4.98V/7600 = 0.655mV

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 In class Example_6.3: Performance of a Two-Stage
Comparator
Evaluate VOH, VOL, Av(0), Vin(min), p1, p2, for the
two-stage comparator shown. The large signal
model parameters are KN’ = 110µA/V2 , KP’ =

50µA/V2 , VTN = |VTP| = 0.7V, λN = 0.04V-1 and λP

= 0.05V-1. Assume that the minimum value of
VG6 = 0V and that CI = 0.2pF and CII = 5pF.
Solution:

the poles of the comparator, p1 and p2 .

p1 = -(gds2 + gds4)/CI = 15x10-6(0.04+0.05)/0.2x10-12 = -6.75x106 (1.074MHz)

And

p2 = -(gds6 + gds7)/CII =(95x10-6)(0.04+0.05)/5x10-12 = -1.71x106 (0.272MHz)

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Maximum slope and the time at which this occurs for a
two pole system: Previous circuit example

Assuming that slew doesn’t occur

Normalizing gives,

If p1 = p2 (m=1), then vout’(tn ) = 1 – e-tp – tpe-tp = 1 - e-tn - tne-tn

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Linear Step Response of the Two-Stage Comparator

 The slope at t = 0 is zero

 The steepest slope occurs for
some value of t
 If the slope of the linear response
exceeds the slew rate, then the step
response becomes slew limited.

The maximum load capacitance depends on the slew rate

For the two-stage comparator, the slew rate is

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 Maximum slope and the time at which this oocurs for a
two pole system

The steepest slope occurs at

The instant of maximum slope =

and the steepest slope at tn(max) is

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 In class Example_6.3 - Find the maximum slope of
previous Ex. and the time it occurs if the magnitude of the
input step is vin(min).
Find the maximum slope of previous Ex. and the time it occurs if the magnitude of the input step is
vin(min). If the dc bias current in M7 is 100µA, at what value of load capacitance, C L would the

transient response become slew limited? If the magnitude of the input step is 100v in(min), what is

the new value of CL at which slewing would occur?

Solution:The poles of the comparator were given as p1 = -6.75x106 rads/sec. and

p2 = -1.71x106 rads/sec. This gives a value of m = 0.253.

From the previous expressions, the maximum slope occurs at t n(max) = 1.84 secs.

Time instant of maximum slope t(max) =

The slope of the transient response at this time is found as

Multiplying the above by |p1| gives dvout’(t(max))/dt = 0.159X 6.75x106 =1.072V/µs

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 Example_6.3 . If the dc bias current in M7 is 100µA, at
what value of load capacitance, CL would the transient
response become slew limited?
If the slew rate is less than 1.072V/µs, the transient response will experience slewing

Therefore, CL ≥ 100µA/1.072V/µs or 93.3pF, the comparator will slew.

Increase of input: If the magnitude of the input step is increased to 100v in(min), what is the new

value of CL at which slewing would occur?

=100 x 1.072V/µs = 107.2V/µs

Therefore, the comparator will slew with a load capacitance greater than 0.933pF.
For large overdrives, the comparator will generally experience slewing.

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 Propagation delay time for the two-pole
comparator when no slewing
0.5(VOH + VOL) =

Replace the exponential terms in Eq. with their power series representations.
This results in

can be simplified to

Setting vout(tn) equal to 0.5(VOH + VOL) and solving for tn gives the normalized
propagation delay time, tpn, as

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 Propagation delay time for the two-pole comparator
Example: prediction
Find the propagation delay time of the comparator of Example if Vin =10 mV,

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 Comparator Design

 There are two approaches to the design of the comparator

 slewing response
 then the ability to charge and discharge capacitors becomes more
important.
 Linear response
 The larger the magnitude of the poles, the shorter the propagation
delay time
 The typical input specifications include the propagation time delay, the
output voltage swing, the resolution, and input common-mode range

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 Design of the Two-Stage, Open-Loop
Comparator for Slewing response ;L= 1 µm
Assume the specifications of Fig. are given
tp = 50 ns; VOH = 2 V; VOL = -2 V;

VDD = 2.5V; VSS= -2.5 V; CII = 5 pF;

Vin(min) =1 mV; V+icm = 2V; V-icm = -1.25V Vin =10 mV

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Design of the Two-Stage, Open-Loop Comparator for
Slewing response ;L= 1 µm
Assume the specifications of Fig. are given
tp = 50 ns; VOH = 2 V; VOL = -2 V;

VDD = 2.5V; VSS= -2.5 V; CII = 5 pF;

Vin(min) =1 mV; V+icm = 2V; V-icm = -1.25V

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 Design of the Two-Stage, Open-Loop
Comparator for Slewing response ;L= 1 µm
Assume the specifications of Fig. are given
tp = 50 ns; VOH = 2 V; VOL = -2 V;

VDD = 2.5V; VSS= -2.5 V; CII = 5 pF;

Vin(min) =1 mV; V+icm = 2V; V-icm = -1.25V

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

 Design of the Two-Stage, Open-Loop
Comparator for Slewing response ;L= 1 µm
Assume the specifications of Fig. are given
tp = 50 ns; VOH = 2 V; VOL = -2 V;

VDD = 2.5V; VSS= -2.5 V; CII = 5 pF;

Vin(min) =1 mV; V+icm = 2V; V-icm = -1.25V

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Design of the Two-Stage, Open-Loop
Comparator for Slewing response ;L= 1 µm
Assume the specifications of Fig. are given
tp = 50 ns; VOH = 2 V; VOL = -2 V;
VDD = 2.5V; VSS= -2.5 V; CII = 5 pF;
Vin(min) =1 mV; V+icm = 2V; V-icm = -1.25V

Find CI and check assumption If CI is greater than the guess, increase the value

of CI :

CI = Cgd2 + Cgd4 + Cgs6 + Cbd2 + Cbd4 = (0.66+0.44+120+11.5+6.86)fF

= 139.6fF≤ 0.2pF
AD2 = W2(L1 + L2 + L3) : PD2 = 2(W2 + L1 + L2 + L3) : AD4 = W4(L1 + L2 + L3)

PD4 = 2(W4 + L1 + L2 + L3)

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 Design of the Two-Stage, Open-Loop Comparator for
Slewing response ;L= 1 µm

Method of estimating the source and drain

areas and peripheries.

L1 = Minimum allowable distance between the contact

in S/D and the poly
L2 = Width of a minimum size contact to diffusion
L3 = Minimum allowable distance from the contact in
S/D to the edge of the S/D

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Design of the Two-Stage, Open-Loop Comparator for
Slewing response ;L= 1 µm

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Design of the Two-Stage, Open-Loop Comparator for
Slewing response ;L= 1 µm

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Design of the Two-Stage, Open-Loop Comparator for a
Linear Response
Assume the specifications of Fig. are given
tp = 50 ns; VOH = 2 V; VOL = -2 V;

VDD = 2.5V; VSS= -2.5 V; CII = 5 pF;

Vin(min) =1 mV; V+icm = 2V; V-icm = -1.25V

& overdrive= 10

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Design of the Two-Stage, Open-Loop Comparator for a
Linear Response
Assume the specifications of Fig. are given
tp = 50 ns; VOH = 2 V; VOL = -2 V;

VDD = 2.5V; VSS= -2.5 V; CII = 5 pF;

Vin(min) =1 mV; V+icm = 2V; V-icm = -1.25V

& overdrive= 10

BITS Pilani, Deemed to be University under Section 3 of UGC Act, 1956

Design of the Two-Stage, Open-Loop Comparator for a
Linear Response
Assume the specifications of Fig. are given
tp = 50 ns; VOH = 2 V; VOL = -2 V;

VDD = 2.5V; VSS= -2.5 V; CII = 5 pF;

Vin(min) =1 mV; V+icm = 2V; V-icm = -1.25V

& overdrive= 10

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Design of the Two-Stage, summary

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Improving the Performance of Open-Loop Comparators

 Input-offset voltage
 systematic offset can nearly be eliminated with proper design (though still affected
by process variations)
 random offsets still remain and are unpredictable
 Sol : Autozeroing Techniques
 single transition of the comparator in a noisy environment
 introduction of hysteresis using a bistable circuit.
 In high-resolution A/D converters, large input-offset voltages cannot be tolerated.
 offset voltages can be measured, stored on capacitors, and summed with the input
so as to cancel the offset
 in MOS because of the nearly infinite input resistance of MOS transistors.
 allows long-term storage of voltages on the transistor’s gate

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 Autozeroing Technique
 In order for this circuit to work
properly, it is necessary that the
comparator be stable in the unity-
gain configuration

(a) Simple model of a comparator including offset.

(b) Comparator in unity-gain configuration storing the offset on autozero capacitor CAZ during
the first half of the autozero cycle.
(c) Comparator in open-loop configuration with offset cancellation achieved at the noninverting
input during the second half of the autozero cycle.

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Autozeroing Techniques
(a) Differential circuit implementation of an  The switch
autozeroed comparator.
(b) Comparator during ɸ1 phase. implementations of the
(c) Comparator during ɸ2 phase autozeroed comparator
can be single-channel
MOSFETs or
complementary MOSFETs
 nonoverlapping clocks
 Charge injection resulting
from clock feedthrough

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 Other Autozeroing Techniques

Noninverting autozeroed comparator.

Inverting autozeroed comparator.

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Analysis to show the effect: greater the pole and the gain
faster the response
If the comparator used in Fig. has a dominant pole at 104 rad/s and a gain of 103 .
how long does it take CAZ to charge to 99% of its final value, VOS? What is the final

value that the capacitor, CAZ, will charge to if left in the configuration of
Fig. (b) for a long time

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In class exercise

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In class exercise

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In class exercise

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Cancelling the offset voltage of a comparator

1. φ1, known as the reset phase , to be charged to zero volts

2. The comparison phase, open circuit
3. During φ2 If Vin >0, Output Large –ve

4. If Vin <0, Output Large +ve

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Input-Offset Voltage Errors

not only does this

technique eliminate input-
offset voltage errors, but it
also minimizes errors
input-offset voltage caused by low-frequency
1/f noise

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Speeding up the comparison Time

 Disconnect the compensation capacitor during the comparison phase

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