Unit2 - COA Shikha Singh

Noida Institute of Engineering and Technology, GR.
Noida
(An Autonomous Institute)
School of Computer Science & Engineering in Emerging
Technologies
ALU Unit
Unit: 2
Computer Organization &

Khushboo
Architecture (ACSE 0305)
Assistant Professor
B Tech (CSDS)- 3rd Sem NIET, Greater Noida
Shikha Singh Computer Organisation & Architecture Unit 2

1
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Introduction of Faculty member
Name : Ms. Khushboo

Qualification:
•B.Tech(ECE)
•M.Tech(ECE), Specialization: Communication
•Research Area: Antenna and Internet of Things
Professional details:
•Name of Institute with Code: NIET(133)
•Designation: Assistant Professor
•Department: ECE
Experience (Year): 3 years

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Evaluation scheme

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Subject Syllabus
Course Contents / Syllabus
UNIT-I Introduction 8 Hours
Computer Organization and Architecture, Functional units of digital system and their
interconnections, buses, bus architecture, types of buses and bus arbitration and it’s types.
Register, bus and memory transfer. Process or organization, general registers organization,
stack organization and addressing modes.
UNIT-II ALU Unit 8 Hours
Arithmetic and logic unit: Lookahead carries adders. Multiplication: Signed operand
multiplication, Booth’s algorithm and array multiplier. Division and logic operations.
Floating point arithmetic operation, Arithmetic & logic unit design. IEEE Standard for
Floating Point Numbers.
UNIT-III Control Unit 8 hours
Control Unit: Instruction types, formats, instruction cycles and sub cycles (fetch and
execute etc.), microoperations,
execution of a complete instruction. Program Control, Reduced Instruction Set Computer,
Complex Instruction Set Computer, Pipelining. Hardwire and microprogrammed control,
Concept of horizontal and vertical microprogramming, Flynn's classification.
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Subject Syllabus
Course Contents / Syllabus
UNIT-IV Memory Unit 8 hours

Memory: Basic concept and hierarchy, semiconductor RAM memories, 2D & 2 1/2D
memory organization. ROM memories. Cache memories: concept and design issues &
performance, address mapping and replacement Auxiliary memories: magnetic disk,
magnetic tape and optical disks Virtual memory: concept implementation, Memory
Latency, Memory Bandwidth, Memory Seek Time.
UNIT-V Input/Output 8 hours
Peripheral devices, I/O interface, I/O ports, Interrupts: interrupt hardware, types of
interrupts and exceptions. Modes of Data Transfer: Programmed I/O, interrupt
initiated I/O and Direct Memory Access. ,I/O channels and processors. Serial
Communication: Synchronous & asynchronous communication.

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Branch wise Applications
Computer Science:
Understanding of Computer Organization and Architecture is required

for:
• Performance analysis of practical software
• Parallel Software and its execution
• High performance databases
• Modern Compilers and Code optimization
• High performance game programming
Other applications
• Bio-informatics, Data science using python, Web programming
For high performance computing, we require COA background.

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Course Objective
• Discuss the basic concepts and structure of computers.

• Understand concepts of register transfer logic and arithmetic
operations.
• Explain different types of addressing modes and memory
organization.
• Understand the concepts of memory system and Learn the different
types of memories to store data.
• Explain the various types of interrupts and modes of data transfer.

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Course Outcomes
Course outcomes : After completion of this course students will be able to
CO 1 Understand the basic structure and operation of a digital K1, K2
computer system
CO 2 Analyze the design of arithmetic & logic unit and understand the K1, K4
fixed point and floating-point arithmetic operations.

CO 3 Implement control unit techniques and the concept of Pipelining K3
CO 4 Understand the hierarchical memory system, cache memories K2
and virtual memory.

CO 5 Understand different ways of communicating with I/O devices K2
and standard I/O interfaces.

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Program Outcomes
• Program Outcomes are narrow statements that describe what the
students are expected to know and would be able to do upon the
graduation.
• These relate to the skills, knowledge, and behavior that students acquire
through the programmed.
1. Engineering knowledge
2. Problem analysis 9. Individual and team work
3. Design/development of solutions 10. Communication
4. Conduct investigations of complex 11. Project management and
problems finance
5. Modern tool usage 12. Life-long learning
6. The engineer and society
7. Environment and sustainability
8. Ethics

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CO-PO Mapping
COMPUTER ORGANIZATION AND ARCHITECTURE

(ACSE 0305)
PO PO PO
CO PO1 PO2 PO3 PO4 PO5 PO6 PO7 PO8 PO9 10 11 12
CO1 3 2 1 1 1 1 1 - 1 1 1 2
CO2 2 2 2 2 1 1 - 1 1 1 1 2
CO3 3 2 2 1 2 2 1 1 2 2 1 2
CO4 3 2 2 2 2 1 1 - 1 1 1 2
CO5 2 2 2 1 2 - 1 - 1 2 2 2
Average 2.6 2 1.8 1.4 1.6 1 0.8 0.4 1.2 1.4 1.2 2

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Program Educational Objectives
PEO1: Solve real-time complex problems and adapt to technological

changes with the ability of lifelong learning.
PEO2: Work as data scientists, entrepreneurs, and bureaucrats for
the goodwill of the society and pursue higher education.
PEO3: Exhibit professional ethics and moral values with good
leadership qualities and effective interpersonal skills.

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Result Analysis
Department Result Individual Result
Computer 100%
Organization
and Architecture
Renewable 98.57%
Energy
Resources
Universal 90.74%
Human Values
Introduction to 95.61%
Microprocessor

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End Semester Question Paper Template
Question Paper
Template -100 Marks

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Prerequisite and Recap
• Basic knowledge of Digital Logic Design

• ALU Unit
• Control Unit
• Memory unit

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Brief Introduction about Subject
The Computer Organization and architecture is one of the most

important and comprehensive subject that includes many foundational
concepts and knowledge used in design of a computer system. This
subject provides in-depth knowledge of internal working, structuring,
and implementation of a computer system.
The COA important topics include all the fundamental concepts such
as computer system functional units , processor micro architecture ,
program instructions, instruction formats , addressing modes ,
instruction pipelining, memory organization , instruction cycle,
interrupts and other important related topics.
Video link: https://www.youtube.com/watch?v=q6oiRtKTpX4

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Unit Content
Arithmetic and logic unit
•Look ahead carries adders

•Multiplication: Signed operand multiplication
•Booths algorithm and array multiplier
•Division and logic operations
•Floating point arithmetic operation
•Arithmetic & logic unit design
•IEEE Standard for Floating Point Numbers

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Unit Objective
• Design of arithmetic and logic unit and float point arithmetic.

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Introduction to Topic 1
Name of Topic Objective of Topic Mapping with CO

Students will be able
Look ahead carries to understand about CO 2
adders different adders in
ALU unit

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Introduction
• An arithmetic logic unit (ALU) is a digital circuit used
perform arithmetic and logic operations.
• It represents the fundamental building block of the central
processing unit (CPU) of a computer. Modern CPUs contain very
powerful and complex ALUs.
• In addition to ALUs, modern CPUs contain a control unit (CU)
• The inputs to an ALU are the data to be operated on, called operands,
and a code indicating the operation to be performed.
• A symbolic representation of an ALU and its input and output signals

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Half Adder
• Half adder is a combinational arithmetic circuit that adds two

numbers and produces a sum bit(S) and carry bit (C) as the output.
• If X and Y are the input bits ,then sum bit(S) is the X-OR of X and Y
and the carry bit (C) will be the AND of X and Y.
Shikha Singh Computer

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Half Adder
• The block diagram of half adder is:
• Truth Table for half adder is:

Functional Units of Computer System
Boolean equations for sum and carry are -

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Half Adder
• Logic diagram of half adder:

Full Adder
• Full adder is developed to overcome the drawbacks of Half Adder

circuit.
• It can add two one-bit numbers A and B, sum S and carry C.
• The full adder is a three input and two output combinational circuit
Block Diagram:

Full Adder
Truth Table :

Full Adder
Sum = A XOR B XOR Cin

Carry = AB + BCin + Cin A
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Full Adder
• Full Adder using two half adders :
Sum = = A XOR B XOR Cin
Carry = AB + Cin (A xor B)
Circuit diagram of full adder

Parallel Adder
• A Parallel Adder is a digital circuit capable of finding the
arithmetic sum of two binary numbers that is greater than one bit in
length by operating on corresponding pairs of bits in parallel.
• It consists of full adders connected in a chain where the output carry
from each full adder is connected to the carry input of the next higher
order full adder in the chain.
• A n bit parallel adder requires n full adders to perform the operation.

Parallel Adder
Logic Diagram of Parallel Adder :
Inputs:
A1 A2 A3 A4……A (n-1) An for A
B1 B2 B3 B4…….B (n-1) Bn for B
Parallel Adder
Working of parallel Adder –
•As shown in the figure, firstly the full adder FA1 adds A1 and B1 along
with the carry C1 to generate the sum S1 (the first bit of the output
sum) and the carry C2 which is connected to the next adder in chain.
•Next, the full adder FA2 uses this carry bit C2 to add with the input
bits A2 and B2 to generate the sum S2(the second bit of the output
sum) and the carry C3 which is again further connected to the next
adder in chain and so on.

Parallel Adder
• The process continues till the last full adder Fan uses the carry bit
Cn to add with its input An and Bn to generate the last bit of the
output along last carry bit Cout.

Parallel Adder
• The speed at which the number of bits added in the parallel adder
depends on the carry propagation time.
• However, signals must be propagated through the gates at a given
enough time to produce the correct or desired output.

Parallel Adder
• The following are the methods to get the high speed in the parallel
adder to produce the binary addition.
– By employing faster gates with reduced delays, we can reduce the
propagation delay.
– But there will be a capability limit for every physical logic gate.
– Another way is to increase the circuit complexity in order to
reduce the carry delay time.
– There are several methods available to speeding up the parallel
adder, one commonly used method employs the principle of look
ahead-carry addition by eliminating inter stage carry logic.

Carry-Look-ahead Adder
• A carry Look-ahead adder is a fast parallel adder as it reduces the
propagation delay by more complex hardware, hence it is costlier.
• This method makes use of logic gates so as to look at the lower
order bits of the augend and addend to see whether a higher order
carry is to be generated or not.

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• Consider the full adder circuit shown above with corresponding

truth table.
• If we define two variables as carry generate Gi and carry propagate
Pi then,
P i = Ai ⊕ B i
Gi = Ai Bi
• The sum output and carry output can be expressed as
Si = Pi ⊕ Ci
C i+1 = Gi + Pi Ci
• Where Gi is a carry generate which produces the carry when both
Ai, Bi are one regardless of the input carry. Pi is a carry propagate
and it is associate with the propagation of carry from Ci to Ci+1
• The carry output Boolean function of each stage in a 4 stage carry

Look-ahead adder can be expressed as
C1 = G0 + P0 C0
C2= G1 + P1 C1
= G1 + P1 G0 + P1 P0 C0
C3 = G2 + P2 C2
= G2 + P2 G1+ P2 P1 G0 + P2 P1 P0 C0

• From the above Boolean equations we can observe that C 3 does not
have to wait for C2 and C1 to propagate but actually C3 is
propagated at the same time as C2 and C1.
• Since the Boolean expression for each carry output is the sum of
products so these can be implemented with one level of AND gates
followed by an OR gate.

• The implementation of three Boolean functions for each carry output
(C1, C2 and C3) for a carry Look-ahead carry generator shown in below
figure.


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Daily Quiz
1. For a 4-bit parallel adder, if the carry-in is connected to a logical HIGH, the
result is ___________
a) The same as if the carry-in is tied LOW since the least significant carry-in
is ignored
b) That carry-out will always be HIGH
c) A one will be added to the final result
d) The carry-out is ignored
2. Fast-look-ahead carry circuits found in most 4-bit full-adder circuits which
___________
a) Determine sign and magnitude
b) Reduce propagation delay
c) Add a 1 to complemented inputs
d) Increase ripple delay
3. What distinguishes the look-ahead-carry adder?
a) It is slower than the ripple-carry adder
b) It is easier to implement logically than a full adder
c) It is faster than a ripple-carry adder
d) It requires advance knowledge of the final answer
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Daily Quiz with Answers
1. For a 4-bit parallel adder, if the carry-in is connected to a logical HIGH, the
result is ___________
a) The same as if the carry-in is tied LOW since the least significant carry-in
is ignored
b) That carry-out will always be HIGH
c) A one will be added to the final result
d) The carry-out is ignored
2. Fast-look-ahead carry circuits found in most 4-bit full-adder circuits which
___________
a) Determine sign and magnitude
b) Reduce propagation delay
c) Add a 1 to complemented inputs
d) Increase ripple delay
3. What distinguishes the look-ahead-carry adder?
a) It is slower than the ripple-carry adder
b) It is easier to implement logically than a full adder
c) It is faster than a ripple-carry adder
d) It requires advance knowledge of the final answer
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Daily Quiz
4. Carry lookahead logic uses the concepts of ___________
a) Inverting the inputs
b) Complementing the outputs
c) Generating and propagating carries
d) Ripple factor
5. Total number of inputs in a half adder is __________
a) 2
b) 3
c) 4
d) 1
6. In which operation carry is obtained?
a) Subtraction
b) Addition
c) Multiplication
d) Both addition and subtraction
7. If A and B are the inputs of a half adder, the sum is given by __________
a) A AND B
b) A OR B
c) A XOR B
d) A EX-NOR B
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4. Carry lookahead logic uses the concepts of ___________
a) Inverting the inputs
b) Complementing the outputs
c) Generating and propagating carries
d) Ripple factor
5. Total number of inputs in a half adder is __________
a) 2
b) 3
c) 4
d) 1
6. In which operation carry is obtained?
a) Subtraction
b) Addition
c) Multiplication
d) Both addition and subtraction
7. If A and B are the inputs of a half adder, the sum is given by __________
a) A AND B
b) A OR B
c) A XOR B
d) A EX-NOR B
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Multiplication: Signed Students will be able
operand to understand about CO 2
multiplication signed multiplication

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Multiplication: Signed operand
multiplication
• Multiplication of two fixed point binary number in signed
magnitude representation is done with process of successive shift
and add operation.
• The numbers copied down in successive lines are shifted one
position to the left from the previous number.
• Finally numbers are added and their sum form the product.

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Multiplication for Signed magnitude data
Hardware for multiply operation

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Example

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Daily Quiz
1. We make use of ______ circuits to implement multiplication.
a) Flip flops
b) Combinatorial
c) Fast adders
d) None of the mentioned
2. The product of 1101 & 1011 is ______

a) 10001111
b) 10101010
c) 11110000
d) 11001100
3. The multiplier is stored in ______

a) PC Register
b) Shift register
c) Cache
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1. We make use of ______ circuits to implement multiplication.
a) Flip flops
b) Combinatorial
c) Fast adders
2. The product of 1101 & 1011 is ______

a) 10001111
b) 10101010
c) 11110000
d) 11001100
3. The multiplier is stored in ______

a) PC Register
b) Shift register
c) Cache
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Daily Quiz
4. The ______ is used to coordinate the operation of the multiplier.
a) Controller
b) Coordinator
c) Control sequencer
5. The product of -13 & 11 is ______________

a) 1100110011
b) 1101110001
c) 1010101010
d) 1111111000

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4. The ______ is used to coordinate the operation of the multiplier.
a) Controller
b) Coordinator
c) Control sequencer
5. The product of -13 & 11 is ______________

a) 1100110011
b) 1101110001
c) 1010101010
d) 1111111000

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Booths algorithm and to understand about CO 2
array multiplier booths algorithm and
array multiplier

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Booth Multiplication Algorithm
Booth Multiplication Method

Booth algorithm gives a procedure for multiplying binary integers in
signed-2's complement representation.
Hardware for booth algorithm

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Flow diagram
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Example

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Array Multiplier
• An array multiplier is a digital combinational circuit used for multiplying
two binary numbers by employing an array of full adders and half
adders.
• This array is used for the nearly simultaneous addition of the various
product terms involved.
• The multiplication of two 2-bit numbers as shown in figure. The
multiplicand bits are b1 and b0, the multiplier bits are a1 and a0, and
the product is -

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Array Multiplier
• 4 bit by 3 bit Array multiplier B=b3 b2 b1 b0 and A= a2 a1 a0.

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Array Multiplier
For k multiplicands & j multipliers bits , we needs

1. j x k AND gates
2.(j-1 )x k bit adders produce
3. A product of j + k bits
For 4 bit by 3 bit Array multiplier-

k-= 4, j= 3
1.12 AND gates
2.8 bit adders
3.A product of 7 bits

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Daily Quiz
1. Which of the following is used for binary multiplication?
a) Restoring Multiplication
b) Booth’s Algorithm
c) Pascal’s Rule
d) Digit-by-digit multiplication
2. Booth’s Algorithm is applied on _____________

a) decimal numbers
b) binary numbers
c) hexadecimal numbers
d) octal Numbers
3. What will be the value obtained after multiplication of (-2) * (-3) using
Booth’s Algorithm?
a) 6
b) -6
c) -2
d) -3 Shikha Singh Computer Organisation & Architecture Unit 2
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a) Restoring Multiplication
b) Booth’s Algorithm
c) Pascal’s Rule
d) Digit-by-digit multiplication

a) decimal numbers
b) binary numbers
d) octal Numbers
3. What will be the value obtained after multiplication of (-2) * (-3) using
Booth’s Algorithm?
a) 6
b) -6
c) -2
d) -3 Shikha Singh Computer Organisation & Architecture Unit 2
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Daily Quiz
4. What does the data transfer instruction STA stand for?
a) Store Accumulator
b) Send Accumulator
c) Send Action
d) Store Action

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4. What does the data transfer instruction STA stand for?
a) Store Accumulator
b) Send Accumulator
c) Send Action
d) Store Action

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Division algorithm to understand about CO 2
and floating point division algorithm
arithmetic operations and floating point
addition, subtraction,
multiplication and
division

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Division Algorithms
Division
• Division of two fixed-point binary numbers in signed magnitude
representation is performed with paper and pencil by a process
of successive compare, shift and subtract operations.
• Binary division is much simpler than decimal division because
here the quotient digits are either 0 or 1 and there is no need to
estimate how many times the dividend or partial remainder fits
into the divisor. .

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Division Algorithms
Division

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Division Algorithms

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Division Algorithms

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Floating point arithmetic operation
• A floating point number in computer registers consists of two parts:

a mantissa m and an exponent e. The two parts represent a number
obtained from multiplying m times a radix r raised to the value of e;
thus
m x re
• Example .53725 x 103
• Normalization-
A floating-point number is normalized if the most significant digit of
the mantissa is nonzero. In this way the mantissa contains the
maximum possible number of significant digits.

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Register Configuration
Registers for floating – point arithmetic operations

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Floating Point Addition & Subtraction
• During addition or subtraction, the two floating-point operands are in
AC and BR. The sum or difference is formed in the AC. The algorithm
can be divided into four consecutive parts:
1. Check for zeros.

2. Align the mantissas.
3. Add or subtract the mantissas.
4. Normalize the result.
• A floating-point number that is zero cannot be normalized. If this

number is used during the computation, the result may also be zero.
• Instead of checking for zeros during the normalization process we check
for zeros at the beginning and terminate the process if necessary.

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Floating Point Multiplication
• The multiplication of two floating-point numbers requires that we

multiply the mantissas and add the exponents.
• The multiplication of the mantissas is performed in the same way as
in fixed-point to provide a double-precision.
The multiplication algorithm can be subdivided into four parts:

1. Check for zeros.
2. Add the exponents.
3. Multiply the mantissas.
4. Normalize the product.

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Flow diagram

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Floating Point Division
• Floating-point division requires that the exponents be subtracted

and the mantissas divided.
• The mantissa division is done as in fixed-point except that the
dividend has a single-precision mantissa that is placed in the AC.
• The division algorithm can be subdivided into five parts:

1. Check for zeros
2. Initialize registers and evaluate the sign
3. Align the dividend
4. Subtract the exponents
5. Divide the mantissas

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Floating Point Division
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Arithmetic & logic unit design
• Inside a computer, there is an Arithmetic Logic Unit (ALU), which is
capable of performing logical operations (e.g. AND, OR, Ex-OR, Invert
etc.) and arithmetic operations (e.g. Addition, Subtraction etc.).
• The control unit supplies the data required by the ALU from memory,
or from input devices, and directs the ALU to perform a specific
operation based on the instruction fetched from the memory. ALU is
the “calculator” portion of the computer.
Different operation as carried out by

ALU can be categorized as follows
•Logical operations
•Bit-Shifting Operations
•Arithmetic operations
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1-bit ALU Design
• Construct a simple ALU that performs a arithmetic operation (1 bit
addition)and does 3 logical operations namely AND, NOR and XOR as
shown below.
• The multiplexer selects only one operation at a time. The operation

selected depends on the selection lines of the multiplexer as shown in
the truth table.

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1-bit ALU Design
Inputs Outputs
M1 M0 Operation
0 0 SUM
1 0 AND
0 1 OR
1 1 XOR

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Daily Quiz
1. If the decimal point is placed to the right of the first significant digit,
then the number is called ________
a) Orthogonal
b) Normalized
c) Determinate
2. The IEEE standard followed by almost all the computers for floating
point arithmetic _____
a) IEEE 260
b) IEEE 488
c) IEEE 754
d) IEEE 610
3. Which of the following is often called the double precision format?
a) 64-bit
b) 8-bit
c) 32-bit
d) 128-bit
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1. If the decimal point is placed to the right of the first significant digit,
then the number is called ________
a) Orthogonal
b) Normalized
c) Determinate
point arithmetic _____
a) IEEE 260
b) IEEE 488
c) IEEE 754
d) IEEE 610
a) 64-bit
b) 8-bit
c) 32-bit
d) 128-bit
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IEEE Standard for to understand about CO 2
Floating Point different IEEE
Numbers standard for floating
point numbers

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IEEE Standard for Floating Point Numbers
• The IEEE Standard for Floating-Point Arithmetic (IEEE 754) is a

technical standard for floating-point computation which was
established in 1985 by the Institute of Electrical and Electronics
Engineers (IEEE).
• IEEE 754 has 3 basic components:
1. The Sign of Mantissa –
0 represents a positive number while 1 represents a negative
number.
2. The Biased exponent –
A bias is added to the actual exponent in order to get the stored
exponent.
3. The Normalized Mantissa –
A normalized mantissa is one with only one 1 to the left of the
decimal.

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IEEE 754 numbers are divided into two based on the above three
components: single precision and double precision.

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BIASED NORMALISED
TYPES SIGN BIAS
EXPONENT MANTISA
Single
1(31st bit) 8(30-23) 23(22-0) 127
precision
Double
1(63rd bit) 11(62-52) 52(51-0) 1023
precision

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Daily Quiz
1. The number of sign bits in a 32-bit IEEE format _________
a) 1 b) 11
c) 9 d) 23
2. In 32 bit representation the scale factor as a range of -
a) -256 to 255 b) 0 to 255
c) -128 to 127 d) None
3. The ‘heart’ of the processor which performs many different operations
_____.
a) Arithmetic and logic unit
b) Motherboard
c) Control Unit
d) Memory
4. IEEE stands for ___________
a) Instantaneous Electrical Engineering
b) Institute of Emerging Electrical Engineers
c) Institute of Emerging Electronic Engineers
d) Institute of Electrical and electronics engineers
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1. The number of sign bits in a 32-bit IEEE format _________
a) 1 b) 11
c) 9 d) 23
2. In 32 bit representation the scale factor as a range of -
a) -256 to 255 b) 0 to 255
c) -128 to 127 d) None
3. The ‘heart’ of the processor which performs many different operations
_____.
b) Motherboard
c) Control Unit
d) Memory
4. IEEE stands for ___________
a) Instantaneous Electrical Engineering
b) Institute of Emerging Electrical Engineers
c) Institute of Emerging Electronic Engineers
d) Institute of Electrical and electronics engineers
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Weekly Assignment
1. Explain in detail the principal of carry look ahead adder and design 4 bit
CLA adder.
2. Explain the addition and subtraction of floating-point numbers with help
of flowchart.
3. What is restoring method in Fixed point Division algorithm?
4. Show the systematic multiplication process of (20) X (-19) using Booths
Algorithm.
5. Explain IEEE standard for floating point representation.

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Weekly Assignment

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Video Links
You tube/other Video Links

• https://www.youtube.com/watch?v=vcvgvqnH7GA
• https://www.youtube.com/watch?v=U62iP8RkZIk
• https://www.youtube.com/watch?v=6ToR6vuRb3M
• https://www.youtube.com/watch?v=9nkCLdhLDZk
• https://www.youtube.com/watch?v=0HiGruw9VcQ

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MCQ
1. The ‘heart’ of the processor which performs many different operations.
b) b) Motherboard
c) c) Control Unit
d) d) Memory
2. Which of the following is not a bitwise operator?

a) | b) ^ c) . d) <<
3. The sign magnitude representation of -1 is __________
a) 0001 b) 1110 c) 1000 d) 1001
4. The ALU gives the output of the operations and the output is stored in
the ________
a) Memory Devices b) Registers c) Flags d) Output Unit

05/17/24 97
MCQ
point arithmetic
a) IEEE 260 b) IEEE 488 c) IEEE 754 d) IEEE 610
a) 64-bit b) 8-bit c) 32-bit d) 128-bit
a) Restoring Multiplication b) Booth’s Algorithm
c) Pascal’s Rule d) Digit-by-digit multiplication
a) decimal numbers
b) binary numbers
d) octal Numbers

05/17/24 98
Glossary Questions
The multiplication of two floating-point numbers requires that we
multiply the mantissas and add the exponents. No comparison of
exponents or alignment of mantissas is necessary. The multiplication of
the mantissas is performed in the same way as in fixed-point to provide
a double-precision product. The double precision answer is used in fixed-
point numbers to increase the accuracy of the product. In floating-point,
the range of a single-precision mantissa combined with the exponent is
usually accurate enough so that only single-precision numbers are
maintained. Thus the half most significant bits of the mantissa product
and the exponent will be taken together to form a single-precision
floating point product.

05/17/24 99
Glossary Questions
1. What are the steps of multiplication algorithm?
2. Explain mantissa and exponent with help of an example.
3. Draw the flowchart of multiplication process of floating point
numbers.

05/17/24 100
Old Question Papers - Sessional
Sessional 1
Sessional 2
Sessional 3
Shikha Singh Computer Organisation & Architecture Unit 2 101

05/17/24
Old Question Papers
2017-18
2018-19
2019-20

05/17/24
Expected Questions

05/17/24
Recap
• A carry Look-ahead adder is a fast parallel adder as it reduces the
propagation delay by more complex hardware, hence it is costlier.
• This method makes use of logic gates so as to look at the lower order
bits of the augend and addend to see whether a higher order carry is
to be generated or not.
• Multiplication of two fixed point binary number in signed magnitude
representation is done with process of successive shift and add
operation.
• The numbers copied down in successive lines are shifted one position
to the left from the previous number.
• Finally numbers are added and their sum form the product.

05/17/24
Recap
• An array multiplier is a digital combinational circuit used for
multiplying two binary numbers by employing an array of full adders
and half adders.
• This array is used for the nearly simultaneous addition of the various
product terms involved
• Division of two fixed-point binary numbers in signed magnitude
representation is performed with paper and pencil by a process of
successive compare, shift and subtract operations.
• The IEEE Standard for Floating-Point Arithmetic (IEEE 754) is a
technical standard for floating-point computation which was
established in 1985 by the Institute of Electrical and Electronics
Engineers (IEEE).

05/17/24
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05/17/24

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Noida Institute of Engineering and Technology, GR.

Computer Organization &

Shikha Singh Computer Organisation & Architecture Unit 2

Name : Ms. Khushboo

Experience (Year): 3 years

Shikha Singh Computer Organisation & Architecture Unit 2

Shikha Singh Computer Organisation & Architecture Unit 2

UNIT-IV Memory Unit 8 hours

Shikha Singh Computer Organisation & Architecture Unit 2

Understanding of Computer Organization and Architecture is required

• Bio-informatics, Data science using python, Web programming

For high performance computing, we require COA background.

• Discuss the basic concepts and structure of computers.

Shikha Singh Computer Organisation & Architecture Unit 2

Course outcomes : After completion of this course students will be able to

CO 1 Understand the basic structure and operation of a digital K1, K2

fixed point and floating-point arithmetic operations.

CO 4 Understand the hierarchical memory system, cache memories K2

and virtual memory.

and standard I/O interfaces.

Shikha Singh Computer Organisation & Architecture Unit 2

Shikha Singh Computer Organisation & Architecture Unit 2

COMPUTER ORGANIZATION AND ARCHITECTURE

Shikha Singh Computer Organisation & Architecture Unit 2

PEO1: Solve real-time complex problems and adapt to technological

Shikha Singh Computer Organisation & Architecture Unit 2

Department Result Individual Result

Shikha Singh Computer Organisation & Architecture Unit 2

Shikha Singh Computer Organisation & Architecture Unit 2

• Basic knowledge of Digital Logic Design

Shikha Singh Computer Organisation & Architecture Unit 2

The Computer Organization and architecture is one of the most

Video link: https://www.youtube.com/watch?v=q6oiRtKTpX4

Shikha Singh Computer Organisation & Architecture Unit 2

•Look ahead carries adders

Shikha Singh Computer Organisation & Architecture Unit 2

• Design of arithmetic and logic unit and float point arithmetic.

Shikha Singh Computer Organisation & Architecture Unit 2

Name of Topic Objective of Topic Mapping with CO

Shikha Singh Computer Organisation & Architecture Unit 2

Shikha Singh Computer Organisation & Architecture Unit 2

• Half adder is a combinational arithmetic circuit that adds two

Shikha Singh Computer

• The block diagram of half adder is:

• Truth Table for half adder is:

Shikha Singh Computer

Shikha Singh Computer Organisation & Architecture Unit 2

• Logic diagram of half adder:

Shikha Singh Computer

• Full adder is developed to overcome the drawbacks of Half Adder

Shikha Singh Computer

Shikha Singh Computer

Sum = A XOR B XOR Cin

05/17/24 Shikha Singh Computer Organisation & Architecture Unit 2 26

Circuit diagram of full adder

05/17/24 Shikha Singh Computer Organisation & Architecture Unit 2 27

05/17/24 Shikha Singh Computer Organisation & Architecture Unit 2 28

Logic Diagram of Parallel Adder :

• A floating point number in computer registers consists of two parts: