MPI TUT-12

8253 and 8259

16/04/2024
17/04/2024
18/04/2024
22/04/2024
 Question 1
Write a program to initialize 8253/8254 in mode 1 to read and load lower 8-
bits only assuming that 8253/8254 is interfaced in memory mapped IO.
Consider that the address of counter 0 is 3FFE8H.

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 Solution 1
Write a program to initialize 8253/8254 in mode 1 to read and load lower 8-
bits only assuming that 8253/8254 is interfaced in memory mapped IO.
Consider that the address of counter 0 is 3FFE8H and DS = 3000H.

Control Word for 8253 with counter 0 in mode 1: 12H

Address for counter 0, counter 1, counter 2 and CWR are

Binary counter 0 is selected. Load the lower 8-bits only. It latches the count and
then stores it in register such that it can be read. Let 05H is the lower 8-bit count.

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 Solution 1
Program

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 Question 2
Design a pulse train generator for a pulse train of frequency
1 kHz and duty cycle of 50% using 8253/8254. Assume the
CWR and Counter 0 addresses are marked as CWR_add
and Counter_0, respectively.

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 Solution 2
The operational mode should be mode 3.

Duty cycle 50% means that out of 4 parts of the wave, for 2 parts, the output will
be high, and for the remaining two parts, the output will be low.

We want 1 kHz output frequency and 4 count pulses to get 50% duty cycle so 4
kHz input frequency will be selected.

The control word to initialize counter 0 will be 17H.

ALP

MOV AL, 17H

OUT CWR_add, AL
MOV AL,04H
OUT Counter_0, AL

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 Question 3
Write the initialization required for 8259 to meet the following:

a. Interrupt vector type 65H.

b. Call address interval will be 4 bytes
c. Nested mode.
d. IC4 is required, and the interrupts are edge-triggered.

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 Solution 3

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 Question 4

Using the following code what should be the value of

‘Count’ to make a delay of 100 ms using an 8086 system
operating at 10 MHz? For MOV, DEC, NOP, and JNZ
instructions, the no. of required clock cycles are 4, 2, 3,
and 16, respectively.

MOV CX, Count

L1: DEC CX
NOP
JNZ L1

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 Solution 4
 The instruction MOV CX,Count is not in the
delay loop generation.
 Total no. of clock cycles for the complete
execution of the code = (4+2+3+16) = 25
 Among these 21 clock cycles will be repeated.
 Let the required value of Count is = N
 1 Clock pulse = 1/(10 MHz) = 0.1 μs.
 Analytical relation

Solving for N = 47619 (nearest integer) = BA03H

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