5.

5 Cache Organization
 Cache Memory
 Cache Operation
• Pentium processors operate at very high clock speeds to provide very good performance. But reading and writing
memory off-chip is much slower than accessing CPU registers on-chip.
• The cache controllers maintains a directory to keep a track of the information it has copied into the cache memory.
• If the copy is present, the cache controller reads the information from the cache, sends it to the processors data
bus and asserts the processors ready signal. This is called as READ HIT.
• If the cache controller determines that it does not have a copy of the requested information in this cache, the
information is now read form main memory(DRAM). This is known as READ MISS and causes wait states due to
slow access time.
 Principals of Locality
• It is based on the principle of locality of reference. There are two ways with which data or instruction is fetched
from main memory and get stored in cache memory. These two ways are the following:
• Temporal Locality – Temporal locality means current data or instruction that is being fetched may be needed soon.
So we should store that data or instruction in the cache memory so that we can avoid again searching in main
memory for the same data.
• Spatial Locality – Spatial locality means instruction or data near to the current memory location that is being
fetched, may be needed soon in the near future. This is slightly different from the temporal locality. Here we are
talking about nearly located memory locations while in temporal locality we were talking about the actual memory
location that was being fetched.
Cache Architecture
 Look Through Cache Design

• In the look-through case, the consistency is handled transparently by the cache, without the application being involved.
• The performance of systems incorporating Look Through Cache is typically higher than that of systems incorporating Look
Aside Cache.
• Data from main memory (DRAM) is not transferred to the processor using system bus hence system bus is free for other
bus masters to access the main memory.
• To expansion devices, a look-through cache controller is like a system processor.
• It reduces the system and memory bus utilization, leaving them available for use by other bus master.
 Look Aside cache Design
• In the look-aside case, it is the responsibility of the application to maintain the consistency of the data in the cache and
insert the data back into cache.
• In this case the processor is directly connected to the system bus or memory bus.
• When the processor initiates a bus access, cache controller ae well as main memory detects the bus access address.
• The cache controller sites aside and monitors each processor memory request to determine if the cache contains the copy
of the requested information.
• Cache miss cycles complete faster in look aside cache as the bus cycle is already in progress to memory and hence no look
up penalty is incurred.
 Code Cache organization and Operation
• The code cache is 8kb size, organized as two-way set associative mapping configuration.
• The cache ways are referred to as way zero and way one.
• Each cache line is 32bytes wide and the bus connected from this cache to the pre-fetcher is also of 256bits.
• The cache directories are triple ported, to support split line access and snooping.
• The directory consist of 20bit tag field to identify the page in the memory.
• The code cache is designed to permit two simultaneous pre-fetch accesses: one to the upper half of one line
and another to the lower half of the next line.
• Each cache line holds four quadwords of information. Each quadword is associated with a parity bit for error
checking
Line Storage Algorithm
• The code cache considers the 4gb memory space to be divided pages of 4kb each such pages.
• Each page is divided into 128 lines, each of 32bytes.
• When the prefetcher issues a request for an instruction, the decode cache checks the directory to decide
whether it has a copy of that line from the required page memory.
• If the code do not have any copy, it issues a cache line-fill request to bus unit.
• The bus unit fetches the line from L2 cache or system memory and place it in the L1 cache and make directory
entry to track its presence
Inquire Cycles
• Inquire cycles are performed by the Pentium processor L1 cache when another bus master either reads or write
from main memory.
• This is done to ensure cache consistency between the contents of the internal data and code caches and system
memory.
• Inquire cycles are run in the following cases:
I. Memory write by Another Bus Master
II. Memory read by Another Bus Master
III. Internal Snooping
Split Line Access
• In a Pentium Processor, the instruction length varies from 1byte to 15byte and hence multi-byte instruction may
reside in two sequential lines stored in a code cache.
• A code cache miss result in a 32byte cache line-fill, if itsa cacheable address.
• When the prefetcher finds that the instruction is residing in two lines, prefecher must perform two sequential
cache access in order to get the instruction from the code cache but this would impactperformance.