IEG4020

Telecommunication Switching and Network Systems

Chapter 3
Fundamental Principles of Packet
Switch Design
 Output destinations
are random
… 3 1 1 1
… 4 2 4
4x4 2
… 1 1
Switch
3
… 4 2 4

Idle slots Arrival boundaries

(no active packets) may be unaligned

Fig. 3.1. Packet arrivals in a 4 x 4 packet switch

2
 To Switch
Info Input
Disassembler Delay Assembler

( Output VCI )
Header Header
( Input VCI ) Processor
Input Output Output
VCI: virtual-circuit VCI Address VCI
identifier
Memory 1 5 2
2 12 5
. . .
. . .

Fig. 3.2. Input packet processor

3
VCI of a virtual channel may change from link to link

2 2
3
2
2 2

o Simplify VCI assignment algorithm

o Reduce blocking due to shortage of valid VCI

4
 Packet Contention in Switches
Loss System :
o No input or internal buffers. Packets may need to
queue at outputs if group size is greater than 1
o Packets may be dropped internally or at outputs due
to contention. Loss probability can be made
arbitrarily small

Waiting System :
o Contention Resolution mechanism to select packets
to be switched
o Losing packets buffered at inputs or internally
o Output buffers needed if group size is greater than 1
o Throughput can be made arbitrarily close to 100%

5
 Solutions for Packet Contention
1) Speeding up packet switching

1 1
Speedup factor ≥ 3
1 2
 solve the
4x4
contention problem
1 3
in this example
2 4

Packets may be switched one by one to outputs if speedup

is N times, not viable for large N

Fig. 3.3. (a) Speeding up switch operation by N times

6
 Solutions for Packet Contention
2) Discard Packets

One of these 1 1
packets must
1 2
be dropped if
4x4
group size = 2 1 3

2 4

Fig. 3.3. (b) Dropping packets that cannot be switched

7
 Solutions for Packet Contention

3) Buffer Packets

Two of these 1 1
packets must
1 2
be buffered if
4x4
group size = 1 1 3

2 4

Fig. 3.3. (c) Queueing packets that cannot be switched

8
Fundamental properties of interconnection
networks
Interconnection Networks :
o Originally intended for multiprocessor computer
interconnect
o distributed, self-routing algorithms
o regular topological interconnection pattern

Rearrangeable nonblocking in circuit switching is the

same as internally nonblocking in packet switching

Speed is the practical difference !

9
 Banyan Networks
* Definition:
Not internally
nonblocking

* Unique path
from input
to output

* log2N stages

Networks (a) and (c) are isomorphic: one can be obtained

from the other by interchanging the shaded elements

Fig. 3.4. (a) shuffle-exchange (omega) network; (b) reverse shuffle-

exchange network; (c) banyan network; (d) baseline network
10
 Banyan Network
101 0 0 0 000
1 101 1 1 001

0 0 0 010
1 1 1 011

0 0
101 0 100
1 1 1 101
100
0 0 0 110
1 100 1 1 111
100

Destination addresses are in binary form. The log2N-bit address is

used as the routing bits for the packet: bit i is used in stage i

Fig. 3.5. Routing in the banyan network

11
 One packet must be dropped
External Conflict
000 0 0 000 0 000
000 000
1 1 1 001

0 0 0 010
100 1 1 1 011

0 0 0 100
1 1 1 101

0 0 0 110
100 1 1 1 111
Internal Conflict

Fig. 3.6. Internal and external conflicts when routing packets in a

banyan network
12
Loss probability in a Banyan Network :
Pm  Pr {  a packet at an input at stage m  1}
P0  0 , the offered load
Pm 2 Pm2
Pm1  1  (1  )  Pm 
2 4
Approximation:
dPm
Pm1  Pm 
dm
dPm Pm2
 
dm 4
4 0
Pm 
m 0  4
0  Pn n 0
Ploss  
0 n 0  4
13
 Pm Pm+1
m+1

Ploss = n / (n+4)

0.6
0.5
0.4 λ=1
0.3
0.2
0.1
n = log2N
1 2 3 4 5 6 7

Fig. 3.7. Loss probability of the Banyan network operating as a

loss system
14
Combinatoric Properties of Banyan Networks :
N
There are log 2 N switch elements
2
N N
log2 N
2 2
 N states
2

N
Can realize at most N input-output mappings without conflict
2

There are N N possible input-output mappings

Fraction of realizable mappings
N
N 2
1
N
 N  0 as N becomes large
N 2
N
15
Nonblocking Conditions for the Banyan Networks :
Banyan network is nonblocking if active inputs
x1, … xm, (xi, > xj, if j > 1) and their targeted outputs
y1, … ym satisfy :

1.) Distinct and monotonic outputs:

y1 < y2 < … < ym or ym > … > y2 > y1

2.) Concentrated inputs:

For any  such that x i    x j , input ω is active

16
 001 000
010 001
011 010
110 011
100
101
110
111
Fig. 3.8. (a) An example showing the banyan network is
nonblocking for sorted inputs

001 000
010 001
011 010
110 Sorting 011
Network 100
101
110
111
Fig. 3.8. (b) Nonblocking sort-banyan network
17
 Subnetwork 0
Subnetwork 00
0000 0000
0001 000,Φ 00,0 0,00 Φ, 000 0001
0010 0010
001,Φ 01,0 1,00 Φ, 001
0011 0011
0100 0100
0101 010,Φ 10,0 0,01 Φ, 010 0101
0110 0110
011,Φ 11,0 1,01 Φ, 011
0111 0111
1000 1000
1001 100,Φ 00,1 0,10 Φ, 100 1001
1010 1010
101,Φ 01,1 1,10 Φ, 101
1011 1011
1100 1100
1101 110,Φ 10,1 0,11 Φ, 110 1101
1110 1110
111,Φ 11,1 1,11 Φ, 111
1111 1111
Subnetwork 1

Fig. 3.9. (a) Labeling of nodes in the banyan network

18
 Banyan Network – Routing Algorithm

Input
Stage-1
Node
Stage-2
Node … Stage-n
Node Output

an …a1 (an-1 …a1 ,Φ)

b1
(an-2 …a1 ,b1) … (Φ, b …b
1 n-1 )
bn
(b1 …bn)

Fig. 3.9. (b) Sequence of nodes traversed by a packet from input an

… a1 to output bn … b1

19
 Banyan Network – Routing Algorithm
Stage-1 Stage-2 Stage-3
Input Node Node Node
0 …
(an-2 …a1 ,0)
0
1 …
an …a1 (an-1 …a1 ,Φ)
0 …
1 (an-2 …a1 ,1)
1 …
Without collision, a packet with input an …a1 and output
b1 …bn will be in node an-k …a1, b1 …bk-1 at stage k
Stage k :
an-k …a1,
b1 …bk-1

20
 Banyan Network – SNB Proof. ..
Proof : Two packets: x .
. .. y’
.
x’ .
1st packet : x = an…a1 y = b1…bn
2nd packet : x’ = an’…a1’ y’ = b1’…bn’ . .. y

collide in stage k
Then, an-k a1  an-k a1 and b1 bk  b1 bk
x  x  an a1  an a1

 an an-k 1 00  an an-k 1 00

 2nk an an-k 1  an an-k 1

 2n  k
y  y  b1 bn  b1 bn

 bk 1 bn  bk  bn (worst case: 111  000)

 2n  k  1  x   x
21
 Banyan Network – SNB Proof

But if conditions are satisfied :

1.) There are | x’ – x + 1 | active inputs x
.. .. y

between x’ and x x’ y’
They must have distinct outputs
2.) | y’ – y + 1 | >= number of distinct
outputs
= | x’ – x + 1 |

i.e. | y’ – y | >= | x’ – x |

22
Banyan Network with sorted input packets

111 000
110 001

010 010
101 011

001 100
011 101

100 110
000 111

Fig. 3.10. An example of unsorted packets having no conflict in the

banyan network

23
 011 000
110 001

010
011

100
101

001 110
010 111
(x1, y1) (x1 + Z mod N, y1)
.. nonblocking ..
(xm, ym) (xm + Z mod N, ym)

Fig. 3.11. Sorted packets remains unblocked after their inputs are
shifted (mod 8) by 6
24
Concentration :

RBN RBN
(shifted concentration)

Routing: bits are used starting from L.S.B to M.S.B.

25
 3 1
4 2
1 3
2 4
Fig. 3.12. (a) Sorting network switches correctly when all inputs are active and have
no
common outputs
4 1
4
1

Fig. 3.12. (b) Sorting network switches incorrectly when some inputs are inactive

1 1
2 1
3 2
1 3
Fig. 3.12. (c) Sorting network switches incorrectly when some inputs have common outputs
26
 Sorting Network
real packets
4 1
2 Sorting 2
1 Network 3
3 4 dummy packets
discarded at outputs
dummy packets with destinations
chosen to be nonconflicting

Fig 3.13. An example showing that dummy packets with nonconflicting

destinations may be introduced to make the sorting network switch
correctly when not all inputs are active, this requires knowledge of the
destinations of active inputs

27
 Comparator

ai min(ai, aj)
aj max(ai,
aj )
Fig. 3.14. (a) A comparator

ai min(ai, aj)
aj max(ai,
aj )
Fig. 3.14. (b) A compact way of representing a comparator

28
 Structure of Sorting Network
a1 b1
a2 b2
a3 b3
a4 b4
Fig. 3.15. (a) A 4x4 sorting network -- Compact representation

a1 b1
a2 b2
a3 b3
a4 b4
stage stage stage
1 2 3
Fig. 3.15. (b) A 4x4 sorting network -- Full representation

29
Sorting Network vs Comparison Network

Order-preserving property

Comparison
Networks

Sorting
Networks
0-1 principle

30
Order-preserving Property :
Suppose a comparison network maps input sequence
a = < a1, …, aN > to output sequence b = < b1, …, bN >,
Then for any monotonically increasing function f( ． ),
it maps f(a) = < f(a1), …, f(aN) > to f(b) = < f(b1), …, f(bN) >
( Basic idea: large numbers remain larger (no smaller) than small
numbers after mapping
→ Comparator states do not change)

Example : f( ． )

2 3 3 1 2
4 4 + 2
1
3 3
3 2 2 1
2 3 4
31
 x min(x, y)
y max(x, y)
x  y  f (x)  f (y) and x  y  f (x)  f (y)
for any monotonic function f

f(x) min(f(x), f(y))

  f (min(x , y)) if x  y
 ff ((yx))  f (min(x , y)) if x  y
f(y) max(f(x), f(y))


 ff ((yx))  f (max(x , y)) if x  y
 f (max(x , y)) if x  y

Fig. 3.16. Illustration that a comparator has the order-preserving property

32
 ai ci = min(ai, aj)
aj cj = max(ai, aj)
Fig. 3.17. (a) The inputs and outputs of a comparator at stage d when input
sequence is a

f(ai) min(f(ai), f(aj))

= f(min(ai, aj) ) = f(cj)
f(aj) f(cj)

Output of stages before stage d

By assumption of induction, they must be f(ai) and f(aj)

Fig. 3.17. (b) The inputs and outputs of the same comparator when
input sequence is f(a)

33
 < a1, …, aN >
.. Sorting
Network .. aj By contradiction,
assume ai < aj, but
. .. ai aj placed before ai

By order-preserving property

< f(a1), …, f(aN) >

.. Sorting
Network .. f(aj) = 1
(zero-one sequence) . .. f(ai) = 0

  ai
f (x)  10 ifif xx  ai
1

0 ai x

Fig. 3.18. Illustration of the proof of the zero-one principle

34
 2-merger
..
..
2-merger
4-merger N/2-merger
. .
. … .
N-merger
.
2-merger
..
2-merger
4-merger N/2-merger
.
k/2
sorted
... .
numbers N-merger . k sorted
k/2 . numbers
sorted
numbers
2-merger = comparator

Fig. 3.19. Sorting based on merging, successive shorter sorted sequences

are merged into longer sorted sequences
35
Example of sorting by merger :

0 0 0 0
1 2-m 1 0 0

1 0 4-m 1 0
0 2-m 1 1 0

0 0 0 8-m 1
1 2-m 1 0 1

0 0 4-m 1 1
1 2-m 1 1 1

36
 Ascending
Sequence
.. ..
k-bitonic
. Ascending
Descending
Sequence
.. sorter Sequence

or
Descending
Sequence
.. ..
k-bitonic
. Ascending
Ascending
Sequence
.. sorter Sequence

The two input sequences do not have to be the same length

The two input sequences are of opposing directions

Fig. 3.20. Bitonic Sorters

37
 Half-cleaner
a1 min(a1, an+1)
a2 min(a2, an+2)
... .. a’
. bitonic

an min(an, a2n)
an+1 max(a1, an+1)
an+2 a”
... max(a2, an+2)
... bitonic
a2n max(an, a2n)

If a is a zero-one sequence, either a’ is all 0’s

or a” is all 1’s, or both

Fig. 3.21. A half-cleaner

38
 Half-cleaner - operations
Compare
0 0 Bitonic
Clean
0 1 0 1
1 0 0 1 Bitonic
0 Top Bottom Min Max 0
Compare
0 Bitonic
0
1 0 0 Clean
1 0 0 1
0 1 Bitonic
Top Bottom Min Max

Fig. 3.22. Operations performed by a half-cleaner for different cases

39
 Half-cleaner - operations
Compare
0 0 Bitonic
0 Clean
1 0 0
0 Bitonic
0 0
Top Bottom Min Max
Compare
0 0
Bitonic
0 1 0 0
1 1
1 0 0 Bitonic
1 Clean
0 Top Bottom Min Max

Fig. 3.22. Operations performed by a half-cleaner for different cases

40
Examples of Bitonic Sequence (Circularly Bitonic) :

41
Physical picture of half-cleaner action on arbitrary-number
bitonic sequence :

Half of #s above green line,

half below

Min Max

42
 Bitonic Sorter

. ... k/2-bitonic ...

. k-half cleaner
. cleaner
... k/2-bitonic ...
cleaner

Fig. 3.23. Recursive construction of a k-bitonic sorter (merger)

43
 Bitonic Sorting Network
2-bitonic
sorter 4-bitonic
2-bitonic sorter
sorter 8-bitonic
2-bitonic sorter
sorter 4-bitonic
2-bitonic sorter
sorter
Fig. 3.24. (a) A sorting network based on merging using bitonic sorters

Four 2-bitonic Two 4-bitonic One 8-bitonic

sorter sorter sorter
Fig. 3.24. (b) The same network broken down into comparators 44
 Odd-even Sorting Network
a1 d1 c1
a2 d2 c2
a3 Odd d3 c3
...
a4
Merge ...
d4 c4
c5
c6
an dn
c7
.. .
b1
b2
e1
e2 . .
b3 Even e3
...
b4
Merge
e4
... .
bn en c2n

Fig. 3.25 Recursion for Odd-even Sorting Network

45
 Odd-even Sorting Network - Proof
Proof that ei-2  di  ei
n even
a   a1 ,a3 ,  a   a2 ,a4 , 
b   b1 ,b3 ,  b   b2 ,b4 , 
 f (x)  (nx , mx ) where nx  #zeros in x , mx  #ones in x
 na   ma   nb   mb 

 f (a )  (  ,  ) 
fb( )  (  ,  )
2  2  2  2 
 na   ma   nb   mb 

f (a )  (  ,  ) 
fb( )  (  ,  )
2  2  2  2 
 na   nb   ma   mb 
 f (d )  (     ,     )
2 2  2   2 
 na   nb   ma   mb 
f (e)  (     ,     )
2 2  2   2  46
 Odd-even Sorting Network - Proof
a  00011111, na  3, ma  5;
b  00111111, nb  2, mb  6.
odd : a  0011, b  0111;
even : a  0111, b  0111.
n  n 
na   a    a 
2 2
odd even
3 5
f (a)  (2,2)  (  ,  )  (2,2);
2  2 
3 5
f (a)  (1,3)  (  ,  )  (1,3).
2  2 
 n  n  m  m  
f (d )  f (a)  fb( )    a    b  ,  a    b   ;
 2   2   2   2 
 n  n  m  m  
f (e)  f (a)  fb( )    a    b  ,  a    b   .
 2   2   2   2  47
 Odd-even Sorting Network - Proof
ei 2  di  ei
There are at most three possible cases:
(1) nd  ne ,
d1 d2 ...... di ......
0 0 ......0 1 1......1
0 ...... 0 0 1......11
e1 .... ei 2 ei 1 ei ...... ;
(2) nd  ne  1,
d1 d2 ...... di ......
0 0 ......0 1 1......1
0 ...... 0 1 1......11
e1 .... ei 2 ei 1 ei ...... ; 48
 Odd-even Sorting Network - Proof
(3) nd  ne  2,
d1 d2 ...... di ......
0 0 ......0 1 1......1
0 ...0 1 1 1......11
e1 .... ei 2 ei 1 ei ...... .

Do not hold: nd  ne  3,
d1 d2 ...... di ......
0 0 ......0 0 1......1
0 ...0 1 1 1......11
e1 .... ei 2 ei 1 ei ...... ;
49
 Informatio Header
n bits …
0100 Comparator
… in bar state
1000
Order of arrival from right to left
…
010 0 Remain in bar state
… after first bit
100 0

…
01 00
Remain in bar state after
…
10 00 second bit

… Set to cross state after third

0 000
… bit because upper input is
1 100 larger, remains in cress state
for the whole packet duration
Fig. 3.26. The operation of a comparator used in a sorting network
for packet switching 50
 Batcher-banyan network

Batcher (Bitonic Sort) Network Banyan Network

010
011 0 0 0 000
011 1 1 1 001
0 0 0 010
1 1 1 011
010 0 0 0 100
1 1 1 101
0 0 0 110
1 1 1 111
Shuffle
MSB
Activity 1 if inactive
Address Activity Bit Bit 0 if active

Fig. 3.27. An 8x8 Batcher-banyan network

51
 Batcher-banyan network - Complexity

Number of comparators in a Batcher bitonic sorting network :

* f(k) = # stages in a k-bitonic sorter
= log2k
log2 N log2 N
log 2 N(log 2 N  1)
*  fi(2 )  
i 1
i

i 1

2
N log2 N(log 2 N  1)
* # comparators  
2 2
 N log2 N

52
 Three-phase scheme – stage 1

4 2
5 4
Output i 4
Destinations 4 4 Banyan
i = idle outputs i 5 Network
2 i
4 i
i i
Sorting
Network Sorted header. Each output
examines the output above
for possible conflict

Fig. 3.28. (a) Three-phase scheme for sort-banyan network

( Stage 1: probing for conflict )

53
 Three-phase scheme – stage 2

2
4
4
4 Banyan
5 Network
i
i
i

Acknowledgement
path is reverse of
forward sorting path
Fig. 3.28. (b) Three-phase scheme for sort-banyan network
( Stage 2: acknowledgement of winning packets )

54
 Three-phase scheme – stage 3
Concentrated and monotonic
output addresses

4 2
5 4
5

Fig. 3.28. (c) Three-phase scheme for sort-banyan network

( Stage 3: routing winning packets )

55
 Nonblocking and Self-routing Properties
of Clos Networks
Packet switching with Clos networks :
o The Clos network — first studied by C. Clos in 1953

o Features :

— Rearrangeably non-blocking

— Requires centralized route assignment

— Self-routing is impossible in genernal [1]

[1]
B.G. Douglass and A.Y. Oruc, “On self-routing in Clos connection
networks”, IEEE Trans. On Commun., Vol. 41, No. 1, Jan 1993, pp.121-
124
56
 Nonblocking Route Assignment

o Generalization of the sort-banyan principle

o The non-blocking and self-routing properties of Clos

network
o Simple route assignment with an appropriate addressing
scheme
o General Clos-type network from the cascade combination
of a MIN and its reverse network

57
 Address Numbering Scheme
s [s]q q × q  s / q  p × p d / q  q × q [d]q d
0 0 0 0 0 0 0 0

..
1
..
1
0 .. .. 0 .. .. 0
1
.. ..
1

q-1 q-1 q-1 p-1 p-1 q-1 q-1 q-1

q 0 0 0 0 0 0 q

..
q+1
..
1
1 .. .. 1 .. .. 1 ..
1
..
q+1

.. .. .. .. ..
2q-1 q-1 q-1 p-1 p-1 q-1 q-1 2q-1

. . . . .
(p-1)q 0 0 0 0 0 0 (p-1)q

..
(p-1)q+1
..
1
p-1 .. .. q-1 .. .. p-1
1
.. (p-1)q+1
..
pq-1 q-1 q-1 p-1 p-1 q-1 q-1 pq-1

s  ( s / q  ,[ s]q ) d  (d / q  ,[d ]q )

a b
Fig. 3.30. A three-stage Clos network with address numbering scheme 58
Continued :

b
q=4
3 7 11
3
2 6 10
2
1 5 9
1
0 4 8
0 a
1 2 p=3

d = aq + b, 0  a  p-1
0  b  p-1

59
 Nonblocking Route Assignment

A sufficient non-blocking condition :

Let π= {(s1, d1), … , (sn, dn)}
An assignment f : π→ C is non-blocking if
f(si ,di )  f(s j ,d j )  si - s j  q and di - d j  q

 di 
Routing tag from si to di : ( f (si ,di ) ,   ,[di ]q )
q
 si 
Routing tag from di to si : ( f (si ,di ) ,   ,[si ]q )
q 

60
A fundamental lemma :
Let x1, x2,…, xn be a strictly monotonic sequence of
integers and for all i, define

g(xi) = [m+i]q for all i

where m and q are constant integers. Then

g(xi )  g(x j )  xi - x j  q for all i  j

61
Proof :
Without loss of generality, assume that the sequence is
increasing and let i < j. We have
g(xi )  g(x j )  i  lq  j where l  1

Now, xi - x j  (x j - x j -1 )  (x j -1 - x j -2 )  (xi 1 - xi )

 1  1  j  i  lq  q
j-i

62
Rank-based assignment algorithm :
Route assignment based on the “rank” of each connection
request
Let π= {(s1, d1),…,(sn, dn)} be monotonic. The assignment

f (s1, d1) = [m + i]q

where m is a constant integer and i is the rank of connection

(si, di) in π, is non-blocking [2]

[2]
K. Sezaki, Y. Tanaka and M. Akiyama, “N:1 Connection Switching
Networks Suited for Time Division Switching”, Computer Networks and
ISDN Systems, No. 20, 1990, pp. 383-389
63
Proof :
The sequences (s1,…, sn) and (d1,…, dn) are monotonic
Let
g1(si) = f (si, π(si)) = f (si, di) = [m + i]q
g2(di) = f (π-1(di), di) = f (si, di) = [m + i]q

Thus f (si, di) = f (sj, dj) implies

g1(si) = g1(sj) and g2(di) = g2(dj)
By Lemma 1 si  s j  q and di  d j  q

Hence the assignment is non-blocking

64
An example : 1 3 5 6 9 11
π=
2 4 7 9 10 11

si 1 3 5 6 9 11
di 2 4 7 9 10 11
m+i 0 1 2 3 4 5
f (si, di) = [m + i]q 0 1 2 3 0 1
Routing tag (0,0,2) (1,1,0) (2,1,3) (3,2,1) (0,2,2) (1,2,3)
0 0 (0,0)
1 1 (0,1)
2 2 (0,2)
3 3 (0,3)
4 4 (1,0)
5 5 (1,1)
6 6 (1,2)
7 7 (1,3)
8 8 (2,0)
9 9 (2,1)
10 10 (2,2)
11 11 (2,3)
Fig. 3.31. Route assignment for π 65
Order preserving property :
si
mi ni
... ... ... ...
di
si < sj M di < dj
mj nj
sj dj
Fig. 3.32. Order is preserved in a middle-stage module M

Due to Rank-based Assignment Algorithm,

si - s j  q and di - d j  q
 s j   si  q   si 
mj           1  mi  1  mi
q   q  q 
 d j   di  q   di 
nj           1  ni  1  ni
q   q  q 66
Recursiveness :
o Consider a 3-stage Clos network with parameter p0 and q0. Let
the rank of a packet from si to di be r0(si)
o The middle-stage module assigned to the request (si, di) is
[r0(si)]q which can be obtained by decomposing r0(si) :
0

r0(si) = α1(q0) + α0
r1 (si )  r0 (si ) / q0    r0 (si ) q
0

rank in the subnetwork rank in the subnetwork

o Suppose the subnetwork has parameters p1 and q1.
The route assignment in the subnetwork is :
r1 (si ) q
1
  r0 (si ) / q0   q1

67
If N = q0q1…qn-1 , number of stages = 2n – 1
 qi for 0  i  n  1
The size of a stage-i module is 
q2 n-2-i for n -1  i  2n  2
r0  si   1 ' q0    0
  2 ' q1   1  q0   0
  2 ' q1q0  1q0   0
 
  3 ' q2    2  q1  1 q0   0
  3 ' q2q1q0   2q1q0  1q0   0
 ...
n 1 i 1 n 1 i 1
In general, r0 (si )   i  q j   0 and di    i  q j   0
i 1 j 0 i 1 j 0

The routing tag is : (α0,α1,α2,…,αn-2,βn-1,βn-2,…,β1,β0)

68
Example :
Benes network: qi = 2 for all i

s 0 1 3
d 1 2 4
r 0 1 2
r   3 21 0 0000 0001 0010
d  3 2 1  0 0001 0010 0100
R =α0α1α2β3β2β1β0 0000001 1000010 0100100

s 4 7 8 10 12 13
d 6 9 10 12 14 15
r 3 4 5 6 7 8
r 0011 0100 0101 0110 0111 1000
d 0110 1001 1010 1100 1110 1111
R 1100110 0011001 1011010 0111100 1111110 0001111

69
0 0
1 1
2 2
3 3
4 4
5 5
6 6
7 7
8 8
9 9
10 10
11 11
12 12
13 13
14 14
15 15

70
General Clos-type Networks :

Clos Network

Reverse Omega Network Omega Network

Fig. 3.34. Dividing a Clos network into two half-Clos networks 71
 The Omega Network :

si bi ai ai bi q=3 xi ai p = 4 xi yi di
0 00 00 0 0 00 0
1 01 01
0
1 1 0 01 1
2 02 02 2 2 02 2
s  03 3 d 
bi   i  xi   i 
q  3 10 0 10 3 q
4 11
10 0
1 1 11 4
5 12 2 12 5
ai   si  q 11 1 yi  di  q
12 1 2
6 20 13 3 0 20 6
7 21 1 2 21 7
8 22 2 22 8
20 0
9 30 21 1 0 30 9
10 31 22 2 2 1 3 31 10
11 32 23 3 2 32 11
Non-blocking if and only if ai = aj → xi ≠ xj
Routing tag for output xi yi : (xi, yi)
Fig. 3.35. An omega network 72
 The Reverse Omega Network :
si ai bi p = 4 xi ai q=3 xi yi yi xi di
0 00 0 0 00 00 0
1 01 0 1 1
0
01 01 1
2 02 2 2 02 02 2
s  3 03 d 
ai   i  yi   i 
q  3 10 0 10 3 q
4 11 1 1
0 10
11 4
5 12 2 12 5
bi   si  q 1 11 xi  di  q
2 1 12
6 20 0 3 13 20 6
7 21 2 1 21 7
8 22 2 22 8
0 20
9 30 0 1 21 30 9
10 31 3 1 2 2 22 31 10
11 32 2 3 23 32 11
Non-blocking if and only if ai = aj → xi ≠ xj
Routing tag for output yi xi : (xi, yi)
Fig. 3.36. A reverse omega network 73
Cascade combination :
Reverse Omega network Omega network
stage 1 2 3 4 5
0 00 0 0 00 00 00 00 0 0 00 0
1 01 0 1 1 01 01 01 01 1 1 0 01 1
2 02 2 2 0 02 02 02 02 0 2 2 02 2
3 03 03 3
3 10 0 10 10 0 10 3
4 11 1 1 11 11 1 1 11 4
5 12 2 0 10 12 12 10 0 2 12 5
1 11 11 1
2 1 12 12 1 2
6 20 0 3 13 20 20 13 3 0 20 6
7 21 2 1 21 21 1 2 21 7
8 22 2 22 22 2 22 8
0 20 20 0
9 30 0 1 21 30 30 21 1 0 30 9
10 31 3 1 2 2 22 31 31 22 2 2 1 3 31 10
11 32 2 3 23 32 32 23 3 2 32 11

Fig. 3.37. Combining a reverse omega network and an omega network 74

Cascading a MIN and its reverse network results in a
general Clos-type network :
MIN pxp MIN-1

.. ...
... ...
si
N inputs
... .. N outputs

.. di

(n-1) stages middle (n-1) stages

stage

Unique path for each input-output pair in MIN and

its reverse network
Total N/p alternate paths in Clos-type network

75
Self-Routing Properties of Sort-Clos Network Problems :
Concentration required
Contention resolution
by the Three-phase
Algorithm [3]

sorting network + omega network

Contention resolution Concentration required

consists only of two
phases.
Generalization of the
sort-banyan principle
sorting network + omega network

[3]
J.Y. Hui and E. Arthurs, “A Broadband Switch for Integrated Transport”,
IEEE JSAC, Vol. SAC-5, No. 8, Oct. 1987, pp. 1264-1273 76
Multicast connections :
o Extension to broadcast Clos network
o Let the set of active inputs be (s0,s1,…,sn-1)
Let their corresponding sets of outputs be (D0,D1,…,Dn-1)
The set of connection requests is monotonic if
si  s j  di  d j di  Di and d j  D j ; or
si  s j  di  d j di  Di and d j  D j

o Non-blocking route assignment by the Rank-

based Assignment Algorithm

77
An example :
si 2 3 4 5 8
Di 0,1 2,3,4 5,6 7,8,9 10,11
m+i 0 1 2 3 4
f (si, di) = [m + i]q 0 1 2 0 1

s s d d
0 00 00 0
1 01 01 1
2 02 02 2
3 10 10 3
4 11 11 4
5 12 12 5
6 20 20 6
7 21 21 7
8 22 22 8
9 30 30 9
10 31 31 10
11 32 32 11

78
Routing and replication :
o Routing from input to middle-stage modules by
decomposing the rank :
n 1 i 1
r0 (si )   i  q j   0
i 1 j 0

o Routing tag to middle-stage module : (α0,α1,…,αn-2)

o Replication and routing controlled by the General Interval
Splitting Algorithm

79
General Interval Splitting Algorithm :
o Each packet is assigned an address interval represented
by minimum and maximum
o Suppose a node a stage i (n -1  i  2n - 2) receives a
packet with address interval specified by:
min (i-1) = mn-1 … m2n-2
max (i-1) = Mn-1 … M2n-2

o The bases of mi and Mi are q2 n-2-i for n -1  i  2n - 2

o Replication is controlled by the digits mi and Mi

80
General Interval Splitting Algorithm (continued) :

The following procedure is performed :

1. If mi = Mi , then send the packet out on link mi
2. If mi ≠ Mi , then (Mi - mi + 1) copies are required
Replicate the packet, modify the headers and send the
packets out on link mi to Mi

81
 Header modifications :

stage-(i+1)
minimum unchanged
.. min(i) = min(i-1) = (mn-1 ,…,mi,mi+1 ,…,m2n-2)

stage-i mi ... max(i) = (mn-1,…, mi, q(2n-2)-(i+1) -1,…, q0-1)

..
..
j
.. min(i) = (mn-1 ,…, mi-1, j, 0, …, 0)
max(i) = (mn-1,…, mi-1, j, q(2n-2)-(i+1) -1,…,q0-1)

Mi
...
.. min(i) = (Mn-1 ,…, Mi, 0, …, 0)
max(i) = max(i-1) = (Mn-1,…,Mi,Mi+1,…,M2n-2)
maximum unchanged

82
An example :
s d
000 002 000
001 002 001
002 002
010
010 002 002 012 010
011 101 012 011
012 012
100 100
101 100
101
101 100
102 101 102
110 110
111 111
112 112
83
Decomposition and generalization :
Reverse Omega network Omega network
stage 0 1 2 3 4
00 0 0 00 00 00 00 0 0 00
01 0 1 1 01 01 01 01 1 1 0 01
02 2 2 0 02 02 02 02 0 2 2 02
3 03 03 3
10 0 10 10 0 10
11 1 1 11 11 1 1 11
12 2 0 10 12 12 10 0 2 12
1 11 11 1
2 1 12 12 1 2
20 0 3 13 20 20 13 3 0 20
21 2 1 21 21 1 2 21
22 2 22 22 2 22
0 20 20 0
30 0 1 21 30 30 21 1 0 30
31 3 1 2 2 22 31 31 22 2 2 1 3 31
32 2 3 23 32 32 23 3 2 32

84
 Generalized copy network architectures :

Running Adder
Non-blocking copy
Network (RAN) Broadcast Trunk
network based on and Concentrator Banyan Number
broadcast banyan Dummy Address Network Network Translator
network Encoders (BBN) (TNT)
(DAE’s)

Running Adder
Non-blocking copy
Network (RAN) Trunk
network based on Broadcast
and Number
broadcast Clos Dummy Address
Clos Translator
network Encoders Network (TNT)
(DAE’s)

85
Conclusions :
o The principle governing the non-blocking and self-routing
properties of a large class of interconnection networks
o Non-blocking and self-routing properties of Clos networks
o Construction of a general Clos-type network by cascade
combination of any MIN and its reverse network
o Extension to multicast network based on broadcast Clos
network

86
~END~