IEG4020

Telecommunication Switching and Network Systems

Chapter 4
Switch Performance Analysis
and Design Improvements
 Internally Nonblocking Switch:
Loss System
1 P = Pr[ carry a packet ]
2
3
2

Pr[ carry a packet ] = 0

0
1  p  (1  )N
N
0 N
p  1  (1  )  1  e  0 for large N
N

For 0 =1, p  0.632

2
 Winning packet
Input Queues Losing packet Outputs
31 1
Cannot access 21 Internally 2
output 2 because 4 Nonblocking
3
it is blocked by the Switch
3 4
first packet

Fig. 4.1. Illustration of head-of-line (HOL) blocking.

3
 Output 1
Fictitious Output
(3,2) (1,2) Output 2
Queues formed by
HOL packets (2,3) Output 3
(4,4) Output 4
(input, output)
Outputs
(1,1) (1,2) 1
(2,1) (2,3) Internally 2
(3,2) (3,2) Nonblocking
3
Switch
(4,1) (4,4) 4

Fig. 4.2. An input-buffered switch with the fictitious

queues used for analysis.

4
 Throughout of Input-Buffered Switch

o Consider a fictitious queue associated with a

particular output i

C mi = # packets at start of time slot m.

Ami = # packets arriving at start of time slot m.

Bmi = # packets remaining at end of time slot m

Fmi = # inputs that won contention in time slot m

5
 e.g. Fictitious Queue i

Ami  2 C mi 1  3
1 i
i 1
i i
1 2
2 2
3 i
time time
slot slot
m m-1

6
 The empty probability of
… any output link is (1   )

…
C mi  Bmi 1  Ami
 max(0, C mi 1  1)  Ami
N
Fm 1   Bmi 1  N
i 1

N
E[ B i
m 1 ]  N(1   )  E[Bmi 1 ]  1  
i 1

Fm1 Fm1
E[ ]1  1  E[ ] 
N N
7
  
k
F 1 1 Fm1 k
PN [ A  k |Fm 1 ]  k   (1  )
i
m
m 1
N N

Ami is Poisson and independent of Bmi 1 as N  

k
 Pr[ Ami  k ]  e 
k!


A(z)   Pr[ A  k] z k  e( z 1) 
k 0

8
 
B(z)   z k Pr[B  k ]
k 0
 Pr[B  0]  z Pr[B  1]  ...
 Pr[C  0]  Pr[C  1]  z Pr[C  2]...
 (1  z 1 )Pr[C  0]  z 1C (z)

1 

C (z)  [(1  z 1 )(1   )  z 1C (z)]A(z)

C (z)(z  A(z))  (z  1)A(z)(1   )
2C '(1)(1  A '(1))  A "(1)  2 A '(1)(1   )
1  2 
under
saturation
 2  4   2  0   *  2  2  0.586

max. throughput
9
 Meaning of Saturation Throughput

0 =    = throughput

Input Queue
1. Let   0.586 be the saturation throughput of the input-
*

buffered switch with FIFO discipline.

   , the throughput    0 ,
*
2. When the offered load 0
the system is stable.
3. When the offered load 0   , the throughput    ,
* *

the system is saturated. In this case, with probability 1 the

buffer will overflow.

10
How about small N?

Table 4.1. Maximum throughput for input-buffered

switches of different sizes.

11
 Fictitious Queues

Input Queue 1/N Output 1

1/N
N 2 Output 2
HOL
1/N
Time spent in HOL Output N
are independent for
successive packets
when N is large
Service times at
different fictitious
queues are
independent

Fig. 4.3. Queuing scenario for the delay analysis of the

input-buffered switch.

12
U(t)

 X0   X1  X2  X3  X0  t
Idle
Y period Busy period
Busy period

Arrivals here are Arrivals here are considered as

considered as arrivals in intervals i-1
arrivals in
intervals i-2

Xi-1 Xi

Fig. 4.4. The busy periods and interpretations for delay

analysis of an input queue.
13
 mi =2 Arrival of the packet of focus. One
simultaneous arrival to be served
prior before the packet; L=1.
arrivals
Departure of
(1) (1) (2) packet of focus.

Xi Xi+1
Ri
W

-- Packet arrival in interval i.

-- packet departure in interval i+1.
(n) -- number of arrivals
Fig. 4.5. Illustration of the meanings of random variables
used in the delay analysis of an input queue.

14
 W

0

Fig. 4.6. Different contention-resolution policies have different

waiting time versus load relationships, but a common maximum
load at which waiting time goes to infinity.

15
 Simultaneous arrivals are randomly placed on a
unit line to determine the order of service

0 t 1

Packet whose waiting time is

being analyzed is placed at t

Fig. 4.7. A unit line for determining the order of service

among simultaneously arriving packets.

16
Queuing Analysis in Output-buffered Switch
o Switch with Speedup factor of N.
o Arriving packets reach the targeted
output ”immediately”.
 = load 1
1
1
1
o Ami = # arriving packets at start of time slot m
Pr[ Ami  k ]  (Nk )( N )k (1  N )N k

N! e   as N  
k !(N  k )!

k  Poisson
 e Distribution.
k! 17
 Delay in Output-Buffered Switch
o C not necessarily  1
(z  1)A(z)(1   0 )
C (z ) 
z  A(z)
 02
C  C '(1)  0 
2(1  0 )
o Little’s’ Law  D  N
C 0
S 1
0 2(1  0 )

Average Delay

18
o What if FIFO constraint removed ?
Look-ahead scheme : look at first  packets
at each queue.

 1 2 3 4 
* 0.59 0.70 0.76 0.80 1

cost
 = overhead of one round of
contention  ( )
*

1  
Actual throughout =

19
 Output queues are
To avoid packet loss needed because packets
at inputs, input may arrive too many at a
queues are needed if time for immediate
S<N transmission at outputs

Switch with
speedup
factor = S

Each switch cycle = 1/S time slot. Up to S

packets may leave a given input or reach a
given output in a time slot.
Fig. 4.8. The speedup principle.
20
 Packet 2 will be directed to
switch 2 if packet 1 is cleared in
switch 1. Otherwise, packet 1
will be directed to switch 2.

Packet 2 Packet 1
2

Packets are directed to switch 1 in the first half-time slot and

to switch 2 in the second half-time slot.
Fig. 4.9. (a)

21
 Output address

Packet cut into half

Packet assembled

(b)
Fig. 4.9. Methods for achieving speedup effect without
speeding up switch operation: (a) using multiple switches;
(b) using packet-slicing concept.
22
 Channel Grouping

1 R In each time slot, at most 1

packet from each input and
up to R packets to each
N x NR output are cleared.

N R

R 1 2 3 4
* 0.59 0.89 0.98  1

Fig. 4.10. Channel Grouping

23
 e.g. R=S=2

3 1 1

1 2

2 3

2 4

All packets cleared if speedup;

packet 3 not cleared if channel
grouping

24
 0
Banyan
Network 0 Output
0
MUX
0
R-2
0
Batcher N-1
Network Banyan
Network
R-1 N-1
MUX
N-1
N-1

Output i (i=0, …, N-1)

connected to input  i/R  of
banyan network i mod R.
Fig. 4.11. A Batcher-R-banyan network that implements the channel-
grouping principle.
25
 Truncated
R-1 R
0 Banyan
Network
1 0
0 R
1
Truncated
Banyan
R-1 Network
N
R
0 N

Fig. 4.12. (a)

26
 Relative output
R 00 …0
Truncated
Banyan
Inputs connected Network Relative output
to outputs b1 ...bR R bR+1 …bn
of all expanders b1b2…bR

Relative output
R 11 …1

(b)

Fig. 4.12. (a) The expansion banyan network; (b) Labeling of the
truncated banyan network and its output groups.

27
 Rx1 switch working at R = 4
times the links rate
1
mux
R Output Queue
(a)
Rx1 switch working at same
speed as link rate

R 1
Shifting
mux
Concentrator
R

Packets are loaded into Packets are read out

queues in round-robin from queues in round-
fashion robin fashion
(b)
Fig. 4.13. (a) Multiplexer and output queue at an output of a channel-
grouped switch. To accommodate simultaneous packet arrivals, the
multiplexer must work R times faster than link rate. (b) An
implementation of a logical FIFO queue such that the multiplexer only
have to work at same speed as link rate.
28
Max Throughput of Channel-grouped switch
C m  max(0, C m 1  R)  Am
R 1
C (z)  A(z)[ (z R  z k )Pr{c  k}] / (z R  A(z))
k 0
R 1
 A(z) Pr{c  k}[(z  1)(z  z1 )...(z  zR 1 )] / (z R  A(z))
k 0

zis are roots of numerator

can show the roots of denominator zR-A(z) are 1, z1,
z2  …, zR-1  where |zi  | < 1
zi = zi  i, Otherwise C(zi ) infinity which is not
possible R 1
C  C (1)    [   R(R  1)] / [2(R   )]   1 / [1  zk (  )]
2

k 1
29
 Knockout Principle

If R is large, (e.g. R = 8), might as well not queue

packets at inputs. Simply drop them.

Loss probability is small

30
 Loss Probability in Knockout Switch

Pr[k packets destined for a particular output]

 N(
k 0  / N ) k
(1   0 / N )N k
 Pk
N
Ploss  (1 / 0 )  (k  R)Pk
k  R 1

 (1 / 0 )  (k  R)(0k / k!)e  0 for large N
k  R 1
 ...
 (1  R / 0 )[1  (0k / k!)e  0 ]  ( 0R / R!)e  0
Ploss  as R 
R  8 for Ploss  10 6
31
o We can show that the loss probability is bounded by
1
Ploss 
R!

o By employing the following inequalities

 N   N  N  R 
(1)      
 R  i   R  i 
i
i 
(2) 1  e N
N

32
  N   N  N  R 
Proof of      
 R  i R
   i 

 N  N!
 
 R  i  R  i !N  R  i !


N!

 N  R !

R! i !
R!N  R ! i !N  R  i ! R  i !

 N  N  R 
  
R i  N  N  R 
   
   
R  i  R
  i 
 
 R 
33
 i
i 
Proof of 1  e N
N

By the Taylor series expansion

 1 2  1 3
e  1  x   x    x   ...
x

 2!   3! 

i 2 3
i 1 i  1 i 
e 1
N
       ......
N 2!  N  3!  N 
2
i i  1
 1      ...... 
N N i
1
i
N
i 
1  e N
N

34
   N  
k N k
1 N
N   
Ploss  
 k  R 1
(k  R) k    1  
N
R i N R  i
1 
N RN     
Ploss  i   1   (by letting i = k - R )
 i 1  R  i   N   N 
R N R i N R  i
1  N     N  R     
   
  R  N 
 i
i
   1   by applying (1)
i 0   N   N 
R
1  N     Mean value of binomial random
     N  R    variable ρ/ N
  R  N  N
R
    N  1
   
N
   R  35
    N (N  1) N  2   N  R 
R R

 
 N  R! NR

1 1  2  3  R
 R
 1   1   1     1  
R!  N  N  N   N 
R  R 1 
R 1

 e 2N By applying (2)
R!
R  R 1 
1  (independent of input loads)
 e 2N
R!
1
Ploss  (independent of ports)
R!
36
 0 0 0 NxN 0
M
banyan UX
1 1 (1)
1
NxN
R ? Reverse- R banyan
M
UX
1
Batcher =
R+1
banyan (2)
Network ?
= Concentrator

NxN M N-1
banyan UX
N-1 ? (R)
=

Output
Address
Packet 1 a Let packet 2 go
? through if and only if
Packet 2 b =
ab

Fig 4.14. A Batcher-banyan knockout switch.

37
Running Adder Network (RAN)
produces concentrator - output address
0

RAN
1

0
RAN
1

Fig. 4.15. Running adder network.

38
 Central
Controller

Reverse banyan
Concentrator
Address (a)
assigned=Sum of all 0 0 0
activity bits above + + +
0 0
+ + +
Running Sum 0
Packet A + + +
0
Info a a + + +
+ Info b a+b
Info b b Packet B + + +
Packet B + + +
(b) + + +
+ + +
Fig. 4.16. (a) A central controller for computing the assignments of
packets to concentrator outputs; (b) a running-adder address generator
that computes the assignments in a parallel and distributed manner.
39
 1
2
Input
N
1 2 N 1 2 N

Knockout
Concentrator
1 2 R
Shifter
Output

Output 1 Output N
Fig. 4.17. A knockout switch based on broadcast buses and
knockout concentrators.
40
 Input

Packet filters
Knockout
element Delay element

Losing
packets

D D D D
D D
D D D
D D
D D D

1 2 3 4
Output
Number of switch elements =
(N-1)+(N-2)+ … (N-R) =
NR-R(R+1)/2  NR
41
 Packet Packet Packet Inactive Inactive Packet
a b a b

Fig. 4.18. An 8x4 knockout concentrator and operation of its

component 2x2 switch elements.

42
 Replication Principle

Single Banyan Network : Ploss  n0 / (n0  4)

Random Routing Parallel Banyan :

Ploss  (n 0 / k)[(n0 / k)  4]
 n 0 / (n 0  4k)

For a fixed Ploss requirement,

k  ( / 4)(log N / Ploss )
Total cross-points = ( / 4)(log N / Ploss )  (N / 2)(log N)
so, order of complexity = Nlog2N with a large constant.

43
 1 1st Banyan 1
Network
2 2

Kth Banyan
Network
N N

Random router or Statistical

broadcaster multiplexer
Fig. 4.19. A parallel-banyan network.

44
000 000
001 001

010 010
011 011

100 100
101 101

110 110
111 111

Fig. 4.20. An 8x8 banyan network with dilation degree 2.

45
 2 dxd
concentrator

2 dxd
concentrator

Complexity~ O(dlogd)
Fig. 4.21. An implementation of 2dx2d switch element with order of
complexity dlogd.

46
~END~