IEG4020

Telecommunication Switching and Network Systems

Chapter 2
Circuit Switch Design Principles
 Space-Domain Circuit Switching

Inputs Outputs

.. ..
1 1
2 2

. .
N N

Fig. 2.1. An N x N switch used to interconnect N inputs

and N outputs

2
 Strictly Nonblocking

Bar State Cross State

Fig. 2.2. Bar and cross states of 2 x 2 switching elements

3
 Strictly Nonblocking

2 Connections:
Inputs Input 1 to Output 3
Input 2 to Output 4
3

1 2 3 4
Outputs
Fig. 2.3. (a) Crossbar switch

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 Blocking
1 1
2 2

3 3
4 4

Blocking: Input 2 cannot be connected to output 2

if input 1 is already connected to output 1

Fig. 2.3. (b) banyan switch

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 Nonblocking Properties

RNB

WSNB

SNB

RNB — Rearrangeably Nonblocking

WSNB — Wide-sense Nonblocking
SNB — Strictly Nonblocking

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 Rearrangeably Nonblocking

1 1
2 2

3 3
4 4

Fig. 2.4. (a) A 4 x 4 rearrangeably nonblocking switch

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 Rearrangements
1 1 Connection cannot be
2 2 set up between input 4
3 3 and output 1
4 4
Fig. 2.4. (b) a connection request from input 4 to output 1 is blocked

1 1 Connection can now be

2 2 set up between input 4
3 3 and output 1
4 4
Fig. 2.4. (c) Same connection request can be satisfied by rearranging
the existing connection from input 2 to output 2

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Two states corresponding to the same mapping :

1 1
2 2
3 3

 
4 4
Input 1 2 3 4
Output 1 2 3 4
1 1
2 2
3 3
4 4

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Complexity of nonblocking switches :
How to build large switch from smaller switches?
Problems with two-stage networks :
n
1 1 1 1 n N = mn
# lines = m2n

..
2
..
2
..
2
..
2 = mN

. . . . Bandwidth expansion
factor = m
m m m m

(a) (b)

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 1． ．1
2． ．2
3． ．3
4． ．4

Fig. 2.5. (a) An example of one-to-one mapping from input to output

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 N! mappings
1 1
M crosspoints
2
. . 2

. . # states  # mappings

. . 2M  N !
M  log2 N !
 N log2 N
N N for large N

Fig. 2.5. (b) Number of crosspoints needed for nonblocking switch

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 Clos Switching Network
... n 1 × r2 r1 × r3 r2 × n 3
... ri — # switch
modules in
(1) (1) (1) column i
... n 1 × r2 r1 × r3 r2 × n 3
... n1 — # inputs in
column 1

..
(2) (2)
..
(2) module
n3 — # outputs in
. . column 3
... n 1 × r2 r1 × r3 r2 × n 3
... module

(r1) (r2) (r3) Necessary condition

for nonblocking:
n1r1 = n3r3 = N for N × N switch r2  n1 , n3
Fig. 2.6. A three-stage clos switch architecture

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1 1
Key:
2 F 2
Find a commonly
3 3
accessible middle
4 4
node from both
5 G B 5
input and output
6 6
nodes
7 7
8 A H 8
9 9

A request for connection from input 9 to output 4 is blocked

SA = middle-stage nodes used by A
= { F, G }
SB = middle-stage nodes used by B
={H}
Fig. 2.7. An example of blocking in a three-stage switch

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 F
G
A
B
H

Stage 3 switch
1 2 B r2
1
2
Stage 1
switch
A F,G,H

r1

Fig. 2.8. The connection matrix of the three-stage network

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 Fundamental Conditions
Conditions of a Legitimate connection Matrix :

1. SA  n1 , SA  number of symbols in row A

2. SB  n3 , SB  number of symbols in row B
3. r2  n1
r2  n3  necessary condition for
nonblocking property
4. Symbols in each row (column) must be distinct
SA , SB  r2

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 Condition for Strictly Nonblocking
Clos network is strictly nonblocking iff
r2  minn1  n3  1 , N

Proof: Trivial case : N  n1  n3  1

If n1  n3  1  N :
Worst case: all other inputs of A and outputs of B are busy
SA  n1  1
SB  n3  1
SA  SB  SA  SB  SA  SB
 SA  SB
 n1  n3  2
if r2  n1  n3  1 ,
there is at least one available middle-stage node
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 Condition for Rearrangeably Nonblocking

Rearrangeability allows condition to be reduced to

r2  max n1 , n3 

Rearrangement
—— Substituting symbols in connection matrix such that

1.) Matrix remains legitimate

2.) An unused symbol in row A and column B can be found

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 Condition for Rearrangeably Nonblocking
SA SB
Proof: i) "Only if " part trivial
ii) "if " part
． C ‧D
 S A  n1  1
 S  n 1
 B 3

a.) S A  SB  r2   an unused symbol

b.) S A  SB  r2
S A  SB  S A  SB  SB
 r2  (n3  1)  1
SB  SA  r2  (n1  1)  1
  a symbol C in row A, not in column B
 a symbol D not in row A, but in column B
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 B’ B B” SA  SB  r2
Chain terminates
at A” because A’ D C Connection between A
and B is blocked
A’’ D C  SB
C  SA A C
A’” C D
D  SA

Fig. 2.9. (a) A chain of C and D originating from B

..
A’ .. ..
A already .. B’
B already
connected to A” C .. connected to
all middle- .. .. B all middle-
stage nodes A .. stage nodes
.. D
except D .. B” except C
A”’
.. ..
Only links used by connections in the chain are shown
Fig. 2.9. (b) Physical connections corresponding to the chain
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 C D
A loop in the chain
C D

D C  There should be two

end points in a chain
D occurs twice in this column,
making the matrix illegitimate
(i.e. physically impossible in
associated switch)

Fig. 2.10. Illustration showing loops in chains are not

permitted in legitimate connection matrix

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 B’ B B”

A’ C D D can now be put in

A” C entry (A, B)
A C
A”’ D C

Fig. 2.11. (a) Rearrangement of the chain in Fig. 2.9.

..
A’ .. ..
.. B’
A” C ..
.. .. B
A ..
.. D
B”
A”’
.. ..
..
Fig. 2.11. (b) Corresponding rearrangement of connections
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 B
D C
...D
...D
D C
A C
C D
Fig. 2.12. (a) Two chains, one originates from B, one from A

B
This column D C
search ends in
C, which is not
. .. Start searching from B.
D Column search always
possible
looks for D
A C
C D

Fig. 2.12. (b) Illustration that the two chains cannot be connected
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How many rearrangements?
o A new row/column is covered each time a point is
included
o (r1 + r3 – 2) other rows and columns
o At most (r1 + r3 – 1) rearrangements (loose)
Can do better: # rearrangements  min(r1 , r3 )  1
o Basic: consider two chains, one originates from row A,
one from column B
Choose the shorter chain for rearrangement
o A composite move: a move in chain 1 with a move in chain 2
At most r1 – 2 moves before all rows exhausted
At most r3 – 2 moves before all columns exhausted

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 Benes Switching Network
1 1
2 2x2
.. N N

2 2
.. 2x2 2

3 3
4 2x2 2x2 4
.. ..
. .
.. N N
 ..
N-1 2 2 N-1
N 2x2 2x2 N
The N x N network is rearrangeably nonblocking if
N N
the  networks are rearrangeably nonblocking
2 2
Fig. 2.13. Recursive decomposition of a rearrangeably
nonblocking network
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 Benes Network - Complexity
Number of 2x2 elements in Benes Network :
Let N  2n and f(k)  # stages in k x k Benes Network, then
N
f (N)  f ( )  2
2
ff(2n )  (2n-1 )  2
 f (2n-2 )  4
.
.
 fj(2n- j )  2
 f (2)  2(n -1)
 1  2(n -1)
 2n -1  2log 2 N  1

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 Benes Network - Structure
1 1
2 2

3 3
4 4

5 5
6 6

7 7
8 8
Baseline
Network Reverse
Baseline
Network

Fig. 2.14. An 8x8 Benes Network

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 Baseline and Reverse Baseline Networks

Baseline Network

Reverse Baseline Network

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 Looping Algorithm
1 1
2 2

3 3
4 4

5 5
6 6

7 7
8 8

Set up paths for input-output pairs :

(1, 4), (2, 5), (3, 6), (4, 3)
(5, 7), (6, 8), (7, 1), (8, 2)
Central Algorithm: # steps = N logN

input 1 2 3 4 5 6 7 8
output 4 5 6 3 7 8 1 2 
Fig. 2.15. Illustration of a looping connection setup algorithm
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 Properties of Benes Network

1.) Unique path property of underlying baseline and reverse

baseline networks

2.) Binary tree to middle-stage nodes

An input can reach 2j-1 nodes at stage j, j <= log2N

3.) Reachability of nodes in baseline/reverse baseline networks:

A node in stage i can be reached by 2i inputs and
can reach 2n-j+1 outputs

4.) Middles nodes blocked by an existing path

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 Cantor Network

1 .. .. 1

2
.. .. 2
. .
. m=1
.. .
. .

N .. .. N

m = log N
Fig. 2.16. Cantor network
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 Cantor Network – Strictly Nonblocking
Cantor Network is SNB :
1.) Let m be # of Benes Network required
2.) Worst case: all other N-1 inputs/outputs busy
→ there are (N-1) paths to middle nodes
3.) One path meets the binary tree at stage 1
Two paths at stage 2
Let the # paths meeting the binary trees at stage i be Ai
Stage 1 Stage 2 …
Ai  2 - 1
i

log2 N
Check:  A  N 1
i 1
i

An example of 8 x8 Benes network

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 Cantor Network – Strictly Nonblocking

4.) A node in stage i blocks

Bi  2ni 1 middle nodes
(e.g. i  1, half the nodes or 2n-2 nodes are blocked)
# middle nodes log2 N 1
N
eliminated
 
i 1
Ai Bi 
4
(log 2 N  1)

# middle nodes eliminated

5.) # middle nodes >
by inputs and outputs
Nm N
 2  (log 2 N -1)
2 4
m  log 2 N -1

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 Connection paths from inputs 1 and 2 intersect
with binary tree from the first time in stage 2

1 1
2 2

3 3
4 4

5 5
6 6

7 7
8 8

If input 4 is connected to this link: Therefore the two lower middle-

a subtree is formed by the three stage nodes are eliminated from
subsequent nodes connection by input 3

Fig. 2.17. Binary tree extended from an input to

all middle-stage nodes
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 # middle nodes blocked from inputs
Number of paths Number of middle-stage nodes blocked
N
1
4
N
2
8
N
4
16
.. ..
. .
Total number of middle N N N N
 1  2   ...   1   0
nodes blocked from inputs 4 8 4 2
N
 (log 2 N  1)
4
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 Time-Domain Switching

D D
E E
M M
U U
X X

Space division switch

Fig. 2.18. Performing time-slot interchange using space-division switch

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 Time-Domain Switching

TSI

Write Read

Write Address a Read Address

Sequence = a, b, c b Sequence = b, a, c
c

RAM
Switching in time domain

Fig. 2.19. Direct time slot interchange using random access memory
(switching in the time domain)
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 Example for Time-Domain Switching
Example: memory access time
T  1 rate  1.5Mbps
N  24
Each data source is 64 kbps
One byte per time-slot
24 x 64,000 bps
Arrival rate =
8 bits/time-slot
=192,000 time-slots/sec
A read and a write required per time-slot
1
 memory access time   2.6  s
2 x 192,000
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 Time-Space-Time Switching
n m m n

TSI TSI

TSI TSI
.. rxr ..
. .
TSI TSI

n, m : number of time slots per frame at various points

Fig. 2.20. A time-space-time switch

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 Time-Space-Time Switching
( i, j ) — data on input i at time-slot j

Frame

C(1,3) B(1,2) A(1,1) TSI TSI

1 3 2
F(2,3) E(2,2) D(2,1) TSI 3x3 TSI
3 1 1
L(3,3) H(3,2) G(3,1) TSI TSI
2 2 3

Targeted Outputs

Fig. 2.25 A time-space time switch

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 Time-Space-Time Switching
A(1,1) M CBA M D(2,1)
BAC EDC CED
B(1,2) U TSI TSI U E(2,2)
X (1) (1) X
C(1,3) C(1,3)

D(2,1) M M A(1,1)
FED EDF HAL LHA
E(2,2) U TSI TSI U H(3,2)
X (2) (2) X
F(2,3) L(3,3)

G(3,1) M M G(3,1)
LHG HGL BGF GBF
H(3,2) U TSI TSI U B(1,2)
X (3) (3) X
L(3,3) F(2,3)

Fig. 2.21. Equivalent of time-space-time switching and

three-stage space switching

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B(1,2) A(1,1) C(1,3) E(2,2) D(2,1) C(1,3)

E(2,2) D(2,1) F(2,3) 3x3 H(3,2) A(1,1) L(3,3)

H(3,2) G(3,1) L(3,3) B(1,2) G(3,1) F(2,3)

( i, j ) — data on input i at time slot j

Time Slot 1 Time Slot 2 Time Slot 3

Fig. 2.21. Input-output mapping changes from slot to slot in

space-division switch in time-space-time switching

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 These lines correspond to time slot 1
A(1,1) D(2,1)
B(1,2) E(2,2)
C(1,3) C(1,3)
(1) (1) (1)
D(2,1) A(1,1)
E(2,2) H(3,2)
F(2,3) L(3,3)
(2) (2) (2)
G(3,1) G(3,1)
H(3,2) B(1,2)
L(3,3) F(2,3)
(3) (3) (3)

Module (i) corresponds Module (i) corresponds Module (i) corresponds

to input TSI (i) in to time slot i of to output TSI (i) in
time-space-time switch space-division switch in time-space-time switch
time-space-time switch

Fig. 2.22. Equivalent of time-space-time switching and

three-stage space switching
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~END~