Ms.

Poonam Rana
Sr. Assistant Professor
ABES Engineering College, Ghaziabad
General Register Organization

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In this lecture Students will be
able to learn :
 Major Components of CPU
 Bus Organization for seven CPU Registers
 Control Word
 Fields in Control Word
 Encoding of Register Selection Fields
 Encoding of ALU Operations
 Examples of Micro-operations
 Examples of Micro-operations on the CPU

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Major Components of CPU:
 The part of the Computer System that performs the
bulk of data processing operations is called Central
Processing Unit and is referred to as CPU.
 The CPU is made up of major 3 parts:
1.Control
2. Register Set
3. Arithmetic Logic Unit.

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Major Components of CPU Diagram

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Functions of Major Components of CPU:

 The Register set stores intermediate data used during the

execution of the instructions.
 The Arithmetic logic Unit performs the required micro-
operations for executing the instructions.
 The Control unit supervises the transfer of information
among the registers and instructs the ALU as to which
operation to perform.

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Organization and Architecture of the CPU:

 This lecture describes the organization and Architecture of

the CPU with an emphasis on the user's view of the
Computer.
 In this we briefly describe how the registers communicate
with the ALU through buses .

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General Register Organization
 We know that memory locations are needed for storing
pointers , counters, return addresses, temporary results and
partial products during Multiplication.
 Having to refer to memory locations for such applications is
time consuming because Memory access is the most time
consuming operation in a computer.
 It is more convenient and more efficient to store these
intermediate values in processor registers.
 When the large number of registers is included in the CPU it
is most efficient to connect them through a common bus
system.

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General Register Organization:

 The registers communicate with each other

not only for direct data transfers but also
while performing various micro-operations.
 Hence it is necessary to provide a common
unit that perform all the arithmetic , logic and
shift micro-operations in the processor.

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Bus Organization for 7 CPU registers:

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General Register Organization
Description:
 The output of each register is connected to two
multiplexers (MUX) to form the two buses A& B.

 The selection lines in each Multiplexer select one

register or the input data for the particular bus

 The A & B buses form the inputs to a common

arithmetic logic Unit( ALU).

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General Register Organization:
 The operation selected in the ALU determines the arithmetic
or logic operation that is to be performed.

 The result of the micro-operation is available for output data

and also goes into the inputs of all registers.

 The register that receives the information from the output

bus is selected by decoder.

 The decoder activates one of the register load inputs , thus

providing a transfer path between the data in the output bus
and the inputs of the selected Destination register.
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General Register Organization
 The control unit that operates the CPU bus System directs
the information flow through the registers and ALU by
selecting the various components in the System. For
Example , to perform the operation.

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Example of General Register
Organization
 R1<-R2+R3
 To Perform this operation the control unit must provide
binary variables to the following selector inputs.
 a) MUX A Selector A ( SEL A) : To place the contents of R2
into BUS A.
 b) MUX B Selector B(SEL B) : To place the contents of R3
INTO BUS B.
 c) ALU operation selector OPR to provide the arithmetic
addition.
 d) Decoder destination selector (SELD) to transfer the
content of output bus into R1.

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Control Word

 1. SEL A Consists of 3 bits.

 2. SEL B Consists of 3 bits.

SEL A SEL B SEL D OPR

 SEL D consists of 3 bits.

 OPR consists of 5 bits.

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Control word

 There are 14 binary selection inputs in the unit, and their

combined value specifies a control word. The 14 bit control
word is defined in the previous figure.
 Three fields contain three bits each and one field has five
bits.
 The three bits of SEL A select a source register for the A input
of the ALU.
 The three bits of SEL B selects a source register for the B
input of the ALU.
 The three bits of SEL D select a destination register using the
decoder and its seven load inputs.
 The five bits of OPR selects one of the operations in the ALU.
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Encoding of Register Selection
fields:
Binary code SELA SEL B SEL D
000 Input Input None
001 R1 R1 R1
010 R2 R2 R2

011 R3 R3 R3

100 R4 R4 R4

101 R5 R5 R5
110 R6 R6 R6

111 R7 R7 R7

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Encoding of ALU operations:
OPR select Operation Symbol
00000 Transfer A TSFA
00001 Increment A INCA
00010 Add A+B ADD
00101 Subtract A-B SUB

00110 Decrement A DECA

01000 And A and B AND
01010 OR A and B OR
01100 XOR A and B XOR
01110 Complement A COMA
10000 Shift Right A SHRA
11000 Shift Left A SHLA

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Examples of Micro-operations:

 R1<-R2-R3

 Control word: 010 011 001 00101 for the

above micro operation .

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Morris Mano Unsolved
Numerical:
 A bus organized CPU has 16 registers with 32
bits in each, an ALU and a decoder.
 a) How many multiplexers are there in the A
bus and What is the size of each Multiplexer?
 b) How many selection inputs are needed for
MUX A and MUX B?
 c) How many inputs and outputs are there in
the ALU for data, including input and output
carries?
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Morris Mano Unsolved
Numerical
 How many inputs and outputs are there in
the decoder?
 Formulate a control word for the system
assuming that the ALU has 35 operations.

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 32 multiplexers, each of size 16 × 1.
 (b) 4 inputs each, to select one of 16
registers.
 (c) 4-to-16 – line decoder
 (d) 32 + 32 + 1 = 65 data input lines
32 + 1 = 33 data output lines.
 (e) 4 + 4+ 4 + 6 = 18 bits

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