FPGA Implementation Of

Direct Sequence Spread

Spectrum (DSSS)

Stage 1 Thesis Presentation

Guide: Prof. Rahul Dubey

Presentated By:
Examiners: Prof. Deepak Ghodgaonkar Vivek Kr.
Choudhary
Prof. M. V. Joshi
[200611029]

23 Nov' 2007 DA-IICT 1

Outline of the Presentation
Introduction
Literature survey
Complexity of Algorithms
Problem Definition
Progress on Problems
Future Plans
References
23 Nov' 2007 DA-IICT 2
 Introduction of DSSS
 Direct Sequence Spread Spectrum (DSSS) CDMA
is the method used in IS-95 commercial systems.
 A spread spectrum is a technique in which the
bandwidth of a signal is increased by artificially
increasing the bit data rate.
 This is done by breaking each bit into a number of
sub-bits called “chips.”
 Narrow band input from a user is coded (“spread”)
by a user-unique broadband code, then transmitted.
 Broadband signal is received: receiver knows,
applies user’s code , recovers users’ data.
 Generation of DS-CDMA

23 Nov' 2007 DA-IICT 4

 Direct Sequence
CDMA

Fig: The baseband model of a DS-CDMA

transceiver
23 Nov' 2007 DA-IICT 5
 Advantages over a fixed-
frequency transmission

 Secure data communications.

 Military influenced Anti-jamming capabilities.
 Multiple access capabilities.
1. Spread-spectrum
interference
signals are highly resistant to noise and

 Spread spectrum signal are highly resistant to

noise and interference.

23 Nov' 2007 DA-IICT 6

 Problem Definition

 Linear Feedback Shift Register (LFSR)

implementation for long PN-sequence generation.
 Synchronization of PN-sequence between transmitter
and receiver.
 Error correction and detection of data bits .
 Problem Definition
 Digital-Bit errors caused by
a) Attenuation and attenuation distortion
b) Delay distortion
c) Noise
 Single bit error detection is possible but not
correction, so retransmission will take place .
 But Hamming Algorithm can detect and correct
both , so no need of retransmission which is
necessary for high speed wireless communication.
23 Nov' 2007 DA-IICT 8
 Literature Survey
Din
4x 1
Synchronous Dout
RAM

4x 1
Synchronous
RAM

D Q D Q D Q D Q
Control Logic

 LFSR implementation of
synchronous RAM
 Error Detection and

Correction
Error detection is the ability to detect errors.
 Error correction has an additional feature that
enables identification and correction of the errors.
 Error detection always precedes error correction.
 Both can be achieved by having extra or redundant
or check bits in addition to data deduce that there is
an error
Original Data is encoded with the redundant bit(s)
New data formed is known as code word
 Hamming Algorithm
 In 1950, R.W. Hamming described a general method for
constructing code with minimum distance of 3 ,now
called Hamming Code.
 (n,k) Hamming codes. Minimum distance always 3. Thus
can detect 2 errors and correct one error. n=2^m-1,
k = n - m, m≥3 .
 Maximum-length codes. For every k≥3 integer there
exists a maximum length code (n,k) with n = 2k – 1,
dmin = 2k-1.
Position of redundancy
bit’s in hamming code

d d d r8 d d d r4 d r2 r1
11 10 9 8 7 6 5 4 3 2 1

r bit’s is the parity bit for one combination of data bit’s

r1: bit’s 1 , 3 , 5 , 7 , 9 ,11

r2: bit’s 2 , 3 , 6 , 7 , 10 ,11

r4: bit’s 4 , 5 , 6 , 7

r8: bit’s 8 , 9 , 10 , 11
Example of redundancy bit
calculation
Error detection using
hamming code
Hamming Algorithm

Fig: Technology schematic 15

RTL Schematic for
hamming code
generation

16
Technology Schematic
Test Bench Waveform
Simulation Results (4 Bit-data
input)
Number of Slices: 2 out of 3584 0%

Number of 4 input 3 out of 7168 0%

LUTs:

Number of IOs: 11

Number of bonded 11 out of 141 7%

IOBs:

Delay: 7.850ns (Levels of Logic =3)

 Future Plans
 Implementation of Hamming code logic in
Wide band CDMA.
 Implementation by Viterbi Algorithm because it’s
work at receiving end.
 References
[1] Predrag Markovic, Milan Markovic, FPGA/VLSI Implementation Analysis of
PN Sequence Generator for Direct Sequence Spread Spectrum Systems. IEEE
conference, Nis, Yugoslavia,13-15 October 1999.
[2] Sunil Shukla, Neil W. Bergmann, SINGLE Bit Error Correction Implementation in
CRC-16 on FPGA. IEEE conference, 6-8 Dec. 2004.
[3] Behrouz A. Forouzan. Data Communications and Networking. McGraw-Hill 3rd edition,
1 Nov. 1994, pp. 257-259.
[4] Bob Zeidman. Verilog Designer’s Library. Prentice Hall Modern Semiconductor
Design Series, pp. 237-259.
[5] K.H. Tsoi, K.H. leung and P.H.W. Leong, Compact FPGA –based True and Pseudo random
Number Generators. . IEEE conference, 9-11 April 2003.
[6] Taub.Schilling . Principles of Communication System. TATA M cGRAW-HILL EDITION,
2nd edition, pp 720-751.
 Thank You!

23 Nov' 2007 DA-IICT 22

Frequency Hopping
Frequency Hopping
 IS-95 is a standard for CDMA
(Code Division Multiple Access) Digital Cellular.

MobileFrequency Range Rx: 869-894; Tx : 824-849

Multiple Access Method CDMA/FDM

Duplex Method FDD

Number of Channels 20 (798 users per channel)

Channel Spacing 1250kHz

Modulation QPSK/OQPSK

Channel Bit Rate 1.2288Mb