Delay Test

Nitish Sharma - MT2023501

Shreyas R - MS2023013

16/05/2024
 CONTENTS
● Introduction and Delay Fault Models
● Path Delay Fault
○ Path Sensitization
○ Test Generation
● Transition Delay Fault
○ Fault Simulation
○ Test Generation
● Conclusion

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 INTRODUCTION AND MOTIVATION
● Hardware manufacturing Defects affects the functionality or timing of a circuit. Conventionally, if the
defect alter the functionality, these faults can be modelled as Stuck-at Faults.
● Some defects alter the circuit timing and are categorized as delay faults.
● Examples for the sources of delay faults:
○ Random Defects: Resistive opens, resistive bridging etc.
○ Systematic Defects: Crosstalk, Process variation in Vt(threshold voltage)
● As the operating frequency of circuits becomes faster, delay tests are most important.
○ 100ps of delay in 100MHz clock(1%) is insignificant when compared to 100ps in 1GHz
clock(10%).

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 DELAY FAULT MODELS
● To detect delay faults, it requires two-pattern test contrary to the stuck-at faults.
○ V1: initialize circuit elements. V2 - launch transition and propagate fault effect to output.
● Path Delay Fault(PDF): Path delay of the faulty path > clock period.
● Transition Delay Fault(TDF): Path delay of all paths through the fault > clock period.

● Fault Distributed with small delay.

● Example: Good gate Delay: 2ns. Gates Marked with X: 2.5ns ~ 3.0ns.
● Worst Case: exponential faults, depends on path list
● Two path delay faults for each path. Rising(↑) and Falling(↓)

● Lumped Fault with large delay.

● Example: Good gate Delay: 2ns. Gates Marked with X: 8ns ~ 9ns.
● Worst Case: Linear number of faults; depends on number of gates.
● Two transition delay faults on each node: Slow-to-rise(STR) and Slow-to-
fall(STF)

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 PATH DELAY FAULT SENSITIZATION
● A path is a serial connection of combinational gates. A path is testable if a transitions can propagate
along the path under certain sensitization condition.
● For a given target path, all the signals on the path are called on-path(on-input) signals and all the
signals which are not part of the path but feed the gates in the path are called off-path(off-input)
signals.
● Since, path delay test requires 2-pattern test, we need to represent the 2 values in a logic system.
● A path is statically sensitizable iff all the off-inputs have NC values.

S0: static 0; 0→0

S1: static 1; 1→1

U0: X→0

U1: X→1

XX: X→X

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 NON-ROBUST AND ROBUST PATH SENSITIZATION

● Non-Robust Sensitization Criteria: All off-
inputs can have X→NC
● Pros: Easy to find more tests for detecting
PDFs
● Cons: Non-Robust Test can be invalidated if
there are other path delay faults.
● Robust Sensitization Criteria: All off-inputs
must have NC→NC
● Pros: Effective even when there are multiple
PDFs
● Cons: Less number of test vectors that can be
generated when compared with Non-Robust
sensitization.

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 PATH DELAY FAULT TEST GENERATION

● Non-Robust:
● Place a transition on B (U0/F)
● Propagate F to signal E: C = U0 → E = F
● Imply → G = U0/F, J = U1/R, Q = U0/F.
● Propagate R on J to signal K → Justify H = U0
● Imply → A = XX since Q = U0/F
● Therefore A = XX, B = U0/F, C = U0
● Robust:
● Place a transition on B (U0/F)
● Propagate F to signal E: Justify E = U0/F
● Imply → C0 = U0, G = U0/F, J = U1/R, Q = U0/F.
● Propagate R on J to signal K → Justify H = S0
● Imply → A = S0 since Q = U0/F
● Therefore A = S0, B = U0/F, C = U0

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 Transition Delay Fault Detection

● Transition Delay Fault assumes a large delay fault at a particular gate in the netlist.

● To detect a transition delay fault two vectors are required. One vector sets the fault site
to the initial value required for the corresponding transition and other vector causes the
transition at the fault site activating the fault.

● Transition faults are similar to single stuck at faults so they are ATPG friendly as they
can use ATPG algorithms developed for SSFs .

● Transition faults like SSFs are of two types Slow to rise(STR) and Slow to Fall(STF).

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 Transition Delay Fault Detection

● Following truth table illustrates denotes the set of vectors {V1,V2} which can detect
various faults at terminals of an AND gate:

Vector 1(A B) Vector 2(A B) Fault Detected

0x 11 A STR

1x 01 A STF

x0 11 B STR

x1 10 B STF

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 Transition Delay Fault Simulation

● Transition delay fault simulation can be built on SSF simulation

I. Just add additional check for V1
II. V2 is same as SSF simulation
●
Example: V1 ABC = 010, V2 ABC =000
I. V2 detects B SA1, C SA1, E SA1,
G SA1, J SA0, K SA0
II. {V1, V2 } Detected transition faults
III. B STF, E STF, G, STF, J STR, K STR
IV. C STF not detected because no transition
V. Q STF not detected because Q SA1 not detected by V2

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 TDF Test Generation

● First SSF for V2, then control V1.

● Example: use PODEM for G slow-to-fall (STF)
I. V2 objective: detect G stuck-at 1 → B2=0
II. V2 objective: detect G stuck-at 1 → C2=0,
V2 generated
III. V1 objective: G = 1→ B1=1
IV. Test generated: V1 ABC = X1X, V2 ABC =X00

Generate V2 then V1

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 Conclusion

● Transition Fault model are less complex for ATPG compared to Path Delay Test.

● Transition Faults are a must do for Delay fault ATPG.

● Some Critical paths should be preferred for the Path Delay ATPG.

● Also multicycle paths should be considered for Path Delay ATPG.

● If there are too many paths random test patterns can be used initially. If they are not testable
Increase sample size or reduce threshold.

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 References

● VLSI Test Principles And Architecture - For DFT, L.T. Wang, C. W. Wu and X. Wen, Morgan
Kaufman

● Essentials of Electronic Testing For Digital, Memory and Mixed-Signal VLSI Circuits - Bushnell &
Agrawal

● NTU, VLSI Design Testing

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 THANK YOU

16/05/2024