Lane 1

R1

Y1

G1

Lane 2

G2 Y2 R2
 (reset state)
S1
R1 = 1 R2 = 0
Y1 = 0 Y2 = 0
w = 1, 0 G1 = 0 G2 = 1 w = 1, 0

S6 S2
R1 = 1 R2 = 1 w = 1 R1 = 1 R2 = 0
Y1 = 0 Y2 = 0 Y1 = 0 Y2 = 1
G1 = 0 G2 = 0 w = 1 G1 = 0 G2 = 0

w = 0 w = 0
S5 S3
R1 = 0 R2 = 1 R1 = 1 R2 = 1
Y1 = 1 Y2 = 0 Y1 = 0 Y2 = 0
G1 = 0 G2 = 0 G1 = 0 G2 = 0
S4
w = 1, 0 R1 = 0 R2 = 1 w = 0
Y1 = 0 Y2 = 0
G1 = 1 G2 = 0
 Next State Output
Present State
w = 0 w = 1 R1 Y1 G1 R2 Y2 G2 States
XX 0 0 0 0 X X X
S1 S2 S2 1 0 0 0 0 1 XX 0 0 0 1 X X X
S2 S3 S4 1 0 0 0 1 0 1 0 0 1 0 0 1 1
2 0 0 1 1 1 0 0
S3 S4 S3 1 0 0 1 0 0 3 0 1 0 0 1 0 1
S4 S5 S5 0 0 1 1 0 0 4 0 1 0 1 1 1 0
5 0 1 1 0 1 1 1
S5 S6 S1 0 1 0 1 0 0 6 0 1 1 1 0 1 0
XX 1 0 0 0 X X X
S6 S1 S1 1 0 0 1 0 0 XX 1 0 0 1 X X X
1 1 0 1 0 0 1 1
2 1 0 1 1 1 0 1
3 1 1 0 0 X X X
4 1 1 0 1 1 1 0
5 1 1 1 0 0 1 0
6 1 1 1 1 X X X
 h1

w 𝐻1 R1
Combinational Combinational Y1
circuit 𝐻2 h2 circuit G1
R2
𝐻3 Y2
G2
h3

Clock
w

𝐻1 h1 R1

Y1
𝐻2 h2
G1

R2
𝐻3 h3
Y2

G2

Clock
w

𝐻1 h1 R1
𝐷

Y1
𝐻2 h2
𝐷 G1

R2
𝐻3 h3
𝐷 Y2

G2

Clock
w = 0

Clock

h1

h2

h3

𝐻1

𝐻2

𝐻3
w = 1

Clock

h1

h2

h3