555 TIMER IC

BLOCK DIAGRAM, PIN DIAGRAM, OPERATIONS IN

ASTABLE AND MONOSTABLE MODE, APPLICATIONS
555 TIMER IC PIN DIAGRAM
555 TIMER IC BLOCK DIAGRAM
BLOCKS
Voltage divider block
Comparator block
Flip flop block
Discharge block
Output block
 BLOCKS
 The block diagram of 555 timer IC showcases
number of blocks carrying of various
operations. The Voltage divider circuit plays a
crucial role in setting the reference voltage for
the comparators. The three resistors in the
voltage divider circuit are always equal.
Consider the comparator op-amp is ideal thus
no current flows through it. The reference
voltage of the two comparators can be
calculated as;
 PINS
 Depending upon the threshold and trigger pulse the comparators will provide either ‘0’ or ‘1’ as
the outputs. They are the inputs S and R to the SR flip flop. Thus depending upon the comparator
output the output of the IC is determined.
 The reset pin in the flip flop block resets the flip flop when it is applied a logic ‘0’. So usually the
reset pin is connected to the supply voltage Vcc.
 The control pin is connected to the inverting terminal of the first comparator which is useful to
change the timing of the output when voltage is applied.
 The discharge pin consists of a transistor which helps in discharging the capacitor when the IC
output is low.
OPERATION
 When the threshold voltage is greater than
the reference voltage(Vr1= 2/3Vcc), the
comparator 1 gives a +ve output whose logic
is 1.
Likely when the trigger is less than 1/3Vcc ,
the second comparator gives an output 1.
 Depending upon the comparators’ output,
the system provides an output which is either
‘0’ or ‘1’
555 TIMER IN ASTABLE MODE
BLOCK DIAGRAM
GRAPH
DUTY CYCLE
Consider charging time as t1 and discharging time as t2. Hence,
t1 = 0.693(R1+R2)C;
t2 = 0.693(R2)C;
Hence the duty cycle is given by,
Duty cycle = t1/(t1+t2);
= (R1+R2)/(R1+2R2);
From the above equation, one can say that the duty cycle for astable mode is always >50%.
To get a 50% duty cycle we could simply eliminate the resistor R1. But by doing this the internal
transistor is directly exposed to the supply Vcc which may lead to damage. Another method is to
connect a diode D parallel to the resistor R2.
50% DUTY CYCLE
555 TIMER IN MONOSTABLE
MODE
BLOCK DIAGAM
GRAPH
APPLICATIONS
GENERATING TIME DELAY
FREQUENCY DIVISION
PULSE WIDTH MODULATION