PDP Training

(Alexander)
 Agenda

1.Explanation of Layout and

Function of Circuit Board

2.Operation Explanation per Board

2-1 Drive Description on SMPS
2-2 Operation Explanation of Driving
Circuit
2-3 Logic-Main Board
2-4 Scaler Board
1. Explanation of Layout & Function of Circuit Board
[ PDP Module Pic ture ]

Y buffer "Upper"

SMPS
Y- MAIN X- MAIN

Logic- Main

E- buffer F- buffer G- buffer

Y buffer
"Lower" COF x 7
 [ Function Description by board -
1]
■.SMPS(Switching Mode Power Supply)
: It is the supplier to provide voltage and current to work the drive voltage and panel in each board.

■.X-MAIN BOARD
: It makes the drive wave form by switching FETs to Timing Controlle coming from logic-board and
supplies X electrode of panel with the drive wave form via connector.

■.Y-MAIN BOARD
: It makes the drive wave form by switching FETs to Timing Controller coming from the logic-board and
provides Y electrode of panel with the drive wave form via Scan Driver IC on Y buffer board in order.

■.LOGIC MAIN BOARD

: It process image signal and performs buffering of the logic-main board (to create XY drive signal and
output) and the address driver output signal.
Then it supplies the output signal to the address driver IC(COF Module).
 [ Function Description by board - 2 ]
■.LOGIC BUFFER(E,F,G) : It delivers the data signal and control signal to the COF.

■.Y-BUFFER (Upper,Lower)
: It is the board to impress the scan waveform on the Y board and consist of 2 boards
(upper board and lower board).
8 Y-buffers are fixed at the scan driver (STV7617 of STC corp. : 64 or 65 Output).

■.AC Noise Filter

: It has functions to remove noise(low frequency) coming from AC LINE and prevent surge.
It gives serious effects on the safety regulations (EMC, EMI) according to AC filter.

■.COF(Chip on Flexible)
: It impress the Va pulse to the address electrode in the address section and forms the address
discharge by electric potential difference with scanning pulse to be dismissed by the Y electrode.
It is made in the form of COF and one COF consists of 4 Data Drive IC (STV7610A :96 Output),
otherwise single scan is made of 7 COF.
 CELL STRUCTURE OF PDP

Bus electrode Front panel

Dielectric
MgO layer ITO electrode
Barrier Phosphors

Address Back panel

Electrode
 Electro Arrangement of SD PDP
A1 A2 A3 A4 A5 A6 A7
∼
Y1

Y2

∫ ∼

Y480

Reference
- A1,A2, , , : Address Electrode
- Y1,Y2, , , : Scan & Sustain Electrode
- X : Common & Sustain Electrode
ADDRESS OPERATION

In
Inorder
orderto
todisplay
displaypicture,
picture,
select
selectthe
thecells.
cells.
SUSTAIN OPERATION

Display
Displaycells
cellsthrough
throughstrong
strong
Sustain
Sustaindischarge.
discharge.
 1 SUB-FIELD IMAGE PROCESS (ADS)

Reset Address Sustain

Function
Function Function
Function Function
Function
••Sustain
SustainErase
Erase ••Select
SelectOn
OnCell
Cell ••Discharge
DischargeOn
OnCell
Cell
••Wall
WallCharge
ChargeSet
Set
Issue
Issue Issue
Issue
Issue
Issue ••High
HighSpeed
Speed ••High
HighEfficiency
Efficiency
••Operation
Operationmargin
margin ••Low
LowVoltage
Voltage ••Low
LowVoltage
Voltage
••Contrast
Contrast ••Low
LowFailure
Failure ••ERC
ERCPerformance
Performance
••Short
ShortTime
Time
 FRAME STRUCTURE (ADS)

SF1 SF2 SF3 SF4 SF5 SF6 SF7 SF8

sub-field
1
2 address
..
...
scan line

1T 2T 4T 8T 16T 32T 64T 128T

sustain
480
1TV field (time)

Reset Address Sustain

Period Period Period

D
X
Y1
Y2
Yn
 1 Picture Structure by 8 sub-field

e
ag
Im
nal
i
SF1 SF2 SF3 SF4 SF5 SF6 SF7 SF8 rig
O
sub-field
1
2 address
..
...
scan line

1T 2T 4T 8T 16T 32T 64T 128T

sustain
480
1TV field (time)
2. Explanation of Operation per Boards
[ Whole Bloc k Diagram]
Y- Ma in B' d
X- Ma in B' d
Lo g ic B' d Dis p la y
Da ta
Ro w PDP Pa ne l
Drive r
DRAM Drive r 852 X 4 80 Pixe ls X- Puls e
Timing 853 X 3 X 480 Ce lls Ge ne ra to r
Inp ut Da ta Y- Puls e
Co ntro lle r Drive r
Da ta Ge ne ra to r
Timing Sc a n
Pro c e s s o r
Co ntro lle r Timing
Co lumn Drive r
Clo c k :
Clo c k : Clo c k : 20MHz Po we r B' d
27MHz 60MHz 40MHz

Po we r Sup p ly

LVDS
Dig ita l B' d Ana lo g B' d

Ima g e De - Aud io
Pro c e s s o r AC Po we r
Enha nc e r inte rla c e r
Ima g e Vid e o So urc e
Vid e o Tune r
Sc a le rr De c o d e r S/ W 220V

AD TMDS Co mb
Mic o m Filte r
Co nve rte rr Re c e ive rr
1 Picture Structure by 8 sub-field
[ Wiring Diagram Schematic]

CN805 CN805
(10 P) (10 P) CN804 CN804
SMPS (9P) (9P)
CN806)
CN812
(5P)
CN802 CN803 CN801
(11 P) (10 P) (10 P) X- Main
Y- Main

LA03 CN803
(31 P) (10 P)

CN201 CN201 Log ic CN101 CN101

CN401 CN402 CN403

CN806) EF1 FE1 FG1 GF1

CN101 AC
CN111 CN601 CN802 CN801
Inle t
CN102
Digital Analog
CN103
 PIN CONFIGURATION
[ Sc ale r : Analog ↔ Dgital ] [ Sc ale r Dgital ↔ Log ic (CN601) ]
CN101(Co ntro l) CN102(Vid e o / Sync ) CN103(Vid e o / Sync ) NO PIN Na me NO PIN Na me

NO PIN Na me NO PIN Na me NO PIN Na me 1 GND 16 Tx CLK Out+ / Rx CLK In+

2 GND 17 GND
1 GND 1 ANAL_YCOMB 1 ANAL_YCOMB
3 Tx Out0- / Rx In0- 18 GND
2 SCL1 2 GND 2 GND
4 Tx Out0+ / Rx In0+ 19 Tx Out0- / Rx In0-
3 SDA1 3 ANAL_CCOMB 3 ANAL_CCOMB 5 GND 20 Tx Out0- / Rx In0-
4 GND 4 GND 4 GND 6 GND 21 GND

5 SAFT 5 ANAL_Y2 7 Tx Out1- / Rx In1- 22 GND

5 ANAL_Y2
8 Tx Out1+ / Rx In1+ 23 GND
6 GND 6 GND 6 GND
9 GND 24 GND
7 MUTE 7 ANAL_PB2 7 ANAL_PB2 10 GND 25 RESET_MN
8 GND 8 GND 8 GND 11 Tx Out2- / Rx In2- 26 GND
9 MAFT 9 ANAL_PR2 9 ANAL_PR2 12 Tx Out2+ / Rx In2+ 27 IIC SCL2

10 GND 10 GND 13 GND 28 GND

10 GND
14 GND 29 IIC SDA2
11 ANAL_CVBS 11 ANAL_H 11 ANAL_H
15 Tx CLK Out- / Rx CLK In- 30 GND
12 GND 12 ANAL_V 12 ANAL_V 31 GND
 PIN CONFIGURATION
[ SMPS ↔ Analog / Digital / Log ic ] [ SMPS ↔ X,Y- Main / Buffe r ]
CN801(An a lo g Tu) CN802(Dig ita l Tu) CN803(Lo g ic ) CN804(X- Ma in) CN805(Y- Ma in) CN806/ 812(Buffe r)
NO Po we r NO Po we r NO Po we r NO Po we r NO Po we r NO Po we r
1 GND 1 THEM_D 1 D3. 3V 1 D5V 1 D5V 1 Va
2 A33V 2 STD_5V 2 D3. 3V 2 VG 2 VG 2 Va
3 GND 3 GND 3 GND 3 GND 3 GND 3 N. C.
4 GND 4 PS_ON 4 GND 4 GND 4 Vs c an 4 GND
5 AMP12V 5 N. C. 5 D5V 5 VE 5 GND 5 GND
6 AMP12V 6 GND 6 GND 6 GND 6 Vs e t
7 GND 7 GND 7 IC2 7 GND 7 GND
8 D12V 8 D3. 3V 8 IC2 8 VS 8 GND
9 GND 9 D3. 3V 9 PS_ON 9 VS 9 VS
10 D6V 10 GND 10 GND 10 VS
11 D6V

[ FAN B+:For VMB]

CN807/ 811(FAN)
NO Po we r
1 12V
2 GND
5 Fan_D
 2-1. Drive Description on SMPS
[ S MPS Blo c k Diag ra m]
Vs(+85V)
HOT COLD
DC/DC
AC input Converter Vset (+95V)
385Vdc bus
90V∼264V
DC/DC
Converter Ve (+110V)
Boost PFC Vs_Switching
EMI
Stage Stage
FILTER

NOISE Return
FILTER
PWM control
Stage DC/DC Vscan (+78V)
Converter

Va_Switching Va(+79V)
Stage Return
Auxiliary
Stage
Vcc PWM control
Stage

VT(+33V 0.03A)

12V(+12V 0.7A)
Stand_By 5V A12V(+12V)
V_digital D5V (+5V))
Chopper REG
V_analog
PS-ON/Relay Signal Return
Switching Stage
MAG-AMP D3.3V (+3.3V)
Vs Logic_ON
Reg. Vg (+15V)
Active_High
12V Amp(+12v)
A6V(+6V)

PWM control D6V(+6V)

Stage
COLD HOT COLD
 Operation Description on SMPS
1. Overview
SMPS used in PDP 42" developed into the compact-sized with high efficiency.
The asymmetrical half bridge and the flyback converter are applied into all output. To comply with the
harmonic restrictions, it takes the power factor improvementcircuit, which converts AC into the high DC
and uses as the input of another converter controller.

2. Input controller
SMPS works in whole section of AC 90~264V. It is possible to start in the AC 90 and can restart with new
input voltage, even in interruption of electric power. STD_5V comes out when AC is impressed

3. Output Controller
Given SMPS have 15 output voltages. The following shows the specification of output voltage and output
current in case of their successive drive.
 Operation Description on SMPS
Name Voltage Current(Max.) Using in PDP Driving Name Voltage Current(Max.) Using in PDP Driving

A12V +12V 0.3A

VS +75V ~ 100V 4.5A Sustain Voltage
D6V +6V 0.1A
VA +65V ~ 80V 0.6A Address Voltage
A6V +6V 0.1A
VSCAN +65V ~ 100V 0.1A
D5V +5V 1.0A IC Driving Voltage of Logic
VSET +80V ~ 100V 0.1A D3.3V +3.3V 4.5A

VE +100V ~ 120V 0.1A 12VAMP +12V 1.7A Amp Voltage of Audio

VT +33V 0.003A
VG +15V 1.5A Driving Voltage of Fet
Standby for Remote
D12V +12V 0.1A STD_5V +5V 0.6A
Control

3-1. Overvoltage protection

It has circuit to maintain normal voltage, additionally with circuit for sensing overvoltage, so it means any
overvoltage does not give impacts on other output controller. SMPS prevents overvoltage in the latch mode.
VS(85V) works protection function more than 100V, over 94V for VA(75V), over 8.2V for D6V,
over 4.7V for D3.3V
 Operation Description on SMPS
3-2. Short circuit and overvoltage protection
It forms definition that in the short circuit of output controller the output impedance is lower than 300mohm.
If the VS output have a short circuit in case of given SMPS, SMPS stops its working.
Even in the case of short circuit between main output and STD_5V, SMPS does not break down.
When the short circuit is removed, it restarts.

4. Detail Description
① AC-DC Converter
It converts AC into DC by using the power factor improvementcircuit. This converter was designated to
control the high frequency noise, with the function to improve the power factor. This part becomes input
controller of another constant-voltage.

[ PFC Drive FET(SPW47N60) Gate Pulse ]

[ PFC Drive FET(SPW47N60) Drain Pulse ]
 Operation Description on SMPS
② Auxiliary Power
It is the part to supply power of mycom for remote control. When the power is on, it will work,
which means that MICOM is on standby.
This output part is stand_by voltage. When the power-on signal from remote control impress,
it works main power panel of SMPS via stand_by voltage.

③ Configuration of VS output
Major part of PDF SMPS outputs 85V 5A. It takes asymmetrical half bridge converter and connects
2 converters with 85V output in parallel, which increases efficiency than one 85V converter,
on the other hand, decreases its size.

[ Driving FET(2SK2372) Drain Pulse&Current wave. ] [ Driving FET(2SK2372) Gate Pulse ]

 Operation Description on SMPS
- PWM Part
It uses PWM part of ML4824, but there are some points to take cautions. As this part is synchronized with
the PFC part, PWM wave in the current mode drive is induced via the current sensor resistance or current
transformer, and shows the current flowing in the output controller.

④ DC-DC Converter : Input of VSCAN, VSET and VE belongs to the VS part

[ VE Pulse ] [ Vscan Pulse ]

[ VSET Pulse ]
 Operation Description on SMPS
⑤ Output (VA,Multi Outputs) Pulse

[ Va Main Pulse ] [ Multi Outputs Main Pulse ]

 Trouble shooting on SMPS
Po we r ON
Che c k c o rd c o nne c tio n

OK

NG
STB_5V Check the IC2,D28

OK

PFC Check the IC1,Q1,Q2

OK OK

NG
PFC Check the IC35

NG
PFC Check the IC7
 Trouble shooting on SMPS

NG
VS Check the Q6,Q8

OK

Vs c an
Check the IC16, IC17, IC18
VE,Vs e t

OK

Check the Other board ( Image Board or Driver Board ) or Cable.

 2-2. Operation Explanation of Driving Circuit
1. Overview of Driver Circuit
1) Definition of Driver Circuit
The driver circuit division drives the panel with the proper wave form (high voltage pulse) to develop image on
the outside terminal division (X electrode group, Y electrode group, Address electrode).
High voltage switching pulse is made by MOSFET combination.

2) Working Principle of Driver Circuit

To develop image on the PDP, the voltage should be impressed into the X, Y and ADDRESS electrodes
(which are component of each pictorial element) under the proper conditions. The driver wave form which is
currently applied to is ADS (Address & Display Separate: Driving method to work by dividing address and
constant-current section ) Based on this method, the discharge to be done in the pictorial element of PDP
can be divided into 3 types as follows.

● Address Discharge: to form the wall voltage within pictorial element by providing lighting pictorial
element with information(impressing data voltage)
: It is the discharge produced by difference between the positive electric potential of address electrode
(normally, Va impressed voltage of 70~75V +Positive Wall charge) and
negative electric potential of Y electrode
(GND level impression+ Negative Wall charge).
 Operation Description on Driving Board

● Constant-current Discharge: It is the display section to form discharge voluntarily with the help of
wall voltage formed by address discharge. (It makes optical power to create image)
: It is the Self Sustaining Discharge made by combining the electric potential of coherent pulse, normally
160-170Volt, which alternates the X electrode with Y electrode in the sustain section, with the wall voltage
according to the pictorial element condition changed by if the former discharge exists or not. That is to
say,
it works according to Memory characteristic (it means that former working condition defines the
current condition) as the basic feature of AC PDP.

If the wall voltage formerly exists in the pictorial element(i.e., the pictorial element is on), the discharge makes
forms again because the voltage higher than one of the discharging starting time is impressed by
combination
of the wall voltage and of the next impressed constant-current.
While if the wall voltage does not exist in the pictorial element (i.e., the pictorial element is off), the discharge
does not form because the voltage could not reach to the level of the discharging starting time, only with
constant-current.
 Operation Description on Driving Board
● Erasing discharge: To selectively perform the address discharge for respective pixel, pixels of all
panels must be on same conditions (same wall charge state and space charge state).
Therefore the erasing discharge zone is important factor to obtain driving margins.
There are various methods such as application of log waveform but the wall voltage control
method
by the Ramp Waveform is now widely applied.
: The purpose of intialization (Erasing) discharge is to make wall voltage within the the whole of Pixels.
In other words, the erasing discharge must make difference between wall voltages uniform depending
on
whether or not the sustain discharge exists in the previous state. Namely it must remove the wall voltage
formed by the sustain discharge and supply ions or elements by causing discharge for removing the wall
voltage. In the other words, To remove the wall voltage, limit the time when polarity of the wall voltage is
reversely charged by causing discharge or prevent polarity form being reversely charged by supplying
appropriate quantity of ions or elements through forming weak discharge [low voltage of erasing].
There are two types of the weak discharge [low voltage]as known so far. 1) Log Waveform adopted by
the F-company 2) Weak erasing discharge by the Ramp Waveform largely adopted by Matsushita
company, etc. Outside applied voltage is adjusted depending on difference of wall voltage within Pixel,
since discharge is formed when the sumof the existing wall voltage remained and the voltage on a
rising waveform exceed the driving beginning voltage, by slowly applying the
rising slope of the erased waveform for these two methods. In addition,
 Operation Description on Driving Board

3) Essential factors for driving board operation

- Supplied from power board and the optimum value may somewhat differ from
the below cases.

● Vs : 85V - Sustain
● Vset : 60V ~ 70V - Y Rising Ramp
● Ve : 110V - Ve bias
● Vscan : 70V ~ 80V - Scan bias
● Vdd : 3.3V - Logic signal buffer IC
● Vcc : 15V - FET Gate drive IC
● Logic Signal
: Supplied from logic board
: Gate signal of each FET
Driving Waveform Specification Arrangement

Y rising Y sustain
Ramp Pulse

Y falling
Ramp Y scan
Pulse
X sustain
Pulse

Address
Pulse

A1,2..... Address(=Data) Electrode Vs 85V Ve 110V

X Common & Sustain Electrode Vset 95V Va 79V
Y1,2.... Scan & Sustain Electrode Vscan 85V
 Explanation of Function per Pulse

● Y Rising Ramp Pulse

Outside voltage of about 390V~400V is applied to the Y electrode in the Y Rising Ramp zone, and weak
discharge begins if respective gap voltage equals to the discharge beginning voltage.
Negative Wall charges accumulate on the Y electrode and the Positive Wall charges on the X electrode in
the whole while weak discharge is maintained.

● Y Falling Ramp Pulse

Most of Negative Wall charges accumulated on the Y electrode by the X bias of about 200V are used to
remove Positive Wall charges in the Y Falling Ramp zone, and most of Positive charges accumulated on
the (0V) Rising Ramp zone toward the address electrode are maintained, having distribution of wall
charges beneficial for the subsequent address discharge.
 Explanation of Function per Pulse
● Y Scan Pulse
Y scan pulse is called as injection pulse, and selects the Y electrode one by one (Line-at-a-time).
In this case, Vscan is called as Scan bias. For the electrode line with the Vscan voltage applied,
voltage of about 70 Volt (Vscan) is applied, and voltage of 0 Volt(GN0) is applied.
However, since Negative Wall charges accumulate on the Y electrode by the application of Ramp pulse
and Positive Wall charges accumulate on the address electrode, voltage of more than the discharge
beginning voltage is applied to the cell where address pulse(70V~75V) is allotted and thus address
discharge occurs. Address time of the PDP is very long since both scan pulse and data pulse must be
applied in line at a time.

● 1st Sustain Pulse

The Sustain Pulse always begins from the Y electrode, it is because Positive Wall charges are formed on
the Y electrode if address discharge occurs. The wall charges formed by the address discharge are less
than those for the sustain discharge, and thus the strength of the initial discharge is weak.
Sustain discharge usually become stable after 5~6 times of discharge depending on structure of electrode
and environment. Therefore, the initial long sustain pulse is intended to form the initial
discharge stable and form the wall charges much as possible as.
 Trouble shooting on Driving Board
1. Y buffer
- To check whether there is failure of the Y Main, firstly check normal operation of the Y
buffer.
- After separating both the Y Main and the Y buffer connector,
- Check forward voltage drop of 0.4V ~ 0.5V by diode check between OUTL and OUTH.
- In addition, resistance between both ends is also more than several kΩ.

OUTL OUTH

OUTL
OUTH
OUTL

OUTH
 Trouble shooting on Driving Board
2. Y Main
- After connecting both the Y Main and the Y buffer, check that output of one of OUT1~8 of the Y buffer
※ You must check 1EA of Scan pulse is output
is done as follows in application of power

OUT1 OUT2

OUT3
OUT4

OUT6 OUT5
 Trouble shooting on Driving Board
3. X Main
- Check output of the TPOUT on the X board is done as follows in application of power

TPOUT
 2-3. Operation Explanation of Logic Board
[ Lo g ic Blo c k Diag ra m]
Vs Start Logic Power
Image Signal Signal 3.3V,5V

X2000
LA03 CN803
60MHz
U2004 Vs start
IIC 27MHz 28.636MHz X2002 64M 64M
(SCL,SDA) LVDS SW2001 OSC CY2305
SDRAM SDRAM
Image Signal CY2305 U2003 U2014 U2002 U2013 X CONTROL
8 bit per DATA R.G.B
1 bit per H,V SYNC X CONTROL
EP20K400EBC652-1 EPC2 EPC2 EPC2 RESET
U2011 U2007 U2006 SPS10-MEM CN101
Y CONTROL FPGA Circuit
8 bit per DATA R.G.B ASIC
Y CONTROL 1 bit per H,V SYNC
FRONT_XY 1 bit per DATA_EN,TSC,POL,SEN,SDA,SCLK MEMORY
_nRESET
CN201 U2005 CONTROLLER 40MHz
28BV256K CLK_XY(20MHz),SV_SYNC U2000
U2001 X2001
nRESET
IIC
VCC(3.3V)
GND IIC(SCL,SDA)
CN2002
ADRV101~106
ADRV201~206 ADRV501~506
ADRV401~406 ADRV601~606
ADRV301~306 CLK,BLK,POL,STB
CN401 CLK,BLK,POL,STB CN402 ADRV701~706 CN403
CLK,BLK,POL,STB

e-buffer f-buffer g-buffer

 Definition
①
of Name and Terms on Logic Board
⑩
②
⑪
⑥

⑫
LOGIC BOARD
⑤
M O D E L OPTION S/W REMARKS
STATUS
External
④ ON
③ : 2,4 On
42" SD
OFF Internal
1 2 3 4 : 3 On
⑦ ⑧ ⑨
No. Item Explanation
① LVDS connector Connector for receiving RGB, H, V, DATAEN, DCLK encoded in the LVDS from image board.
② LED for operation check LED to show that Sync, clock is normally input into the logic board
③ I2C connector Connector connecting the Key Scan Board that checks and adjusts 256K data
④ 256K Eeprom to save γ table, APC table, driving waveform timing and other option, etc
⑤ Y connector Connector to output control signal of the Y driving board
⑥ X connector Connector to output control signal of the X driving board
⑦ CN401(E-address buffer connector) Connector to output address data, control signal to the E-buffer board
⑧ CN402(F-address buffer connector) Cnnector to output address data, control signal to the F-buffer board
⑨ CN403(G-address buffer] connector) Connector to output address data, control signal to the G-buffer board
⑩ Power connector Connector to receive power 95V] to the logic board
⑪ Power fuse Fuse attached to power [5V] to the logic board
⑫ OPTION S/W Inner/Outer cut-off S/W
 Explanation of Logic Board
Logic board is composed of a logic main board that generates and outputs the address driver output signal
and the XY driving signal by processing image signal, and a buffer board that buffers the address driver
output
signal and delivers it to the address driver IC (COF Module).

Logic Board Function Remarks

- Processes Image signal (W/L, error dispersion, APC)
- Outputs image signal as address driver control signal,
Logic Main
data signal buffer board
- Outputs the XY driving board control signal

- Delivers data signal and control signal to the

E Buffer board
right/right COF

- Delivers data signal and control signal to the

Buffer Board F Buffer boadr
middle/lower COF

- Delivers data signal and control signal to the

G Buffer board
Right/ Lower COF
2-4. Explanation of Scaler(Image Board) Operation
DIGITAL BOARD IC & SIGNAL BLOCK DIAGRAM CRYSTAL ANALOG Signal DIGITAL Signal CLOCK Signal

TO LOGIC FROM SMPS

DS90C385
Z86129
M
2
7
V
1 K4S643232E
VPC3230
6 SNI FLI2200 CVBS
0 K4S643232E

20.25M

K4S641632E
K4S643232E Y/C
K4S643232E
M27V160
ASI500
K4S643232E
14.3181M Y/Pb/Pr/H/V

SDA6000

VPC3230
BA7657 20.25M
AD9883

FROM 6M SiI161A
CONTROL 74HC4052
PCB DVI L/R DVI,D-SUB L/R
S-VHS Y/C
R/G/B/H/V D-SUB L/R S-VHS L/R

RS-232 DVI DVI SOUND D-SUB D-SUB S-VIDEO S-VIDEO/VIDEO Sound

Sound
 Explanation of Scaler(Image Board) Operation
ANALOG BOARD IC & SIGNAL BLOCK DIAGRAM CRYSTAL ANALOG SIGNAL DIGITAL SIGNAL CLOCK SIGNAL

CN801 FROM SMPS

18.432M

Y/C 20M
UPD64083

CN101 SUB WOOPER

CVBS CVBS
DVI,D-SUB L/R MSP3451
L/R
Y/Pb/Pr/H/V S-VHS L/R
CN102 CXA2151
4M

S-CVBS

TEA6425
M-CVBS
Y/Pb/Pr
TUNER 2 TUNER 1
TA1101
BA7657
CN103
VIDEO-CVBS Y/Pb/Pr 1 Y/Pb/Pr 2

VODEO COMPONENT1 COMPONENT1 SOUND COMPONENT2 COMPONENT2 SOUND SOUND OUTPUT RF Sub-woofer
INPUT Output
 Factory Data per each Mode
1. UPD 64083 (COMB FILTER)
ITEM TV/Video/S-Video/Component 1,2(SD) Component 1,2(HD) PC DVI
VAPGAIN 4 4 4 4
VAPINV 16 16 16 16
YPFP 3 3 3 3
YPFG 9 9 9 9

2. VPC 3230(M) : Main VCD

ITEM TV/Video/S-Video/Component 1,2(SD) Component 1,2(HD) PC DVI
CONTRAST 43 43 43 43
BRIGHTNESS 47 47 47 47
PEAKING 5 5 5 5
CORING 0 0 0 0
LUMA DELAY 255 255 255 255
HPLL SPEED 1 1 1 1
YUV CONTRAST 29 29 29 29
YUV BRIGHTNESS 68 68 68 68
YUV SATCB 42 42 42 42
YUV SATCR 42 42 42 42
YUV TINT 3 3 3 3
SATURATION 2000 2000 2000 2000
TINT 32 32 32 32
 Factory Data per each Mode
3. VPC 3230(S) : SUB VCD
ITEM TV/Video/S-Video/Component 1,2(SD) Component 1,2(HD) PC DVI
PIP CONTRAST 43 43 43 43
PIP BRIGHTNESS 47 47 47 47
YUV CONTRAST 29 29 29 29
YUV BRIGHTNESS 68 68 68 68
LUMA DELAY 255 255 255 255
H POSITION 0 0 0 0
V POSITION 0 0 0 0

4. FLI 2200 (De-Interlacer)

ITEM TV/Video/S-Video/Component 1,2(SD) Component 1,2(HD) PC DVI
Y CLAMP 64 64 64 64
C CLAMP 512 512 512 512
Y DELAY 4 4 4 4
C DELAY 11 11 11 11
MOTION DETECT 48 48 48 48
 Factory Data per each Mode
5. ASI500 Ⅰ (SCALER MAIN / OSD)
ITEM TV/Video/S-Video/Component 1,2(SD) Component 1,2(HD) PC DVI
R CONTRAST 32
G CONTRAST 32
B CONTRAST 32
R BRIGHTNESS 0
G BRIGHTNESS 0
B BRIGHTNESS 0
TEXT ALPHA 1
TEXT THRESHOLD 7
FILTER ML 0
FILTER MR 0
FILTER FR 0
FILTER MC 16
FILTER UC 0
FILTER LC 0
FILTER YPASS 0
R GAMMA 32
G GAMMA 32
B GAMMA 32
H POSITION 0
V POSITION 0
H SIZE 0
V SIZE 0
OVERSCAN B 63
OVERSCAN G 63
OVERSCAN R 63
 Factory Data per each Mode

6. ASI500 Ⅱ (SCALER PIP)

ITEM TV/Video/S-Video/Component 1,2(SD) Component 1,2(HD) PC DVI
PIP R CONT 32
PIP G CONT 32
PIP B CONT 32
PIP R BRIGHT 0
PIP G BRIGHT 0
PIP B BRIGHT 0
PIP FILTER LC 0
PIP FILTER ML 0
PIP FILTER MR 0
PIP FILTER UC 0

8. CXA2151HD (COMPONENT MUX)

ITEM TV/Video/S-Video/Component 1,2(SD) Component 1,2(HD) PC DVI
GAIN-SEL 1 1 1 1
CR GAIN 7 7 7 7
CB GAIN 7 7 7 7
Y GAIN 7 7 7 7
 Factory Data per each Mode

7. DNIe (Picture Enhancer)

ITEM TV/Video/S-Video/Component 1,2(SD) Component 1,2(HD) PC DVI
BRIGHT OFFSET 0
CONTRA OFFSET 0
NR SCALE MAX 52
NR SCALE MIN 18
DE GAIN COR 3
DE GAIN CLIP 60
CE UPPER 240
CE CUTOFF 64
CE GAIN 48
WTE Y THRE 230
R CTL 2
SYNC MODE 1
PATT SEL 0
RED CONPENSA 616
BLUE CONPENSA 616
WTE GAIN 58
RAST VSIZE 1023
RAST HSIZE 895
SHARP OFFSET 0
 Factory Data per each Mode
9. AD 9883 (AD Converter)
ITEM TV/Video/S-Video/Component 1,2(SD) Component 1,2(HD) PC DVI
R GAIN 142 142 142 142
G GAIN 142 142 142 142
B GAIN 142 142 142 142
R, CR OFFSET 60 60 54 60
G, Y OFFSET 48 48 54 48
B, CB OFFSET 64 64 54 64
Auto Color

10. Logic (PDP Driver)

ITEM TV/Video/S-Video/Component 1,2(SD) Component 1,2(HD) PC DVI
R DRIVE 140 140 140 140
G DRIVE 130 130 130 130
B DRIVE 120 120 120 120
R CUTOFF 0 0 0 0
G CUTOFF 0 0 0 0
B CUTOFF 0 0 0 0
GAMMA 1
GTS SET 0
ERD MODE 2
RANDOM NOISE 0
DIFF FILTER 1
APC 1
APC SET 0
APC VALUE 127
ACTIVE VPOS 12
ACTIVE HPOS 19
VSYNC POS 3
HSYNC POS 32
VSYNC WIDTH 2
HSYNC WIDTH 12
 Factory Data per each Mode
11. TP LOG-ASI : Test Pattern LOGIC/SCALER
ITEM TV/Video/S-Video/Component 1,2(SD) Component 1,2(HD) PC DVI
LOG PATTERN 0
LOG HIGH LEVEL 255
LOG LOW LEVEL 0
ASI COLORBAR 0

12. Option
ITEM TV/Video/S-Video/Component 1,2(SD) Component 1,2(HD) PC DVI Remark
PIX SHIFT 0 0 : OFF 1 : ON

SHIFT TEST 0 0 : minute 1 : second

PIX NUMBER 2 Number of shifted Lines horizontally

SHIFT LINE 1 Number of shifted Lines vertically

SHIFT TIME 4 Time fixed at SHIFT TEST

COUNTRY 0 0 : domestic 1 : USA 2 : Japan

TEMP PROTECT 0
SNI DEMO 0 0 : OFF 1: ON

SNI THROUGH 0 0 : NOT THROUGH 1 : THROUGH

VIDEO MUTE 10 Unit : 100msec

IRC AFN 0 0 : for customer 1 : for military

LANGUAGE 0 0 : English 1 : French 2 : Spanish

CUSTOMER 0 0 : CE 1 : VMB

TUNER 0 0:1 TUNER 1:2 TUNER

Signal Waveform at AV(Audio & Visual) Board
Input Signal : 8-Color Bar

ANALOG BOARD IC103(TEA6425D) PIN6(VIDEO-CVBS) ANALOG BOARD CN102 PIN12(3D_Y_OUT)

ANALOG BOARD CN102 PIN10(3D_C_OUT) DIGITAL BOARD IC101(VPC3230D-C5) PIN57(VPC_VSYNC)

Signal Waveform at AV(Audio & Visual) Board
Input Signal : 8-Color Bar

DIGITAL BOARD IC101(VPC3230D-C5) PIN56(VPC_HSYNC) DIGITAL BOARD IC101(VPC3230D-C5) PIN28(VPC_CLK)

DIGITAL BOARD IC104(FLI2200) PIN91(FLI_VSYNC) DIGITAL BOARD IC104(FLI2200) PIN92(FLI_HSYNC)

* Dimensions in mm
Signal Waveform at AV(Audio & Visual) Board
Input Signal : 8-Color Bar

DIGITAL BOARD IC104(FLI2200) PIN90(FLI_DE) DIGITAL BOARD IC104(FLI2200) PIN117(FLI_CLK)

DIGITAL BOARD RW507(ASI500 OUTPUT) PIN2(MN_IN_V) DIGITAL BOARD RW507(ASI500 OUTPUT) PIN1(MN_IN_H)
Signal Waveform at AV(Audio & Visual) Board
Input Signal : 8-Color Bar

DIGITAL BOARD RW507(ASI500 OUTPUT) PIN4(MN_IN_CLK) DIGITAL BOARD IC601(SNI OUTPUT) PIN9(OUT_VSYNC)

DIGITAL BOARD IC601(SNI OUTPUT) PIN10(OUT_HSYNC) DIGITAL BOARD IC601(SNI OUTPUT) PIN8(OUT_DE)
Signal Waveform at AV(Audio & Visual) Board
Input Signal : 8-Color Bar

DIGITAL BOARD IC601(SNI OUTPUT) PIN12(OUT_CLK) ANALOG BOARD IC101(CXA2151 OUTPUT) PIN27(COMP_Y)

ANALOG BOARD IC101(CXA2151 OUTPUT) PIN26(COMP_PB) ANALOG BOARD IC101(CXA2151 OUTPUT) PIN25(COMP_PR)
Signal Waveform at AV(Audio & Visual) Board
Input Signal : 8-Color Bar

ANALOG BOARD IC101(CXA2151 OUTPUT) PIN23(COMP_V) ANALOG BOARD IC101(CXA2151 OUTPUT) PIN22(COMP_H)

DIGITAL BOARD IC705(AD9883 OUTPUT) PIN64(ASI_SUB_V) DIGITAL BOARD IC705(AD9883 OUTPUT) PIN66(ASI_SUB_H)
Signal Waveform at AV(Audio & Visual) Board
Input Signal : 8-Color Bar

DIGITAL BOARD IC705(AD9883 OUTPUT) PIN65(ASI_SUB_SOG) DIGITAL BOARD IC705(AD9883 OUTPUT) PIN67(ASI_SUB_CLK)

DIGITAL BOARD IC702(SII169CT OUTPUT) PIN47(DVI_VSYNC) DIGITAL BOARD IC702(SII169CT OUTPUT) PIN48(DVI_HSYNC)
Signal Waveform at AV(Audio & Visual) Board
Input Signal : 8-Color Bar

DIGITAL BOARD IC702(SII169CT OUTPUT) PIN46(DVI_DE) DIGITAL BOARD IC702(SII169CT OUTPUT) PIN44(DVI_CLK)
 Trouble Shooting for PDP Set
Turn on the set Connect Check
Connect OK Connect OK OK
Protection or Remove all Connectors OK Address other
X-Main Y-Main
NO LED problems from SMPS(except AV) and Buffer Boards
LED Normal
Check the protection Change
NO Change
SMPS NO NO
or voltages Change NO Change
X-Main
Y-Main Address
OK Buffer
Check PS_ON(0V : SMPS CN802 pin4) & OK Check the
NO LED Check stand_by 5V(SMPS CN802 pin2) Key-Pad

Remove all Connectors Change

Check Voltages Remove Connectors from NO Almost No OK
NO
NO from SMPS and Check the Digital
on the SMPS X,Y-Main,Address Voltages
voltages on AV Boards
(Vs,Va,Ve,Vset..) Buffers and Check the on the SMPS?
voltages on SMPS again Change
NO Voltages NO
OK Only Vs or Va cannot be measured
OK SMPS
Change
Check VS_ON(3V) NO Change
Check the damaged SMPS
CN803(SMPS pin2) Logic
components on Yes Change the
X,Y-Main & damaged Board
Address Board

NO Damaged Components

Check the Fuses on

Change the
X,Y-Main Boards I can see some Video Change
NO damaged Board
(F4003,F5003) ex) TV,Video or etc Inputsource Analog

OK
Check whether
Change Check the Change
Change Y-Main Change X-Main always No Video
NO NO NO, can't see Digital NO LVDS cable NO Logic
about all AV inputs
any Video
 Comparison with New Models
Project Alexander (V2) Mozart (V3) Nelson (V3)
Design

Brightness 700cd/m2 1000cd/m2 1000cd/m2

Contrast ratio 1200:1 3000:1 3000:1
Tuner 2Tuner 2Tuner 1Tuner
Audio out 10W x 2 15W x 2 15W x 2
Sound Dolby Virtual SRS Tru Surround XT SRS Tru Surround XT
Speaker Not Included Included Not Included
Video input 1Rear 2Rear 1Rear
S-Video input 1Rear 1Rear 1Rear
Component 2Rear 2Rear 1Rear
Input
Side Input - CVBS, S-Video -
DVI 1Rear 1Rear 1Rear
Power 330W 330W 330W
Consumption
Etc. - Touch Pad, Melody -