TIMING MODELS

By, Chiranjeevi Karthik 1st sem M.Tech(VLSI)

Introduction

Timing models characterize the circuit by a single parameter, which depends on resistance and capacitance of circuit elements. To ensure that single constant timing approximation is valid for the circuit, the timing models provides both an estimate and bounds for the output waveform. These simple models provide insight about the circuit performance issues , as well as determining the circuit delay.

Timing models for sequential cells

Figure shows timing arcs of a sequential cell

Synchronous checks: setup and hold

For synchronous outputs such as Q & QN there is following timing arc Ck to output propagation delay arc. Fig (a) shows the timing checks using various signal waveforms

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The setup and hold arc checks are needed for proper propagation of data through sequential cell. These checks will verify that the data input is unambiguous at the active edge of the clock and proper data is latched in at active edge. Setup time is the min time before the active edge of clock where the data input must remain stable. Hold time is the min time after active edge of the clock where the data input should remain stable.

Negative values in setup and hold checks

The negative hold value is acceptable and happens when the path from the pin of a FF to the internal latch point of a data is longer than the corresponding path for clock. For FF it is helpful to have a negative hold time on scan mode data input pins. This gives flexibility in terms of clock skew and eliminates the need for almost all buffer insertion for fixing the hold violations in scan mode.

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The figure shows negative hold

Asynchronous check

The asynchronous recovery and removal check verify that the asynchronous pin has return unambiguously to inactive state at the next active clock edge.

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Recovery time is the min time that an asynchronous pin remains inactive after being de-asserted before active edge of the clock. Removal time is the min time after the active edge of the clock that the asynchronous pin must be active before it is re-asserted.

Pulse width check

In addition to the synchronous and asynchronous check ,there is a check that ensures that width of pulse at input pin of a cell meets the min requirement. The pulse width checks can be specified for relevant synchronous and asynchronous pins also. It can also be specified for high pulse or low pulse.

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