WELCOME

To
Introduction to Digital Logic Fundamentals
(DLF)

Dr. Nageswara Rao K

Department of EE
 MODULE 2 – LOGIC GATES
 Minimization:
 K‐Map Method ,
 POS ‐ SOP,
 Don’t Care Conditions,
 NAND, NOR Implementation,
 Combinational Logic:
 Combinational Circuits,
 Analysis and Design Procedure,
 Binary Adder, Subtractor,
 Magnitude Comparator,
 Decoders, Encoders,
 Multiplexers.
Half & Full Adder
 HALF-ADDER
• To add two binary bits.
• It has two inputs that represent the two bits to be added.
• and two outputs, one producing the SUM output and the other
producing the CARRY.
Truth table & Boolean expressions
A B S C

0 0 0 0

0 1 1 0

1 0 1 0

1 1 0 1
LOGIC DIAGRAM
 FULL-ADDER
A full adder is a combinational circuit that forms the arithmetic sum of three
input bits.
It consists of 3 inputs and 2 outputs.
Two of the input variables, represent the significant bits to be added.
The third input represents the carry from previous lower significant position.
 Truth table &
Boolean expressions
LOGIC DIAGRAM
FULL ADDER WITH
2 -HALF ADDERS
 HALF -SUBTRACTOR
 Used to subtract one binary digit from another to
produce a DIFFERENCE output and a BORROW
output.
 The BORROW output here specifies whether a ‗1‘ has
been borrowed to perform the subtraction.
Truth table & Boolean
expressions
LOGIC DIAGRAM
 Comparing a Half-Subtractor
with a Half-Adder
 SUM = DIFFERENCE

 BORROW ≠ CARRY
 Full Subtractor
 Performs subtraction operation on two bits, a
minuend and a subtrahend.
 Takes into consideration whether a ‗1‘ has already
been borrowed by the previous adjacent lower
minuend bit or not.
 Truth table &
Boolean expressions
LOGIC DIAGRAM
FULL-SUBTRACTOR USING
2- HALF-SUBTRACTORS
 Binary Adder (Parallel Adder)
 The 4-bit binary adder using full adder circuits is capable of
adding two 4-bit numbers resulting in a 4-bit sum and a
carry output.
The 4-bit words to be added
 C3 C2 C1 C0 = 11 1 0
 A3 A2 A1 A0 = 1 1 1 1- (15)
 B3 B2 B1 B0 = 0 0 1 1 – (03)
 OUTPUT = 1 00 1 0 SUM

CARRY
OUT
 Binary Adder (Parallel Adder)

0 1 0 1 1 1 1 1

1 1 1

1 0 0 1 0
 Carry Propagation
Look-Ahead Carry Generator
• Example: 0011+ 0101

 propagation delay of 30nsec

 S3 = 30+30+30+30=120 nsec.
 Carry Propagation
Look-Ahead Carry Generator
 Carry Propagation
Look-Ahead Carry Generator
Binary additon &
subtraction
Binary Subtraction
 Have previously looked at the subtraction operation. A
quick review.
 Just like subtraction in any other base
 Minuend 10110
 Subtrahand - 10010
 Difference 00100
 And when a borrow is needed. Note that the borrow gives
us 2 in the current bit position.

 .
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Multiplexers
And a full example
 And more ripple -

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Multiplexers
In General
 When there is no borrow into the msb position,
then the subtrahend in not larger than the
minuend and the result is positive and correct.

 If a borrow into the msb does occur, then the

subtrahend is larger than the minuend. This was
seen back in lecture 2.
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Consider
 Now do the operation 4 – 6

 Correct difference is -2 or -0010

 Different because 2n was brought in and made
the operation M-N+2n
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Desired
 Actual desired magnitude is N-M
 To get this need to do 2n – (M-N+2)= N-M

 Doing the subtraction from 2n gives the

correct result.
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Multiplexers
Two’s compliment
 But how do you represent a minus sign
electronically in a computer?
 How can you represent it such that arithmetic
operations are manageable?
 There are two types of compliments for each
number base system.
 Have the r’s complement
 Have the (r-1)’s complement
 For base 2 have 2’s complement and
1’s complement
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1’s Complement
 1’s complement of N is defined as (2 n -1)-N.
 If n=4 have (2n -1) being 1 0000 - 1 = 1111
 So for n=4 would subtract any 4-bit binary
number from 1111.
 This is just inverting each bit.
 Example: 1’s compliment of 1011001
 is 0100110
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Multiplexers
2’s complement
 The 2’s complement is defined as 2 n-N
 Can be done by subtraction of N from 2 n or
adding 1 to the 1’s complement of a number.
 For 6 = 0110
 The 1’s complement is 1001
 The 2’s complement is 1010

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Multiplexers
Operation with 2’s complement
 Add 4 and -6
 Will use the 2’s complement of -6 or 1010
 4 0100
 -6 1010
 1110
 And taking the 2’s complement of 1110 get
0001 + 1 = 0010

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Multiplexers
A 2’s complement table for 4 bits
 Listing the
values
represented.

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Multiplexers
A circuit that does +/-
 A general adder subtractor
 OP=0 for addition/ =1 for subtraction

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Multiplexers
Another number format
 Signed magnitude –
use the MSB to
indicate the sign. The
remaining bits
indicate the
magnitude.

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Multiplexers
Overflow
 When adding 2 n-bit numbers it is possilbe to
get a n+1 bit result if there is a carry out.
 On paper it is easy just add another bit.
 In 2’s complement add a msb 0 for a positive
or a msb 1 for a negative.

 In a computer the number of bits that can be

used is fixed.
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Overflow indication.
 In 8-bit 2’s complement notation the range
that can be represented is -127 to +127.
 Then the operation to add +70 to +80 is
 Carries 0 1
 +70 0 100 0110
 +80 0 101 0000
 +150 1 001 0110
 Also look at the addition of -70 and -80
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The other addition
 The addition of -70 and -80
 Carries 1 0
 -70 1 011 1010
 -80 1 011 0000
 -150 0 110 1010
 The rule – if the carry into the msb position differs from
the carry out from the msb position then an overflow has
occurred.
 The circuit

 .
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