Unit4 OS

Noida Institute of Engineering and Technology, Greater Noida
Operating Systems
ACSE0403A
Unit 4
Memory Management System

Rajeev Kumar
B. Tech 4th Semester Assistant Professor, Dept. of IT
Rajeev Kumar ACSE0403A OS Unit 4 1

June 1, 2024
Evaluation Scheme
June 1, 2024 Rajeev Kumar ACSE0403A OS Unit 4 2

Subject Syllabus

Subject Syllabus

Syllabus For Unit-4
UNIT-IV Memory Management

Memory Management function, Address Binding Loading : Compile Time, Load
Time and Execution Time, MMU, Types of Linking, Types of Loading, Swapping,
Multiprogramming with Fixed Partitions, Multiprogramming with variable
partitions,
Memory Allocation: Allocation Strategies First Fit, Best Fit, and Worst Fit, Paging,
Segmentation, Paged Segmentation, Virtual Memory Concepts, Demand Paging,
Performance of Demand Paging, Page Replacement Algorithms: FIFO,LRU,
Optimal and LFU, Belady’s Anomaly, Thrashing, Cache Memory Organization,
Locality of Reference.

Introduction (CO4)
 Memory management keeps track of the status of each memory location, whether it is
allocated or free.
 It allocates the memory dynamically to the programs at their request and frees it for
reuse when it is no longer needed.
These Requirements of memory management are:

1. Relocation
2. Protection
3. Sharing
4. Logical organization
5. Physical Organization
For Video Lecture:- https://www.youtube.com/watch?v=UDPYpf-nsDY

Base and Limit Registers
• A pair of base and limit registers define the logical address space
• CPU must check every memory access generated in user mode to be sure it is between
base and limit for that user
Figure :- A base and a limit register define a logical address space
Reference Book :- Operating System Concepts (8th Edition) Abraham Silberschatz, Peter Baer Galvin, and Greg
Gagne Page No. -316
Hardware Address Protection (CO4)
Figure:- Hardware address protection with base and limit registers.
Reference Book :- Operating System Concepts (8th Edition) Abraham Silberschatz, Peter Baer
Galvin, and Greg Gagne Page No. -317

Binding of Instructions and Data to Memory
Address binding of instructions and data to memory addresses can happen at three different
stages
 Compile time: If memory location known a priori, absolute code can be generated;
must recompile code if starting location changes
 Load time: Must generate relocatable code if memory location is not known at
compile time
 Execution time: Binding delayed until run time if the process can be moved during its
execution from one memory segment to another
Need hardware support for address maps (e.g., base and limit registers).
Galvin, and Greg Gagne Page No. -318-319.

Multistep Processing of a User Program
Figure:- Multistep processing of a user program.

Logical vs. Physical Address Space (CO4)
The concept of a logical address space that is bound to a separate physical address space is
central to proper memory management
 Logical address – generated by the CPU; also referred to as virtual address
 Physical address – address seen by the memory unit
Logical and physical addresses are the same in compile-time and load-time address-binding
schemes; logical (virtual) and physical addresses differ in execution-time address-binding
scheme
 Logical address space is the set of all logical addresses generated by a program
 Physical address space is the set of all physical addresses generated by a program
For Video Lecture:- https://www.youtube.com/watch?v=CmTMr_x3NwY
June 1, 2024 11
Rajeev Kumar ACSE0403A OS Unit 4
Memory-Management Unit (MMU)
 Hardware device that at run time maps virtual to physical address

 Many methods are possible.
 To start, consider simple scheme where the value in the relocation register is added to
every address generated by a user process at the time it is sent to memory
-The user program deals with logical addresses; it never sees the real physical
addresses
-Execution-time binding occurs when reference is made to location in memory
-Logical address bound to physical addresses
For Video Lecture:-
http://www.infocobuild.com/education/audio-video-courses/computer-science/IntroToOperatin
gSystems-IIT-Madras/lecture-07.html

Dynamic relocation using a relocation register
 Routine is not loaded until it is called

 Better memory-space utilization; unused routine is never loaded
 All routines kept on disk in relocatable load format
 Useful when large amounts of code are needed to handle infrequently occurring cases
 No special support from the operating system is required
 Implemented through program design
 OS can help by providing libraries to implement dynamic loading
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June 1, 2024 Rajeev Kumar ACSE0403A OS Unit 4
Dynamic relocation using a relocation register
Figure:- Dynamic relocation using a relocation register.
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June 1, 2024 Rajeev Kumar ACSE0403A OS Unit 4
Linking & Loading (CO4)
Types of Linking
A.Static linking
B.Dynamic linking
Types of Loading
A.Static Loading
B.Dynamic Loading
For video lecture :-

https://www.youtube.com/watch?v=lWVQsld8hMI
Reference Book :- Operating System Concepts (8th Edition) Abraham Silberschatz, Peter Baer Galvin, and
Greg Gagne Page No. -320-321.

• The choice between Static or Dynamic Loading is to be made at the time of

computer program being developed. If you have to load your program statically,
then at the time of compilation, the complete programs will be compiled and linked
without leaving any external program or module dependency. The linker combines
the object program with other necessary object modules into an absolute program,
which also includes logical addresses.
• If you are writing a Dynamically loaded program, then your compiler will compile
the program and for all the modules which you want to include dynamically, only
references will be provided and rest of the work will be done at the time of
execution.
• At the time of loading, with static loading, the absolute program (and data) is
loaded into memory in order for execution to start.
• If you are using dynamic loading, dynamic routines of the library are stored on a
disk in relocatable form and are loaded into memory only when they are needed by
the program.
• As explained above, when static linking is used, the linker combines all other
modules needed by a program into a single executable program to avoid any
runtime dependency.
• When dynamic linking is used, it is not required to link the actual module or
library with the program, rather a reference to the dynamic module is provided
at the time of compilation and linking. Dynamic Link Libraries (DLL) in
Windows and Shared Objects in Unix are good examples of dynamic libraries.

Swapping (CO4)
A process can be swapped temporarily out of memory to a backing store, and

then brought back into memory for continued execution
Total physical memory space of processes can exceed physical memory
 Backing store – fast disk large enough to accommodate copies of all memory
images for all users; must provide direct access to these memory images
 Roll out, roll in – swapping variant used for priority-based scheduling

algorithms; lower-priority process is swapped out so higher-priority process can
be loaded and executed

Schematic View of Swapping (CO4)
Figure:- Swapping of two processes using a disk as a backing store.

Daily Quiz
1. What are need of memory management.

2. Differentiate between physical and logical address.
3. Write the multiple step of address binding .
4. What is swapping?

Daily Quiz
5. What is Address Binding?
a) going to an address in memory
b) locating an address with the help of another address
c) binding two addresses together to form a new address in a different memory space
d) a mapping from one address space to another
6. Binding of instructions and data to memory addresses can be done at ____________

a) Compile time
b) Load time
c) Execution time
d) All of the mentioned

Topic mapping with CO
Topic CO
Multiprogramming with Fixed CO4
Partitions, Multiprogramming with
variable partitions,
Memory Allocation: Allocation CO4
Strategies First Fit, Best Fit, and Worst
Fit

Topic Objectives
Topic Objective
Students will be able to
Multiprogramming with Fixed Understand the static and dynamic approaches of memory
Partitions, Multiprogramming with partition with their advantages and
variable partitions,
Memory Allocation: Allocation Understand different types of allocation strategies
Strategies First Fit, Best Fit, and Worst
Fit

Topics & Course Outcome
Topic Name Course Outcome

Memory Allocation schemes CO4

Topic Objective
• To explore various techniques of allocating memory to processes.

Contiguous Allocation (CO4)
 Main memory must support both OS and user processes

 Limited resource, must allocate efficiently
 Contiguous allocation is one early method
 Main memory usually divided into two partitions:
– Resident operating system, usually held in low memory with interrupt vector
– User processes then held in high memory
– Each process contained in single contiguous section of memory
For video lecture :-https://www.youtube.com/watch?v=IwESijQs9sM

Contiguous Allocation (Cont.)
 Relocation registers used to protect user processes from each other, and from
changing operating-system code and data
– Base register contains value of smallest physical address
– Limit register contains range of logical addresses – each logical address must
be less than the limit register
– MMU maps logical address dynamically
– Can then allow actions such as kernel code being transient and kernel
changing size
For video lecture:- https://www.youtube.com/watch?v=zDxEctO31TA

Hardware Support for Relocation and Limit Registers
Figure:- Hardware support for relocation and limit registers.

Reference Book :- Operating System Concepts (8th Edition) Abraham Silberschatz, Peter Baer Galvin,
and Greg Gagne Page No. -325.

Multiple-partition allocation (CO4)
Multiple-partition allocation
Degree of multiprogramming is limited by number of partitions
 Variable-partition sizes for efficiency (sized to a given process’ needs)
 Hole – block of available memory; holes of various size are scattered throughout
memory
When a process arrives, it is allocated memory from a hole large enough to

accommodate it

Multiple-partition allocation (CO4)
 Process exiting frees its partition, adjacent free partitions combined
 Operating system maintains information about:
 a) allocated partitions
b) free partitions (hole)
Figure:- Fixed & Unfixed memory partitions.

Dynamic Storage-Allocation Problem
How to satisfy a request of size n from a list of free holes?
Placement Algorithm
• First-fit: Allocate the first hole that is big enough
• Best-fit: Allocate the smallest hole that is big enough; must search entire list, unless
ordered by size
– Produces the smallest leftover hole
• Worst-fit: Allocate the largest hole; must also search entire list
– Produces the largest leftover hole
Note:- First-fit and best-fit are better than worst-fit in terms of speed and storage
utilization
For Numerical video lecture :-https://www.youtube.com/watch?v=N3rG_1CEQkQ

Fragmentation (CO4)
• Fragmentation is an unwanted problem where the memory blocks cannot be

allocated to the processes due to their small size and the blocks remain unused.
It can also be understood as when the processes are loaded and removed from
the memory they create free space or hole in the memory and these small
blocks cannot be allocated to new upcoming processes and results in
inefficient use of memory.
Basically, there are two types of fragmentation:
• Internal Fragmentation
• External Fragmentation

Types of Fragmentation (CO4)
Internal Fragmentation
• In this fragmentation, the process is allocated a memory block of size more
than the size of that process. Due to this some part of the memory is left
unused and this cause internal fragmentation.
• Example: Suppose there is fixed partitioning (i.e. the memory blocks are of
fixed sizes) is used for memory allocation in RAM. These sizes are 2MB,
4MB, 4MB, 8MB. Some part of this RAM is occupied by the Operating
System (OS).
• Now, suppose a process P1 of size 3MB comes and it gets memory block of
size 4MB. So, the 1MB that is free in this block is wasted and this space can’t
be utilized for allocating memory to some other process. This is
called internal fragmentation.


External Fragmentation
• In this fragmentation, although we have total space available that is needed by
a process still we are not able to put that process in the memory because that
space is not contiguous. This is called external fragmentation.
• Example: Suppose in the above example, if three new processes P2, P3, and
P4 come of sizes 2MB, 3MB, and 6MB respectively. Now, these processes get
memory blocks of size 2MB, 4MB and 8MB respectively allocated.
• So, now if we closely analyze this situation then process P3 (unused 1MB)and
P4(unused 2MB) are again causing internal fragmentation. So, a total of 4MB
(1MB (due to process P1) + 1MB (due to process P3) + 2MB (due to process
P4)) is unused due to internal fragmentation.
• Now, suppose a new process of 4 MB comes. Though we have a total space
of 4MB still we can’t allocate this memory to the process. This is
called external fragmentation.
P2

Fragmentation (CO4)
How to remove internal fragmentation?

Daily Quiz-2
1. Differentiate between contiguous and non contiguous memory allocation.

2. What is compaction.
3. Give the example for placement algorithm.
4. Differentiate between internal and external fragmentation.

Daily Quiz-2
5. Which one of the following is the address generated by CPU?
a) physical address
b) absolute address
c) logical address
d) none of the mentioned
6. Run time mapping from virtual to physical address is done by ____________

a) Memory management unit
b) CPU
c) PCI
d) None of the mentioned

Daily Quiz-2
7. What is compaction?
a) a technique for overcoming internal fragmentation
b) a paging technique
c) a technique for overcoming external fragmentation
d) a technique for overcoming fatal error
8. In contiguous memory allocation ____________

a) each process is contained in a single contiguous section of memory
b) all processes are contained in a single contiguous section of memory
c) the memory space is contiguous

Prerequisite and Topic wise Recap
Prerequisite
 To know about the basic knowledge of program execution environment and what the usage of
Random Access Memory(RAM) .
 Recap
To understood various techniques of allocating memory to processes.

Daily Quiz for Module 2 (Memory Allocation)
For formative assessment 1 (10 questions through Google Quiz)

https://docs.google.com/forms/d/e/1FAIpQLSc4Yh7qmuGaZPe5TGGoKS3CQY62nIJniPLt-RvbdiF5hc64TQ/vi
ewform?usp=sf_link
Rajeev Kumar ACSE0403A OS Unit 4 42

June 1, 2024
Topic CO
Paging & Segmentation CO4
Segmentation With Paging CO4

Topic Objectives
Topic Objective
Paging & Segmentation Understand the non contiguous memory allocation
schemes
Segmentation With Paging Know about the implementation of segmentation
with paging concept

Topic Objectives
• To discuss in detail how paging & segmentation works in contemporary computer systems.
• To understand different types of structure of page table.

Paging (CO4)
 Physical address space of a process can be noncontiguous; process is allocated physical
memory whenever the latter is available
-Avoids external fragmentation
-Avoids problem of varying sized memory chunks
 Divide physical memory into fixed-sized blocks called frames

-Size is power of 2, between 512 bytes and 16 Mbytes
 Divide logical memory into blocks of same size called pages
Gagne Page No. -328-332.

Address Translation Scheme
Address generated by CPU is divided into:

 Page number (p) – used as an index into a page table which contains base address of
each page in physical memory
 Page offset (d) – combined with base address to define the physical memory address
that is sent to the memory unit
page number page offset
p d
m -n n
 For given logical address space 2m and page size 2n
For video lecture :-

https://www.youtube.com/watch?v=kt4LkPFt8Zg
https://www.youtube.com/watch?v=kt4LkPFt8Zg&t=165s

Paging Hardware (CO4)
Figure :- Paging hardware.



Implementation of Page Table
 Page table is kept in main memory

Page-table base register (PTBR) points to the page table
Page-table length register (PTLR) indicates size of the page table
 In this scheme every data/instruction access requires two memory accesses
-One for the page table and one for the data / instruction
 The two memory access problem can be solved by the use of a special fast-lookup
hardware cache called associative memory or translation look-aside buffers (TLBs)
Greg Gagne Page No. -333

Associative Memory
• Associative memory – parallel search

P a ge # F ra m e #
• Address translation (p, d)

– If p is in associative register, get frame # out
– Otherwise get frame # from page table in memory
For video lecture :- https://www.youtube.com/watch?v=kHhZUphoANI

Paging Hardware With TLB (CO4)
Figure:- Paging hardware with TLB.

Paging Hardware With TLB (CO4)
Effective memory access time = h1*t1 + (1-h1)*h2*t2+

…...

Advantages & Disadvantages of paging
Advantages :
 Eliminates external fragmentation
 Pages are mapped appropriately anyway
 Allows demand paging and pre-paging
 More efficient swapping
 No need for considerations about fragmentation
Disadvantages :
 Longer memory access times (page table lookup)
 Can be improved using TLB
 Memory requirements (one entry per VM page)
 Internal fragmentation

Memory Protection in Paging
Memory protection implemented by associating protection bit with each frame to

indicate if read-only or read-write access is allowed
-Can also add more bits to indicate page execute-only, and so on
Valid-invalid bit attached to each entry in the page table:
 “valid” indicates that the associated page is in the process’ logical address space,
and is thus a legal page
 “invalid” indicates that the page is not in the process’ logical address space
Or use page-table length register (PTLR)
Any violations result in a trap to the kernel

Valid (v) or Invalid (i) Bit In A Page Table
Figure :-. Valid (v) or invalid (i) bit in a page table.

Daily Quiz-3
1. Explain the paging with their advantages and disadvantages.
2. Physical memory is broken into fixed-sized blocks called ________
a) frames
b) pages
c) backing store
3. Logical memory is broken into blocks of the same size called _________
a) frames
b) pages
c) backing store

Daily Quiz-3
4. The _____ table contains the base address of each page in physical memory.
a) process
b) memory
c) page
d) frame
5. The size of a page is typically ____________

a) varied
b) power of 2
c) power of 4

Segmentation (CO4)
• Memory-management scheme that supports user’s view of memory.
• A program is a collection of segments.
 A segment is a logical unit such as:
main program
procedure
function
method
object
local variables, global variables
common block
stack
symbol table
arrays
Greg Gagne Page No. -343-345.

Segmentation Architecture
Logical address consists of a two tuple:
<segment-number, offset>,
Segment table – maps two-dimensional physical addresses; each table entry has:
 base – contains the starting physical address where the segments reside in memory
 limit – specifies the length of the segment
 Segment-table base register (STBR) points to the segment table’s location in memory
 Segment-table length register (STLR) indicates number of segments used by a program;
segment number s is legal if s < STLR
Video Lecture:-https://www.youtube.com/watch?v=xD5PB_g1rIE

Segmentation Architecture (Cont.) (CO4)
Protection
With each entry in segment table associate:
-validation bit = 0  illegal segment
-read/write/execute privileges
 Protection bits associated with segments; code sharing occurs at segment level
 Since segments vary in length, memory allocation is a dynamic storage-allocation problem
 A segmentation example is shown in the following diagram
For video lecture- https://www.youtube.com/watch?v=xD5PB_g1rIE

Segmentation Hardware
Figure :- Segmentation hardware.



Advantages & Disadvantages of Segmentation
Advantages :
 No internal fragmentation
 Average segment size is larger than the actual page size.
 It is easier to relocate segments than entire address space.
 The segment table is of lesser size as compared to the page table in paging.
 Less overhead.
Disadvantages :
 It can have external fragmentation.
 Costly memory management algorithms.
 It is difficult to allocate contiguous memory to variable sized partition.
 Segments of unequal size not suited well for swapping.

Segmentation with paging (CO4)
In segmented paging,
 Process is first divided into segments and then each segment is divided into pages.
 These pages are then stored in the frames of main memory.
 A page table exists for each segment that keeps track of the frames storing the pages of
that segment.
 Each page in page table occupies one frame in the main memory.

 Number of entries in the page table of a segment = Number of pages that segment is
divided.
 A segment table exists that keeps track of the frames storing the page tables of
segments.
 Number of entries in the segment table of a process = Number of segments that
process is divided.
 The base address of the segment table is stored in the segment table base register.

CPU generates a logical address consisting of three parts-

 Segment Number
 Page Number
 Page Offset

Segmentation with Paging Hardware

Continued…
Advantages-
• Segment table contains only one entry corresponding to each segment.
• It reduces memory usage.
• The size of page table is limited by the segment size.
• It solves the problem of external fragmentation.
Disadvantages-
• Segmented paging suffers from internal fragmentation.
• The complexity level is much higher as compared to paging.

Daily Quiz-4
1. Differentiate between paging and segmentation.

2. What is TLB.
3. In segmentation, each address is specified by ____________
a) a segment number & offset
b) an offset & value
c) a value & segment number
d) a key & value
4. Each entry in a segment table has a ____________
a) segment base
b) segment peak
c) segment value

Topic CO
Virtual Memory Concepts, CO4
Demand Paging, Performance of Demand CO4

Paging,,
Page Replacement Algorithms: FIFO,LRU, CO4

Optimal and LFU,
Belady’s Anomaly CO4

Thrashing, Cache Memory Organization, CO4
Locality of Reference.

Topic Objectives
Topic Objective
Virtual Memory Concepts, Understand the concept of Virtual Memory
Demand Paging, Performance of Demand Know about Demand Paging, Performance of Demand
Paging, Paging
Page Replacement Algorithms: FIFO,LRU, Understand the Page Replacement Algorithms:
Optimal and LFU, FIFO,LRU, Optimal and LFU,
Belady’s Anomaly Understand the Belady’s Anomaly

Thrashing, Cache Memory Organization, Understand Thrashing, Cache Memory Organization,
Locality of Reference. Locality of Reference.

Topic Objective
• To describe the benefits of a virtual memory system.

Virtual Memory (CO4)
• Virtual Memory is a storage mechanism which offers user an illusion of having

a very big main memory. It is done by treating a part of secondary memory as the
main memory. In Virtual memory, the user can store processes with a bigger size
than the available main memory.
• Therefore, instead of loading one long process in the main memory, the OS loads
the various parts of more than one process in the main memory. Virtual memory
is mostly implemented with demand paging and demand segmentation.
Reasons for using virtual memory:
• Whenever your computer doesn’t have space in the physical memory it writes
what it needs to remember to the hard disk in a swap file as virtual memory.
• If a computer running Windows needs more memory/RAM, then installed in the
system, it uses a small portion of the hard drive for this purpose.

Working of Virtual Memory (Cont.)
• In the modern world, virtual memory has become quite common these days. It
is used whenever some pages require to be loaded in the main memory for the
execution, and the memory is not available for those many pages.
• So, in that case, instead of preventing pages from entering in the main memory,
the OS searches for the RAM space that are minimum used in the recent times
or that are not referenced into the secondary memory to make the space for the
new pages in the main memory.

(Cont.) (CO4)
Virtual address space – logical view of how process is stored in memory

– Usually start at address 0, contiguous addresses until end of space
– Meanwhile, physical memory organized in page frames
– MMU must map logical to physical
Virtual memory can be implemented via:

– Demand paging
– Demand segmentation
Galvin, and Greg Gagne Page No. -361

Daily Quiz-5
1. What are need of virtual memory.

2. What is page fault.
3. Because of virtual memory, the memory can be shared among ____________
a) processes
b) threads
c) instructions
4. When a program tries to access a page that is mapped in address space but not loaded in physical
memory, then ____________
a) segmentation fault occurs
b) fatal error occurs
c) page fault occurs
d) no error occurs

Prerequisite and Topic wise Recap
Prerequisite
 To know about the difference between RAM and virtual memory
Recap
 To understood usage of the and benefits of a virtual memory system.


Demand paging CO4
Page Replacement Algorithms. CO4
Allocation of free frame CO4

Topic Objective
• To explain the concepts of demand paging, page-replacement algorithms, and allocation

of page frames.

Demand Paging (CO4)
• A demand paging mechanism is very much similar to a paging system with

swapping where processes stored in the secondary memory and pages are
loaded only on demand, not in advance.
• So, when a context switch occurs, the OS never copy any of the old program’s
pages from the disk or any of the new program’s pages into the main memory.
Instead, it will start executing the new program after loading the first page and
fetches the program’s pages, which are referenced.
• During the program execution, if the program references a page that may not
be available in the main memory because it was swapped, then the processor
considers it as an invalid memory reference. That’s because the page fault and
transfers send control back from the program to the OS, which demands to
store page back into the memory.

Demand Paging
Figure:- Transfer of a paged memory to contiguous disk space.

Valid-Invalid Bit
With each page table entry a valid–invalid bit is associated
(v  in-memory – memory resident, i  not-in-memory)
Initially valid–invalid bit is set to i on all entries
Example of a page table snapshot:
During MMU address translation, if valid–invalid bit in page table entry is i  page fault

Conti….. (CO4)
Figure:- Page table when some pages are not in main memory.

Page Fault (CO4)
If there is a reference to a page, first reference to that page will trap to operating system:
page fault
1. Operating system looks at another table to decide:
 Invalid reference  abort
 Just not in memory
2. Find free frame
3. Swap page into frame via scheduled disk operation
4. Reset tables to indicate page now in memory, Set validation bit = v
5. Restart the instruction that caused the page fault
For video Lecture:- https://www.youtube.com/watch?v=lgmws9oraXE

Gagne Page No. -362-364.

Steps in Handling a Page Fault.
Figure:- Steps in handling a page fault

What Happens if There is no Free Frame?
Used up by process pages

Also in demand from the kernel, I/O buffers, etc
How much to allocate to each?
Page replacement – find some page in memory, but not really in use, page it out
-Algorithm – terminate? swap out? replace the page?
-Performance – want an algorithm which will result in minimum number of page
faults
Same page may be brought into memory several times

Page Replacement (CO4)
 Prevent over-allocation of memory by modifying page-fault service routine to include

page replacement
 Use modify (dirty) bit to reduce overhead of page transfers – only modified pages are
written to disk
 Page replacement completes separation between logical memory and physical memory –
large virtual memory can be provided on a smaller physical memory
Gagne Page No. -369-377

Basic Page Replacement (CO4)
1. Find the location of the desired page on disk
2. Find a free frame:

- If there is a free frame, use it
- If there is no free frame, use a page replacement algorithm to select a victim
frame
- Write victim frame to disk if dirty
3. Bring the desired page into the (newly) free frame; update the page and frame tables
4. Continue the process by restarting the instruction that caused the trap
Note now potentially 2 page transfers for page fault – increasing EAT

Daily Quiz-6
1. Differentiate between demand paging and demand segmentation.

2. What is lazy swapper?
3. Effective access time is directly proportional to ____________
a) page-fault rate
b) hit ratio
c) memory access time
4. Virtual memory allows ____________
a) execution of a process that may not be completely in memory
b) a program to be smaller than the physical memory
c) a program to be larger than the secondary storage
d) execution of a process without being in physical memory

Page Replacement
Figure:- Page replacement

Page and Frame Replacement Algorithms
Frame-allocation algorithm determines

o How many frames to give each process
o Which frames to replace
Page-replacement algorithm
o Want lowest page-fault rate on both first access and re-access
Evaluate algorithm by running it on a particular string of memory references (reference string)
and computing the number of page faults on that string
o String is just page numbers, not full addresses
o Repeated access to the same page does not cause a page fault
o Results depend on number of frames available
In all our examples, the reference string of referenced page numbers is
7,0,1,2,0,3,0,4,2,3,0,3,0,3,2,1,2,0,1,7,0,1

First-In-First-Out (FIFO) Algorithm
Reference string: 7,0,1,2,0,3,0,4,2,3,0,3,0,3,2,1,2,0,1,7,0,1
3 frames (3 pages can be in memory at a time per process)
15 page faults
Can vary by reference string: consider 1,2,3,4,1,2,5,1,2,3,4,5
Adding more frames can cause more page faults!
Belady’s Anomaly: It is the phenomenon in which increasing the number of
page frames results in an increase in the number of page faults for certain
memory access patterns.

Optimal Algorithm
• Replace the page that will not be used for the longest period of time.
– 9 is optimal for the example
• How do you know this?
– Can’t read the future
Used for measuring how well your algorithm performs
9 page faults
For Video lecture:- https://www.youtube.com/watch?v=Ub4VVDGLJx0

Least Recently Used (LRU) Algorithm
1. Use past knowledge rather than future

2. Replace page that has not been used in the most amount of time
3. Associate time of last use with each page
12 page faults
o 12 faults – better than FIFO but worse than OPT

o Generally good algorithm and frequently used
Counting Algorithms (CO4)
Keep a counter of the number of references that have been made to each page
Not common.
 Least Frequently Used (LFU) Algorithm: replaces page with smallest count
 Most Frequently Used (MFU) Algorithm: based on the argument that the page with
the smallest count was probably just brought in and has yet to be used

Global vs. Local Allocation
• Global replacement – process selects a replacement frame from the set of

all frames; one process can take a frame from another
– But then process execution time can vary greatly
– But greater throughput so more common
• Local replacement – each process selects from only its own set of
allocated frames
– More consistent per-process performance
– But possibly underutilized memory

Daily Quiz-7
1. Explain the FIFO page replacement with suitable example.
2. Which of the following page replacement algorithms suffers from Belady’s Anomaly?
a) Optimal replacement
b) LRU
c) FIFO
d) Both optimal replacement and FIFO
3. A process refers to 5 pages, A, B, C, D, E in the order : A, B, C, D, A, B, E, A, B, C,
D, E. If the page replacement algorithm is FIFO, the number of page transfers with an
empty internal store of 3 frames is?
a) 8
b) 10
c) 9
d) 7


Thrashing CO4

Topic Objective
• To discuss the principles of the working-set model.

Thrashing (CO4)
• In case, if the page fault and swapping happens very frequently at a higher
rate, then the operating system has to spend more time swapping these pages.
This state in the operating system is termed as thrashing. Because of
thrashing the CPU utilization is going to be reduced.
• Let's understand by an example, if any process does not have the number of
frames that it needs to support pages in active use then it will quickly page fault.
And at this point, the process must replace some pages. As all the pages of the
process are actively in use, it must replace a page that will be needed again right
away. Consequently, the process will quickly fault again, and again, and again,
replacing pages that it must bring back in immediately. This high paging activity
by a process is called thrashing.
• During thrashing, the CPU spends less time on some actual productive work and
spend more time on swapping.
Thrashing (Cont.)

Cause of thrashing (CO4)
• Thrashing affects the performance of execution in the Operating system. Also, thrashing results in
severe performance problems in the Operating system.
• When the utilization of CPU is low, then the process scheduling mechanism tries to load many
processes into the memory at the same time due to which degree of Multiprogramming can be
increased. Now in this situation, there are more processes in the memory as compared to the available
number of frames in the memory. Allocation of the limited amount of frames to each process.
• Whenever any process with high priority arrives in the memory and if the frame is not freely
available at that time then the other process that has occupied the frame is residing in the frame will
move to secondary storage and after that this free frame will be allocated to higher priority process.
• We can also say that as soon as the memory fills up, the process starts spending a lot of time for the
required pages to be swapped in. Again the utilization of the CPU becomes low because most of the
processes are waiting for pages.
• Thus a high degree of multiprogramming and lack of frames are two main causes of thrashing in the
Operating system.
For Video Lecture:-https://www.youtube.com/watch?v=j2QujhrwLYA
Reference Book :- Operating System Concepts (8th Edition) Abraham Silberschatz, Peter Baer Galvin, and Greg Gagne Page No. -
386-391.

Locality of Reference
 Locality of reference refers to the tendency of the computer program to access
the same set of memory locations for a particular time period. The property of
Locality of Reference is mainly shown by loops and subroutine calls in a
program.
• On an abstract level there are two types of localities which are as follows −
• Temporal locality
• Spatial locality
• Temporal locality
• This type of optimization includes bringing in the frequently accessed memory
references to a nearby memory location for a short duration of time so that the
future accesses are much faster.

Locality of Reference
• Spatial locality
This type of optimization assumes that if a memory location has been accessed it
is highly likely that a nearby/consecutive memory location will be accessed as
well and hence we bring in the nearby memory references too in a nearby memory
location for faster access.

Numerical Problems
Q1.Consider the following system:
Number of pages = 2k,Page size = 4k words and Physical address = 18 bits
Calculate the logical address space (LAS) and number of frames.
Sol. Number of pages = LAS/page size
• So, LAS = Number of pages * page size
• LAS = (2k *4k) words = 211 * 212 words= 223 words = 8M words
• Number of frames = PAS/frame size=218/212
• Because frame size = page size, the number of frames is 2 6 frames = 64 frames.
Q2. Consider a system with page fault service time (s) = 100 ns, main memory access time (M) = 20
ns, and page fault rate (P) =65%. Calculate effective memory access time.
Sol. EMAT = P * S + (1 -P) * M
• = 0.65 * 100 + (1 – 0.65) * 20
• = 0.65 * 100 +0.35 * 20
• = 65 + 7 =72 ns

Numerical Problems
Q3. Consider a system with LA = 32 bits, physical address space (PAS) = 64 MB and page size is 4
KB. The memory is byte addressable. Page table entry is 2 bytes. What is the approximate page
table size?
Sol. LA=32 bits. So, LAS =232 bytes
• Number of pages = LAS/ Page size = 232/212 = 220
• Page table size = Number of entries * Page table entry size
• 220 * 2 bytes = 2MB (because number of page table entries = number of pages)
Q4. Consider a system with TLB access time 20 ns and main memory access time 100 ns. Calculate
effective memory access time if TLB hit ratio is 95%.
Sol. Given that C = 20ns, M = 100ns, X = 95%. Without TLB effective memory access time
• EMAT = 2M = 2 * 100 = 200ns
• With TLB, effective memory access time
• EMAT = X(C + M) + (1- X) (C + 2M)
= 0.95(20 + 100) + (1 – 0.95) (20 + 2 * 100) = 114 + 11 = 125ns.

Daily Quiz for Module 4 (Thrashing)
For formative assessment 4 (10 Questions through Google Quiz)
https://docs.google.com/forms/d/e/
1FAIpQLSdsUDs1JSLT_04DIWS7UoSn4CyswTRFbUVrDV3Yn2AmYA6quA/viewform?usp=sf_link

Daily Quiz (Unit-4)
Q1. Consider a virtual memory system with FIFO page replacement policy. For an arbitrary page
access pattern, increasing the number of page frames in main memory will (GATE CS 2001)
a) Always decrease the number of page faults b) Always increase the number of page faults
c) Some times increase the number of page faults d) Never affect the number of page faults
Answer: (c)
Q2. Suppose the time to service a page fault is on the average 10 milliseconds, while a memory access
takes 1 microsecond. Then a 99.99% hit ratio results in average memory access time of (GATE CS
2000)
(a) 1.9999 milliseconds (b) 1 millisecond
(c) 9.999 microseconds (d) 1.9999 microseconds
Answer: (d)
Q3. The minimum number of page frames that must be allocated to a running process in a virtual
memory environment is determined by (GATE CS 2004)
a) the instruction set architecture b) page size
c) physical memory size d) number of processes in memory
Answer (a)

Weekly Assignment (UNIT-4 )
Q1. Consider the following reference string 1,3,2,4,0,1,7,4,0,2,3,5,1,0,7,1,0,2.How many page
faults will occur for:
 FIFO Page Replacement
 LRU Page Replacement
 Optimal Page Replacement
Assuming three and four frames (initially empty). [CO4]
Q2. What is thrashing? State the cause of thrashing and discuss its solution.
[CO4]
Q3. Differentiate between Paging and Segmentation with their advantages and disadvantages.
[CO4]
Q4. Differentiate between internal and external fragmentation. [CO4]
Q5. Discuss the paging and segmentation with their advantages and disadvantages .
[CO4]

Weekly Assignment (UNIT-4 )
Q6. Consider a reference string: 4, 7, 6, 1, 7, 6, 1, 2, 7, 2. the number of frames in the memory is 3.

Find out the number of page faults respective to:
 Optimal Page Replacement Algorithm
 FIFO Page Replacement Algorithm
 LRU Page Replacement Algorithm

Faculty Video Links, YouTube & NPTEL Video Links and Online
Courses Details
Youtube/other Video Links
1.https://www.youtube.com/watch?v=kt4LkPFt8Zg
2.https://www.youtube.com/watch?v=Ub4VVDGLJx0
3.https://www.youtube.com/watch?v=njXBgjdn--Y
4.https://www.youtube.com/watch?v=xD5PB_g1rIE
5.https://www.youtube.com/watch?v=j2QujhrwLYA
6.https://www.youtube.com/watch?v=UDPYpf-nsDY
7.https://www.youtube.com/watch?v=lWVQsld8hMI
8.https://www.youtube.com/watch?v=CmTMr_x3NwY
9.https://www.youtube.com/watch?v=zDxEctO31TA
10.https://www.youtube.com/watch?v=kt4LkPFt8Zg&t=165s
11.https://www.youtube.com/watch?v=xD5PB_g1rIE
12.https://www.youtube.com/watch?v=ujoJ7J_l9cY
13.https://www.youtube.com/watch?v=lgmws9oraXE

MCQs
MCQ Link:-
1. https://www.sanfoundry.com/operating-system-questions-answers-memory-management/
2. https://www.sanfoundry.com/operating-system-mcqs-memory-allocation-1/
3. https://www.sanfoundry.com/operating-system-mcqs-memory-allocation-2/
4. https://www.sanfoundry.com/operating-system-mcqs-memory-management-paging-1/
5. https://www.sanfoundry.com/operating-system-mcqs-memory-management-swapping-1/
6. https://www.sanfoundry.com/operating-system-mcqs-memory-management-segmentation/
7. https://www.sanfoundry.com/operating-system-questions-answers-virtual-memory/
8. https://www.sanfoundry.com/operating-system-mcqs-virtual-memory-page-replacement-algorithms-
1/

Glossary Questions
Choose the correct option:

1CPU fetches the instruction from memory according to the value of ____________
2 A memory buffer used to accommodate a speed differential is called ____________
3. Run time mapping from virtual to physical address is done by ____________
4. The address of a page table in memory is pointed by ____________
The page table contains ____________
(program counter, cache, Memory management unit, page table base register, base
address of each page in physical memory)

Old Question Papers

Old Question Papers

Old Question Papers

Old Question Papers

Old Question Papers
Last 12 Years University paper Link:-
https://drive.google.com/drive/folders/1UPXvZ7NY09OunSLrEkTFWpw_M3xLzjhs?
usp=sharing

Expected Questions for University Exam
1. Explain paging. Describe how logical address is translated to physical address in a paged system.
2. Explain thrashing. State the cause of thrashing and discuss its solution
3. Differentiate between internal fragmentation and external fragmentation.
4. Define Belady’s anomaly.
5. Differentiate between the paging and segmentation.
6. When do page faults occur? Describe in detail the actions taken by the operating system when a page
faults occur.
7. Consider the following reference string 1,3,2,4,0,1,5,6,0,1,2,3,0,5,6,4,2,1,3,2.7,3,2.
How many page faults will occur for:
• FIFO Page Replacement
• Optimal Page Replacement
• LRU Page Replacement
Assuming three and four frames (initially empty)

Recap of Unit

References
Books :
1.Silberschatz, Galvin and Gagne, “Operating Systems Concepts”, Wiley
2. SibsankarHalder and Alex A Aravind, “Operating Systems”, Pearson Education
3. Harvey M Dietel, “ An Introduction to Operating System”, Pearson Education
4. D M Dhamdhere, “Operating Systems : A Concept basedApproach”, McGraw Hill.
5.Charles Crowley, “Operating Systems: A Design-Oriented Approach”, Tata McGraw Hill
Education”.
6. Stuart E. Madnick & John J. Donovan, “ Operating Systems”, Tata McGraw


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Noida Institute of Engineering and Technology, Greater Noida

Memory Management System

Rajeev Kumar ACSE0403A OS Unit 4 1

June 1, 2024 Rajeev Kumar ACSE0403A OS Unit 4 2

June 1, 2024 Rajeev Kumar ACSE0403A OS Unit 4 3

June 1, 2024 Rajeev Kumar ACSE0403A OS Unit 4 4

UNIT-IV Memory Management

June 1, 2024 Rajeev Kumar ACSE0403A OS Unit 4 5

These Requirements of memory management are:

For Video Lecture:- https://www.youtube.com/watch?v=UDPYpf-nsDY

June 1, 2024 Rajeev Kumar ACSE0403A OS Unit 4 6

Figure :- A base and a limit register define a logical address space

Figure:- Hardware address protection with base and limit registers.

June 1, 2024 Rajeev Kumar ACSE0403A OS Unit 4 8

June 1, 2024 Rajeev Kumar ACSE0403A OS Unit 4 9

Figure:- Multistep processing of a user program.

For Video Lecture:- https://www.youtube.com/watch?v=CmTMr_x3NwY

 Hardware device that at run time maps virtual to physical address

June 1, 2024 Rajeev Kumar ACSE0403A OS Unit 4 12

 Routine is not loaded until it is called

Figure:- Dynamic relocation using a relocation register.

For video lecture :-

June 1, 2024 Rajeev Kumar ACSE0403A OS Unit 4 15

• The choice between Static or Dynamic Loading is to be made at the time of

June 1, 2024 Rajeev Kumar ACSE0403A OS Unit 4 17

A process can be swapped temporarily out of memory to a backing store, and

Total physical memory space of processes can exceed physical memory

 Roll out, roll in – swapping variant used for priority-based scheduling

June 1, 2024 Rajeev Kumar ACSE0403A OS Unit 4 18

Figure:- Swapping of two processes using a disk as a backing store.

June 1, 2024 Rajeev Kumar ACSE0403A OS Unit 4 19

1. What are need of memory management.

June 1, 2024 Rajeev Kumar ACSE0403A OS Unit 4 20

6. Binding of instructions and data to memory addresses can be done at ____________

June 1, 2024 Rajeev Kumar ACSE0403A OS Unit 4 21

June 1, 2024 Rajeev Kumar ACSE0403A OS Unit 4 22

June 1, 2024 Rajeev Kumar ACSE0403A OS Unit 4 23

Topic Name Course Outcome

June 1, 2024 Rajeev Kumar ACSE0403A OS Unit 4 24

• To explore various techniques of allocating memory to processes.

June 1, 2024 Rajeev Kumar ACSE0403A OS Unit 4 25

 Main memory must support both OS and user processes

For video lecture :-https://www.youtube.com/watch?v=IwESijQs9sM

June 1, 2024 Rajeev Kumar ACSE0403A OS Unit 4 26

For video lecture:- https://www.youtube.com/watch?v=zDxEctO31TA

June 1, 2024 Rajeev Kumar ACSE0403A OS Unit 4 27

Figure:- Hardware support for relocation and limit registers.

June 1, 2024 Rajeev Kumar ACSE0403A OS Unit 4 28

Degree of multiprogramming is limited by number of partitions

 Variable-partition sizes for efficiency (sized to a given process’ needs)

When a process arrives, it is allocated memory from a hole large enough to

June 1, 2024 Rajeev Kumar ACSE0403A OS Unit 4 29

Figure:- Fixed & Unfixed memory partitions.

June 1, 2024 Rajeev Kumar ACSE0403A OS Unit 4 30

• First-fit: Allocate the first hole that is big enough

For Numerical video lecture :-https://www.youtube.com/watch?v=N3rG_1CEQkQ

• Fragmentation is an unwanted problem where the memory blocks cannot be

June 1, 2024 Rajeev Kumar ACSE0403A OS Unit 4 32

Effective memory access time = h1t1 + (1-h1)h2*t2+