Digital Logic Design

Lecture – 9

Slides Credits: Dr. Muhammad Taha Jilani

 Recap (Before Mid terms)
Design Techniques of Combinational Circuits
• Gates, Timing Diagrams, Truth Tables
• Boolean Laws Rules, DE Morgan's Law
• SOP, POS, K-Map Minimization

Functions of Combinational Logic

• Athematic Circuits  Adders/ Subtractors, Multipliers
• Code converters, Gray Codes, BCD Codes
• Encoder / Decoder, 7-segment Decoder
• Multiplexers / Demultiplexers, Special Combinational Circuits

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SEQUENTIAL LOGIC CIRCUIT
Chapter 7, Page 387 11th E

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Flip-flops and latches are both digital circuits used to store data, but
they have some key differences:
1. Flip-flops:
- Have a clock input (CLK) that controls when the data is stored.
- Data is stored only when the clock signal is high (or low, depending
on the type).
- Can be either level-triggered (e.g., SR flip-flop) or edge-triggered
(e.g., D flip-flop).
2. Latches:
- Do not have a clock input.
- Data is stored as soon as the input signals change.
- Are level-sensitive, meaning the output changes as soon as the input
changes.
In summary, flip-flops are clock-controlled, while latches are not. Flip-
flops are used in sequential logic circuits, while latches are used in
combinational logic circuits.
 Sequential Logic
Introduction
• So far we have studied combinational circuits, i.e. the output at any instant of time
is entirely dependent on its inputs.
• However, in practice, various systems also include memory and timing elements,
they called Sequential Logic (Some Examples?).

Feeback path

Sequential Logic – block diagram

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 Sequential Logic
Introduction
• Individual Sequential Logic circuits can be used to build more complex circuits such
as Multivibrators, Counters, Shift Registers and Memories.
• Multivibrators, has three types of logic devices :
– Monostable, and
– Astable
– Bistable,

• Monostable Multivibrator, has only one stable state.

– One stable state: e.g. pulse of a specific duration (a single controlled-width pulse when
activated or triggered).

• Astable Multivibrator has no stable state

– No stable state: but switches continuously between two states, providing a pulse-train
• Used as an oscillator or waveform generator like, 555 timer .

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 Sequential Logic

• Bistable Multivibrator devices have two stable states, called SET and
RESET; they can retain either of these states indefinitely, making them
useful as storage devices.
– Two Stable states: Triggered by inputs
• Two categories of bistable devices
– Latch
– Flip-flop
• The basic difference between latches and flip-flops is the way in which they
are changed from one state to the other.

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Sequential Logic

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Sequential Logic

LATCHES

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 Latches

• Latch is the bistable devices that can reside in either of two

states using a feedback arrangement.
– The Latch can be designed either by
• two cross-coupled NAND gates or
• two-cross coupled NOR gates

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 Latches
• Set-Reset Latch (SR Latch)
There are two types of SR latches
– An active-HIGH input S-R latch is formed with two cross-coupled NOR gates.
– An active-LOW input S-R latch is formed with two cross-coupled NAND gates.

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 Latches
• Set-Reset Latch (SR Latch)
– An active-HIGH input S-R latch – also define as, when S = 1 it is in SET
condition
or Q = 1
G1

G2

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 Latches
• Set-Reset Latch (SR Latch)
– An active-LOW input S-R latch– also define as, when S = 0 it is in SET condition
or Q = 1
G1

G2
NOR as NAND gate

Recalling property
of NAND, output is 1
when at least one
of the inputs is 0 Self Reading
Flyod,
10e Pg: 292
11e Pg: 389-390

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 Latches
• Set-Reset Latch (SR Latch)
– An active-HIGH input S-R latch is formed with two cross-coupled NOR
gates.
Assuming S = 1 and R = 0
G1 Recalling property of NOR, output is 0 when at
least one of the inputs is 1.

So when S is applied as 1 the output of gate

G2 G2 i.e. is 0 irrespective of the condition of
second input Q to the gate.

Now Q’ input of gate G1 so both the inputs of

In normal operation, the outputs of a
latch are always complements of each
other.
G1 become 0 as R is already 0. So, output of
G1 is now1
Therefore, with S = 1 and R = 0,
Q’ = 0 and Q = 1
This is called SET condition

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 Latches
• Set-Reset Latch (SR Latch)
– An active-HIGH input S-R latch is formed with two cross-coupled NOR
gates.
G1 Now, it will remain in same state until, R changes
Now assume S = 0 and R = 1
(Again NOR is 0 when any inputs is 1)

G2 So when R is applied as 1, the output of gate G1

i.e. Q is 0 irrespective of the condition of second
input Q’ to the gate.

So, whatever may be the previous condition of Q,

it always becomes 0 this 0 is then fed back to input
of gate G2. As here S is already 0, both inputs of
G2 are 0.
Therefore, with S = 0 and R = 1,
Q’ = 1 and Q = 0
This is called RESET condition
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 Latches
• Set-Reset Latch (SR Latch) Keeping SET / RESET in mind,
if S = 0 and also R = 0, Q remains same as it was.
G1
First suppose Q is previously 1.

Now the inputs of G2 are 0 and 1 as S=0 and Q=1. So output of

G2 G2 i.e. Q’ is or 0.

Now both inputs of G1 are 0 as R=0 and Q’=0. So output of G1

i.e. Q is or 1.

Now suppose Q is previously 0.

Now both inputs of G2 are 0 and 1 as S=0 and Q=0. So output of

G2 i.e. Q’ is 1.

Now the inputs of G1 are 0 and 1 as R=0 and =1. So output of G1

i.e. Q is 0.

So it is proved that Q remains same as it is when S = 0 and also

R = 0 in S R latch
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 Latches
• Set-Reset Latch (SR Latch) If S = 1 and also R = 1,
the condition of Q is Invalid
G1
First suppose Q is previously 1.

Now both inputs of G2 are 1 as S=1 and Q=1. So output of G2 i.e.

G2 Q’ is or 0.

Now the inputs of G1 are 1 and 0 as R=1 and Q’ =0. So output of

G1 i.e. Q is or 0. That means Q is changed.

Now Q is 0. So inputs of G2 are 1 and 0 as S = 1 and Q = 0. So

output of G2 i.e. Q’ is or 0. That means Q’ is unchanged.

Now the inputs of G1 are 1 and 0 as R=1 and Q’ =0. So output of

G1 i.e. Q is or 0. That means Q is unchanged.

So, when both S and R are 1, it becomes unpredictable whether

the value of output Q will be changed or unchanged.
This condition of S R latch normally avoided.

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 Latches
• Set-Reset Latch (SR Latch)
– An active-HIGH input S-R latch – also define as, when S = 1 it is in SET
condition
or Q = 1
G1

G2

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 Latches
• Set-Reset Latch (SR Latch)
– An active-LOW input S-R latch– also define as, when S = 0 it is in SET condition
or Q = 1
G1

G2
Negative-OR as NAND
gate

Recalling property
of NAND, output is 1
when at least one
of the inputs is 0 Self Reading
Flyod,
10e Pg: 292
11e Pg: 389-390

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 Latches
• Set-Reset Latch (SR Latch)
– These Latches (either, active-LOW/HIGH inputs) are asynchronous latches.
– Since they change its state instantaneously on the application of required
inputs conditions.

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 Latches
• Gated Latches
– There is another type called “Gated Latches” and they are considered as
synchronous latches.
– They only change its output state when there is an enabling signal (third input)
along with required two inputs.

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 Latches
• Gated SR Latch / SR Latch with Control Input
– In gate latch, there is additional input called Gate or Enable input, EN
– In the Gated latch inputs can only act upon when the latch is enabled
otherwise there will be no change in output state even required inputs are
applied
– EN used to control the state to which the latch operate, for SR Latch
• When EN is HIGH, latch will be SET condition
• Otherwise it will be in RESET condition
• Invalid when, both inputs and EN is high

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 Latches
• Gated SR Latch
– EN used to control the state to which the latch operate, for SR Latch
• When EN is HIGH, latch will be SET condition
• Otherwise it will be in RESET condition
• Invalid when, both inputs and EN is high

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 Latches
• Gated D Latch / Transparent Latch
– Gated D Latch is different from Gated SR latch
– It has only one input “D” (data), in addition it has “EN” (Enable) input
that controls the output,
• When the D input is HIGH and the EN input is HIGH, the latch will SET.
• When the D input is LOW and EN is HIGH, the latch will RESET.

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 Latches
• Gated D Latch
– It has only one input “D” (data), in addition it has “EN” (Enable) input that
controls the output,
• When the D input is HIGH and the EN input is HIGH, the latch will SET.
• When the D input is LOW and EN is HIGH, the latch will RESET.

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 Latches
• Exercise
– Type?
– Find Q?

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 Latches
• Exercise
– Type?
– Find Q?

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 Latches
• Exercise
– Type?
– Find Q?

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Sequential Logic

FLIP-FLOPS

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 Flip-Flops
Problem with Latches
• When latches are used for the storage elements, a serious difficulty arises.
– The state transitions of the latches start as soon as the clock pulse changes to the logic-1
level.
– The new state of a latch may appear at its output while the pulse is still active. This
output is connected to the inputs of some of the latches through a combinational circuit.
– If the inputs applied to the latches change while the clock pulse is still in the logic-1
level, the latches will respond to new state values of other latches instead of the
original state values, and a succession of changes of state instead of a single one may
occur.
• The result is an unpredictable situation, since the state may keep changing
and continue to change until the clock returns to 0. The final state
depends on how long the clock pulse stays at the logic-1 level.
– Flip-flop handle this issue by triggering only at transition (either 0→1 or 1→0)

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 Flip-Flops
Problem with Latches
• Latches = Level Triggering

• Flip-Flops = Edge Triggering

Edges

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 Flip-Flops
• As the logic-gates are the basic building block of Combinational
circuits, similarly, Flip-flops are the basic building block of
Sequential circuits.
• Since it is a bistable multivibrator, it can remain in either of the
states indefinitely period of time, until the state is changed by
applying the triggering or Clock signal (often called Dynamic input).
– It is a control inputC , that is, changes in the output occur in synchronization
with the clock.
– It is a edge triggerd signal, either, leading or trailing edge
• Due to this attribute it is called synchronous device.
• Flip flop is one-bit memory element.

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 Flip-Flops
• An edge-triggered flip-flop changes state either at the positive edge
(rising edge) or at the negative edge (falling edge) of the clock pulse
and is sensitive to its inputs only at this transition of the clock.
• The basic type is SR-FF, but it is not available in IC form

positive edge-triggered
rising edge-triggered

Using NAND

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 Flip-Flops
• An edge-triggered flip-flop changes state either at the positive edge
(rising edge) or at the negative edge (falling edge) of the clock pulse
and is sensitive to its inputs only at this transition of the clock.
• The basic type is SR-FF, but it is not available in IC form

positive edge-triggered C
rising edge-triggered

Using NOR

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 Flip-Flops
• An edge-triggered flip-flop changes state either at the positive edge
(rising edge) or at the negative edge (falling edge) of the clock pulse
and is sensitive to its inputs only at this transition of the clock.
• Two types of edge-triggered flip-flops, commonly available:
– D flip-flops
– JK flip-flops

positive edge-triggered
rising edge-triggered

negative edge-triggered
falling edge-triggered

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 Flip-Flops
• Edge triggered D-type flip-flops
Remember?

D-Latch

D formed by SR

Pulse transition detector:

36
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 Flip-Flops
D flip-flops
• It has only one input in addition to Control/Enable input
• The operation is similar to SR FF, as the sinlgle input D is connected to the
input “S” of FF and the “R” input is achieved by inverting the D..
• With the triggering edge at Control, if D is HIGH, the Q output goes HIGH and it
is in SET condition.
• With the triggering edge at Control, if D is LOW, the Q output goes LOW, and the
flip-flop is RESET.
• Output follows “D” as long as the “Control” remain HIGH, but when it becomes
LOW, the output will be remain same as “D” was during that transition.
S

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 Flip-Flops
D flip-flops
S
Characteristic / Function table

Remember, flip-flop cannot change state except on

the triggering edge of a clock pulse

Examples:

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 Flip-Flops
D flip-flops
• Determine the Q output?

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 Flip-Flops
JK flip-flops
• It has two inputs in addition to Control input, also based on SR-FF
• J is connected to the input “S” of FF and the K is is connected to the input
“R”
• With the triggering edge of the clock pulse, When J is HIGH and K is LOW, the Q output
goes HIGH and the flip-flop is SET.
• With the triggering pulse, when J is LOW and K is HIGH, the Q output goes LOW and the
flip-flop is RESET.
• When both inputs are HIGH, the circuit goes to complement (State changed, i.e. if Q=1,
now Q=0, vice-versa)
• When both J and K are LOW, the output does not change from its prior state.

43
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 Flip-Flops
JK flip-flops
• It has two inputs in addition to Control input
Characteristic / Function table
R

Examples:

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 Flip-Flops
JK flip-flops
• It has two inputs in addition to clock, Find Q?
• Present state is LOW

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 Flip-Flops
Circuit using Flip-Flops
– For more than one bit circuit?
• we need to Cascade FFs

– How more than one FFs will be connect to form a circuit?

• Yes it involve combinational circuits

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 Flip-Flops
Flip-Flop Applications
• Parallel Data Storage

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 Flip-Flops
Flip-Flop Applications
• Frequency Division (divide-by-2 device )

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 Flip-Flops
Flip-Flop Applications
• Frequency Division (divide-by-4 device )

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 Flip-Flops
Flip-Flop Applications
• Frequency Division (divide-by-8 device )

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 Flip-Flops
Flip-Flop Applications
• Counting

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 Flip-Flops
Flip-Flop Applications
• Counting

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