19EE44

LINEAR INTEGRATED
CIRCUITS

Dr. A. Kavithamani
ASSOCIATE PROFESSOR /
EEE / CIT
Syllabus

COURSE OBJECTIVE: To educate the students about the concepts of linear integrated circuits, and use
of op-amp and other linear ICs in various applications.

COURSE OUTCOMES: After successful completion of this course, the students will be able to,
CO1: Summarize the DC/AC characteristics and compensation techniques of an operational amplifier
CO2: Understand the working and design of various linear applications using op-amp IC741.
CO3: Understand the working and design of various non - linear applications using opamp IC741.
CO4: Understand the working and design of analog circuits such as voltage regulator, VCO and multi -
vibrators using other linear IC's.
CO5: Design of analog computation and signal conditioning circuits using op-amps.
Syllabus

OVERVIEW OF INTEGRATED CIRCUIT TECHNOLOGY (video/animation to be displayed and discussed)

Silicon Semiconductor Technology - Wafer processing, Oxidation, Epitaxy, Deposition, Ion implantation
Diffusion and Metallization - Basic CMOS processing technology - N-well, P-well process - Twin tub
process and Silicon on insulator - Circuit Elements - Resistors, Capacitors and Thin film transistors.
(3)
OPERATIONAL AMPLIFIER CHARACTERISTICS
Functional block diagram - Analysis of typical op-amp - Equivalent circuit - Open loop gain - CMRR - Input
bias and off set currents - Input and Output off set voltages - Off set compensation techniques - Frequency
response - Noise - Stability - Limitation - Frequency compensation techniques - Slew rate.
(9)
OPERATIONAL AMPLIFIER APPLICATIONS
DC and AC Amplifier - Inverting and Non-inverting amplifier - Summing, Scaling and Averaging amplifier -
Voltage follower - Differential amplifier - Instrumentation amplifier - Voltage to Current and Current to
Voltage converters - Integrator and Differentiator - Practical considerations - Active filters and Oscillators.
(9)
Syllabus

COMPARATORS AND CONVERTERS

Comparator- Zero crossing detector - Schmitt trigger - Voltage to Frequency and Frequency to Voltage
converters - Sample and Hold circuit - D/A converters - A/D converters - Precision rectifiers - Peak
detectors - Clipper and Clamper - Log and Antilog amplifier - Multiplier and Divider- Wave form generators.
(9)
OTHER LINEAR IC APPLICATIONS
Voltage regulators – IC 7805 - IC 723 - Current limiting and Current boosting - Fixed and Adjustable three
terminal regulators – SMPS ICs - PLL - Applications - IC 566 Voltage controlled oscillators - IC 555 timer -
Monostable and Astable mode of operations - Applications. (9)

ANALOG COMPUTATION AND SIGNAL CONDITIONING

Solution to integro-differential equations, Signal conditioning of low magnitude signals from sensors –
instrumentation amplifier design, filter design, analog buffers, analog interfacing circuits for
microcontrollers. (6)
Syllabus

TEXT BOOKS:
1. RamakantA.Gayakward, “Op-Amps and Linear Integrated Circuits”, 4th Edition, Prentice Hall of India,
New Delhi, 2015.
2. 2. Coughlin F.R. and Driscoll F.F., “Operational Amplifiers and Linear Integrated Circuits”, 6th Edition,
Prentice Hall of India, New Delhi, 2001.
REFERENCES:
3. Roy Choudhury D and Shail Jain., “Linear Integrated Circuits”, 5th Edition, New Age Science Ltd.,
2018.
4. Sergio Franco, “Design with Operational Amplifiers and Analog and Integrated Circuits”, 3rd Edition
Tata McGraw Hill Publishing Co., New Delhi, 2012.
5. Michael Jacob J., “Analog Integrated Circuit Applications”, 1st Edition, Prentice Hall of India, New Delhi,
2007.
6. Sidney Soclof, “Design & Application of Analog Integrated Circuits”, Prentice Hall of India, 1997.
7. David A. Bell, “Operational Amplifiers and Linear ICs”, 3rd Edition, Oxford University Press, 2011.
OVERVIEW OF INTEGRATED CIRCUIT TECHNOLOGY

Monolithic integrated circuits

- contain active and passive devices that are made on the
surface of a single piece of crystal silicon

- the various processes usually take place through a

single plane and therefore the technology is referred to as
planar technology
Basic planar processes

1. Silicon wafer (substrate) preparation

2. Epitaxial growth
3. Oxidation
4. Photolithography
5. Diffusion
6. Ion implantation
7. Isolation techniques
8. Metallization
9. Assembly packaging and processing
Basic planar processes

1. Silicon wafer (substrate) preparation

Wafer is a thin slice of semiconducting material such as silicon crystal upon
which active and passive devices are fabricated.
Steps:
i) Crystal growth and doping
ii) Grinding and Slicing
iii) Lapping and Etching
iv) Wafer polishing and cleaning
1. Silicon wafer (substrate) preparation

• Starting material is highly purified polycrystalline silicon

• Czochralski cyrstal growth process
• polycrystalline silicon together with an appropriate amount of dopant is put in a quartz crucible and then placed in a
furnace.
• Heated to temperature of 1420 deg c. (Si melting point)
• Seed crystal (small rod of Si) is dipped into the silicon melt and slowly pulled out.
• As the seed crystal is pulled out of the melt, it brings with it a solidified mass of Si with same crystalline structure as
that of seed crystal.
• Diameter 10 to 15 cm ; Length 100 cm; Thickness 16-32 mils (1 mil =0.0254mm)
• Orientation flat is reference for various processes
https://www.youtube.com/watch?v=AMgQ1-HdElM
https://www.youtube.com/watch?v=35jWSQXku74
https://www.youtube.com/watch?v=AcDn4bvW5IU
2. Epitaxial growth

Epi means upon. Taxy means

arranged.
Epi taxy- arranging atoms in a single
crystal fashion.so that resulting
layer is an extension of the substrate
crystal structure.
SiCl4 + 2H2 --> Si + 4 HCl

All the components required for the

circuit are built on top of this layer.
10
3. Oxidation
• SiO2 prevents diffusion of impurities through it.
• It is a extremely hard protective coating and is unaffected by all reagents except hydrofluoric acid. Thus
it stands against any contamination.
• Selective etching of SiO2 can be done to define windows so that impurities can be diffused to fabricate
various components.
• Silicon wafers are stacked in a quartz boat and inserted into a quartz furnace tube.
• Temperature : 950- 1115 deg C
• Exposed to gas containing O2 or H2O or both
Si + O2 → SiO2
or
Si + 2H2O → SiO2 +H2
• Thickness depends on time, temperature and moisture content.
• Thickness: 0.02 to 0.2 micrometer
4.Photolithography and Etching

• Simple layers of thin films do not make a device.

• To create a device such as a transistor, layers of thin films have to
be patterned, etched and coated.
• Lithography combines these processes and can create millions of
devices in batch.
• Lithography is the transfer of geometric shapes on a mask to a
smooth surface.
• In modern semiconductor manufacturing, photolithography uses
optical radiation to image the mask on a silicon wafer using
photoresist layers. 12
4.Photolithography and Etching

• Using photolithography microscopically small circuit can be fabricated.

• On a 1 cm X 1cm chip 10,000 transistors can be fabricated.
• Device dimension less than 1µm can be fabricated.

• Photolithography involves two processes, namely:

• I. Making of a photographic mask
1. preparation of initial artwork (500 times larger than the final dimension)

2. its reduction (decomposed into several layers corresponding to

process step in the fabrication schedule)

• II. Photo etching

4.Photolithography and Etching- Positive and Negative Photoresist

● The photoresist is exposed with UV light wherever the

underlying material is to be removed.

● In positive photoresists, exposure to the UV light changes the

chemical structure of the resist so that it becomes more
soluble in the developer. The exposed resist is then washed
away by the developer solution, leaving windows of the bare
underlying material. In other words, "whatever shows, goes."

● The mask, therefore, contains an exact copy of the pattern

which is to remain on the wafer.
4.Photolithography and Etching- Positive and Negative Photoresist

● Negative resists behave in just the opposite manner.

Exposure to the UV light causes the negative resist to
become polymerized, and more difficult to dissolve.
Therefore, the negative resist remains on the surface
wherever it is exposed, and the developer solution removes
only the unexposed portions.

● Masks used for negative photoresists, therefore, contain the

inverse (or photographic "negative") of the pattern to be
transferred.
Steps of photolithography

16
5. Diffusion (introducing impurities)

process of introducing impurities in silicon chip.

Uses high temperature furnace.
Quartz boat with 20 wafers is pushed into the hot zone with 1000°C
Sources - B₂O₃, BCl₃, P₂O₅ and POCl₃ (phosphoryl chloride).
Depth of diffusion depends on the time of diffusion (extends to 2 hrs).
Diffusion takes place both laterally and vertically.
6.Ion Implantation (introducing impurities)

• In the ion implantation charged dopants (ions)

are accelerated in an electric field and
irradiated onto the wafer. The penetration
depth can be set very precisely by reducing or
increasing the voltage needed to accelerate
the ions. Since the process takes place at
room temperature, previously added dopants
can not diffuse out.
• Wafers are placed in vacuum chamber and
are scanned by beam of high-energy dopant
ions.

18
6.Ion Implantation

ion source: the dopants in gaseous state (e.g. boron

trifluoride BF3) are ionized
lenses: lenses are distributed inside the entire system to
focus the ion beam
mass separation: the charged particles are deflected by
a magnetic field by 90 deg. Too light/heavy particles are
deflected more/less than the desired ions and trapped
with screens behind the separator
accelerator: the ions are drawn with approximately 30
keV out of the ion source
deflectors: the ions are deflected (Y axis and X axis
deflection Plates) with electrical fields to irradiate the
desired location
wafer station: the wafers are placed on large rotating
wheels and held into the ion beam
19
7. Isolation technique

The individual components that make up the circuit on a

monolithic die need to have electrical isolation from each other
in order to function.
Two methods of isolation in Integrated circuits are

1. PN JUNCTION ISOLATION

By doping two adjacent regions with opposite types of

conductivity and providing them with adequate reverse biasing,
they become effectively isolated from each other.

2. DIELECTRIC ISOLATION

• Layer of solid dielectric (silicon dioxide or ruby) surrounds

each component, producing isolation, both electrical and
physical.
• It requires additional fabrication steps, so it is expensive.
• Used for fabricating Professional grade IC’s required for
specialised applications (aerospace and military).
• High cost is justified by superior performance.
8. Metallization

• It produces a thin metal film layer that makes interconnection of

components on the chip.
• Aluminium is mostly used because
 Relatively good conductor.
 Easy to deposit aluminium films.
 Makes good mechanical bonds with silicon.
 Forms low resistance, non-rectifying contact with p-type and n-
type silicon.
• Film thickness – 1 µm; Conduction width – 2 to 25 µm
• Material to be evaporated is placed in a resistance heated tungsten coil or
basket.
• Very high power density electron beam is focused at the surface of the
material to be evaporated.
• It heats up the material to very high temperature and it starts vaporising.
• The evaporated molecules hit the substrate and condense to form thin
film coating.
• The film is patterned to produce interconnections and bonding pad
configuration.
• It is done by photolithographic process and Al is etched by Phosphoric
acid.
9. Assembly packaging and processing
9. Assembly packaging and processing

Wafer contains several hundred chips, each being a

complete circuit.
So it is separated and individually packaged.
Scribing and Cleaving are used for separation that uses
diamond tipped tool to cut lines into the surface of wafer.
Chip is mounted on ceramic wafer and attached to a
suitable package.
Different package configuration
Metal can package
Ceramic flat package
Dual-in-line package
Metal can packages – 8,10 or 12 leads, flat or dual-in-line
package – 8,14 or 16 leads, but even 24 or 36 or 42 leads
are available.
Ceramic packages (flat type or dual-in-line) are costly due
to fabrication process, but have advantage of best
hermetic sealing.
General purpose IC’s are dual-in-line plastic packages
due to economy.
24
Fabrication of NPN transistor

p Substrate

n epitaxial layer

E B C p diffusion

n+ diffusion

n+ n+
P Metal
n epi
P
Fabrication of NPN transistor

p Substrate
Top view

Front view
 n epitaxial layer

N type epitaxial layer is grown to

fabricate collector region
 SiO2 layer

After growing epitaxial layer the

SiO2 layer, is formed.
 Photoresist

After the formation of the SiO2

layer, positive photoresist is applied
to the surface of the wafer.
 Mask

Mask is aligned on the PR to provide

pn junction isolation
UV Light
Diffusion of p type impurities
p diffusion
To reduce the collector resistance in
the path between the epithelial
collector region and the surface. a
region of heavily duped (highly
conductive) N+ material is created in
the collector region.
n+ diffusion
Al –vacuum deposited over the entire
surface of the wafer
Undesired Al area are etched away
Metal
E B C
Fabrication of NPN transistor

p Substrate

n epitaxial layer

E B C p diffusion

n+ diffusion

n+ n+
P Metal
n epi
P
Fabrication of PN diode
E B C

n+ n+
P
n epi
P

K A

n+
P
n epi
P
Fabrication of Resistor
E B C

n+ n+
P
n epi
P

P P
n epi
P
Fabrication of Capacitor
E B C

n+ n+
P
n epi
P

n+
P
n epi
P
 5

4
1 2

86
 2 4
1 3 5

P n+ n+ n+ n+ P
P P

4
1 2

3
UV Light
 2 4
1 3 5
 2 4
1 3 5

P n+ n+ n+ n+ P
P P