DIGITAL LOGIC DESIGN

UNIT-2

Boolean Algebra & Logic

Gates
 COURSE OUTLINE
2
Boolean operations, Boolean functions, algebraic manipulations,
min-terms and max-terms,
sum-of-product and product-of-sum representations,
two-input logic gates,
NAND/NOR implementations,
Minimization of Boolean functions using Karnaugh map, don’t-care conditions,
prime implicants,
minimization of functions using Quine-McClusky method.
 LOGIC GATES
● Logic gates are the fundamental building blocks of digital systems.
● The name logic gate is derived from the ability of such a device to make decisions,
in the sense that it produces one output level when some combinations of input
levels are present, and a different output level when other combinations of input
levels are present.
● Inputs and outputs of logic gates can occur only in two levels. These two levels are
termed as HIGH and LOW, or TRUE and FALSE, or ON and OFF, or simply 1 and 0.

● There are three basic logic gates. AND, OR and NOT.

● There are two universal logic gates. NAND and NOR.
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● There are two derived logic gates. XOR and XNOR.
AND Gate:
• AND gate has two or more inputs but only one output.
• AND gate is a gate whose output is 1, if and only if all its inputs are 1.
• The symbol of AND operation is ‘.’
• The logic symbol, truth table and Boolean expression of a two input AND gate are
shown below.

Inputs Output Y = A.B

A B Y

0 0 0

0 1 0
1 0 0
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1 1 1
OR Gate:
• OR gate has two or more inputs but only one output.
• OR gate is a gate whose output is 1, if any one of the input is 1. Hence it is called
any or all gate.
• It can also be called an inclusive OR gate because it includes the condition ‘both the
inputs can be present’.
• The symbol of OR operation is ‘+’
• The logic symbol, truth table and Boolean expression of a two input OR gate are
shown below.
Inputs Output Y = A+B
A B Y
0 0 0
0 1 1
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1 0 1
1 1 1
NOT Gate:
• NOT gate has one input and one output.
• NOT gate is also called an inverter. It’s output is always the complement of input.
• The symbol of NOT operation is ‘-’ (bar).
• The logic symbol, truth table and Boolean expression of NOT gate are shown
below.

Input Output Y=

A Y

0 1

1 0

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NAND Gate:
• NAND gate has two or more inputs but only one output.
• NAND gate is a gate whose output is 0, if and only if all its inputs are 1.
• NAND means NOT AND. i.e., the AND output is NOTed.
• The logic symbol, truth table and Boolean expression of a two input NAND gate
are shown below.

Inputs Output Y=

A B Y

0 0 1

0 1 1
1 0 1
1 1 0 7
NOR Gate:
• NOR gate has two or more inputs but only one output.
• NOR gate is a gate whose output is 1, if all the inputs are 0.
• NOR means NOT OR. i.e., the OR output is NOTed.
• The logic symbol, truth table and Boolean expression of a two input NOR gate are
shown below.

Inputs Output Y=
A B Y

0 0 1

0 1 0
1 0 0
1 1 0 8
XOR Gate:
• XOR gate has two inputs but only one output.
• XOR gate is a gate whose output is 1, if both the inputs are different. Hence it is
called anti-coincidence gate or inequality detector.
• The logic symbol, truth table and Boolean expression of a two input XOR gate are
shown below.

Inputs Output Y= +
A B Y

0 0 0

0 1 1
1 0 1
1 1 0 9
XNOR Gate:
• XNOR gate has two inputs but only one output.
• XNOR gate is a gate whose output is 1, if both the inputs are same. Hence it is
called coincidence gate or equality detector.
• The logic symbol, truth table and Boolean expression of a two input XOR gate are
shown below.

Inputs Output + A.B

A B Y

0 0 1

0 1 0
1 0 0
1 1 1 10
11
Equivalent Gates:
NAND = Bubbled OR

AND = Bubbled NOR

NOR = Bubbled AND

OR = Bubbled NAND

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XOR gate as an inverter: XNOR gate as an inverter:

Inputs Output Inputs Output

A B Y A B Y

0 0 0 0 0 1

0 1 1 0 1 0
1 0 1 1 0 0
1 1 0 1 1 1

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Properties of Exclusive-OR Gate:

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Example – 1: Find the logical equivalent of the following expressions
a) A 0
b) A 1
c) Aʘ0
d) Aʘ1
e) 1
f) 0

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Example – 2: Find the logical equivalent of the following expressions
a) B
b) ʘB
c)
d) ʘ
e) A
f) Aʘ

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 BOOLEAN ALGEBRA
Some basic logical Boolean operations,
AND Operation OR Operation NOT Operation

Some basic laws for Boolean Algebra

A.0=0 A+0=A
A.1=A A+1=1 = A A double complement of a variable
A.A=A A+Ā=1 is always equal to the variable
A.Ā=0 A+A=A
AND Laws OR Laws Double Complementation Law 17
 BOOLEAN ALGEBRA
Commutative Laws
A+B=B+A
A.B=B.A

Associative Laws

Distributive Laws

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 BOOLEAN ALGEBRA
Idempotence Laws Transposition Theorem
A+A=A AB + = (A+C).(+B)
A.A=A
Identity Laws
A+1=1
A.1=A

Null Laws
A+0=A
A.0=0

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 BOOLEAN ALGEBRA
Redundant Literal Rule
Inputs Output Inputs Output
A B ĀB A + ĀB A B A+B
0 0 0 0 0 0 0
0 1 1 1 0 1 1
1 0 0 1 1 0 1
1 1 0 1 1 1 1

Absorption Laws
Inputs Output
A B AB A+A.B
0 0 0 0
0 1 0 0
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1 0 0 1
1 1 1 1
 BOOLEAN ALGEBRA
De Morgan’s Theorem

Consensus Theorem (or) Included factor Theorem

AB + ĀC+BC = AB+ĀC Proof of Consensus theorem

(A+B)( Ā+C)(B+C) = (A+B)( Ā+C) Statement 1: AB + ĀC+BC = AB+ĀC
AB+ĀC+BC = AB + ĀC + BC.1
= AB + ĀC + BC (A + Ā) → since A + Ā = 1
= AB + ĀC + ABC + ĀBC
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= AB (1 + C) + ĀC (1 + B)
= AB + ĀC → since 1 + B = 1 + C = 1
 BOOLEAN ALGEBRA
Consensus Theorem (or) Included factor Theorem

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 Demorganize

 Apply Demorgan’s theorem to the expression

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 COMPLEMENT
 For obtaining complement expression,
i. Change each OR sign by AND sign and vice-versa.
ii. Complement any 0 or 1 appearing in the expression.
iii. Complement the individual literals.

Complement of A(B+C) is A’+(B’.C’)  (A’+B’).(A’+C’)

Complement of A+B+C is A’.B’.C’  which is Demorgan’s theorem

Complement of AB’+A’B is (A’+B).(A+B’)  A’A+A’B’+A.B+BB’  AB+A’B’

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 DUALITY Operator /
Variable
Dual

AND OR
 Dual expression is equivalent to write a negative logic
OR AND
of the given Boolean relation. For this,
1 0
i. Change each OR sign by AND sign and vice-versa.
0 1
ii. Complement any 0 or 1 appearing in the expression.
A A
iii. Keep literals as it is.

Dual of A(B+C) = AB + AC is A+(BC) = (A+B).(A+C)

Dual of AB+C is (A+B).C Expression Dual
X+0=X X.1=X
Dual of A+= 1 is A. = 0
X+1=1 X.0=0
Dual of A+B= 0 is A.B = 1 X+X=X X.X=X
X + X’ = 1 X . X’ = 0
X +Y =Y + X X .Y =Y . X 26

X + (Y + Z) = (X + Y) + Z X . (Y . Z) = (X . Y) . Z
X.(Y + Z) = X.Y + X.Z X + (Y.Z) = (X+Y).(X+Z)
DUALITY

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 Simplification of Boolean Expression using
Theorems
 Simplify the Boolean function, f = p’qr + pq’r + pqr’ + pqr

Step 1 − In first and second terms r is common and in third and fourth terms pq is common.
So, take the common terms by using Distributive law.
⇒ f = (p′q+pq′)r+pq(r′+r)
Step 2 − The terms present in first parenthesis can be simplified to Ex-OR operation. The
terms present in second parenthesis can be simplified to ‘1’ using Boolean postulate
⇒ f = (p⊕q)r + pq(1)
Step 3 − The first term can’t be simplified further. But, the second term can be simplified to pq
using Boolean postulate.
⇒ f = (p⊕q)r + pq 28

Therefore, the simplified Boolean function is f = (p⊕q)r + pq

 Simplification of Boolean Expression using
Theorems
 Simplify the Boolean function, f = p’qr + pq’r + pqr’ + pqr
Step 1 − Use the Boolean postulate, x + x = x. That means, the Logical OR operation with any
Boolean variable ‘n’ times will be equal to the same variable. So, we can write the last term pqr
two more times.
⇒ f = p’qr + pq’r + pqr’ + pqr + pqr + pqr
Step 2 − Use Distributive law for 1st and 4th terms, 2nd and 5th terms, 3rd and 6th terms.
⇒ f = qr(p′+p) + pr(q′+q) + pq(r′+r)
Step 3 − Use Boolean postulate, x + x’ = 1 for simplifying the terms present in each parenthesis.
⇒ f = qr(1) + pr(1) + pq(1)
Step 4 − Use Boolean postulate, x.1 = x for simplifying the above three terms.
⇒ f = qr + pr + pq 29

⇒ f = pq + qr + pr
Therefore, the simplified Boolean function is f = pq+qr+pr
 Simplification of Boolean Expression using
Theorems
 Simplify the Boolean function, f = A + B [AC + (B + C’)D]

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Simplification of Boolean Expression using
Theorems
 Reduce the expression

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Simplification of Boolean Expression using
Theorems
 Show that

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Example – 1: Implement the following SOP function
F = XZ+Y’Z+X’YZ

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Example – 2: Implement the following POS function
F = (X+Z).(Y’+Z).(X’+Y+Z)

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Example – 3: Draw the simplest possible logic diagram that
Implements the output of the logic diagram shown below

 The logic diagram to implement simplified expression is

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NAND Gate as Universal Gate:

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NAND Gate as Universal Gate:

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NOR Gate as Universal Gate:

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NOR Gate as Universal Gate:

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 XOR Gate using NAND:
F = A XOR B = A’B+AB’ = A’B+AB’+AA’+BB’ = (A+B) (A’+B’)

Now we need to implement this circuit using NAND gates

F = (A+B)(AB)’ = A. (AB)’ + B. (AB)’

Take compliment
F’ = ( A. (AB)’ + B. (AB)’ )’ = (A. (AB)’)’. (B. (AB)’)’

Take compliment again

F = ( (A. (AB)’)’. (B. (AB)’)’ )’

Now we can implement this using NAND gates 40

 XNOR Gate using NOR:
F = A XNOR B = (A XOR B)’
F’ = A XOR B = A’B+AB’ = A’B+AB’+AA’+BB’ = (A+B) (A’+B’)
F’ = A’(A+B)+B’(A+B)

Take compliment
F = ( A’(A+B) + B’(A+B) )’ = (A’. (A+B))’. (B’. (A+B))’
= (A+(A+B)’).(B+(A+B)’)

Take compliment again

F’ = ( (A+(A+B)’). (B+(A+B)’) )’ = (A+(A+B)’)’+(B+(A+B)’)’

Take compliment again

F = ((A+(A+B)’)’+(B+(A+B)’)’)’ 41

Now we can implement this using NOR gates

XOR Gate using NOR:

XNOR Gate using NAND:

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Converting AND-OR-INVERT logic to NAND/NOR logic:

 Convert the following AOI logic circuit to (a) NAND logic (b) NOR logic

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MINTERM AND MAXTERM:

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MINTERM AND MAXTERM:
Example – 1:

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MINTERM AND MAXTERM:
Example – 2:

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Canonical SOP / SSOP:
Canonical SoP form means Canonical Sum of Products form or Standard Sum of Products form.
In this form, each product term contains all literals. So, these product terms are nothing but the
min terms. Hence, canonical SoP form is also called as sum of min terms form.

Consider the following truth table.

Inputs Output Here, the output f is ‘1’ for four combinations of inputs. The
p q r f corresponding min terms are p’qr, pq’r, pqr’, pqr. By doing logical
0 0 0 0 OR of these four min terms, we will get the Boolean function of
0 0 1 0 output f.
Therefore, the Boolean function of output is, f = p’qr + pq’r + pqr’ +
0 1 0 0
pqr. This is the canonical SoP form of output, f. We can also
0 1 1 1
represent this function in following two notations.
1 0 0 0
f=m3+m5+m6+m7
1 0 1 1
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1 1 0 1 f=∑m(3,5,6,7)
1 1 1 1
Canonical POS / SPOS:
Canonical PoS form means Canonical Product of Sums form or Standard Product of Sums form.
In this form, each sum term contains all literals. So, these sum terms are nothing but the Max
terms. Hence, canonical PoS form is also called as product of Max terms form.

Consider the following truth table.

Inputs Output
Consider the same truth table of previous example. Here, the
p q r f
output f is ‘0’ for four combinations of inputs. The corresponding Max
0 0 0 0
terms are p + q + r, p + q + r’, p + q’ + r, p’ + q + r. By doing logical AND
0 0 1 0 of these four Max terms, we will get the Boolean function of output f.
0 1 0 0 Therefore, the Boolean function of output is, f = (p+q+r).(p+q+r′).(p+q′
0 1 1 1 +r).(p′+q+r). This is the canonical PoS form of output, f. We can also
1 0 0 0
represent this function in following two notations.
1 0 1 1
f=M0.M1.M2.M4 50
1 1 0 1
1 1 1 1 f=∏M(0,1,2,4)
 Karnaugh Map (K-Map)
 It is a graphical method, which consists of 2 n cells for ‘n’ variables. The adjacent cells are
differed only in single bit.
 K-Map method is most suitable for minimizing Boolean functions of 2 variables to 5
variables.

2-variable K-Map:

The number of cells in 2 variable K-map is four, since the number of variables is two. The
following figure shows 2 variable K-Map.
• There is only one possibility of grouping 4 adjacent min terms.
• The possible combinations of grouping 2 adjacent min terms are {(m 0, m1), (m2, m3), (m0,
m2) and (m1, m3)}.

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 Karnaugh Map (K-Map)
3-variable K-Map:

The number of cells in 3 variable K-map is eight, since the number of variables is three. The
following figure shows 3 variable K-Map.
• There is only one possibility of grouping 8 adjacent min terms.
• The possible combinations of grouping 4 adjacent min terms are {(m0, m1, m3, m2), (m4, m5, m7, m6),
(m0, m1, m4, m5), (m1, m3, m5, m7), (m3, m2, m7, m6) and (m2, m0, m6, m4)}.
• The possible combinations of grouping 2 adjacent min terms are {(m 0, m1), (m1, m3), (m3, m2), (m2,
m0), (m4, m5), (m5, m7), (m7, m6), (m6, m4), (m0, m4), (m1, m5), (m3, m7) and (m2, m6)}.
• If X=0, then 3 variable K-map becomes 2 variable K-map.

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 Karnaugh Map (K-Map)
4-variable K-Map:

The number of cells in 4 variable K-map is sixteen, since the number of variables is four. The
following figure shows 4 variable K-Map.
• There is only one possibility of grouping 16 adjacent min terms.
• Let R1, R2, R3 and R4 represents the min terms of first row, second row, third row and fourth row
respectively. Similarly, C1, C2, C3 and C4 represents the min terms of first column, second column,
third column and fourth column respectively. The possible combinations of grouping 8 adjacent
min terms are {(R1, R2), (R2, R3), (R3, R4), (R4, R1), (C1, C2), (C2, C3), (C3, C4), (C4, C1)}.
• If W=0, then 4 variable K-map becomes 3 variable K-map.

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 Karnaugh Map (K-Map)
5-variable K-Map:

The number of cells in 5 variable K-map is thirty-two, since the number of variables is 5. The
following figure shows 5 variable K-Map.
• There is only one possibility of grouping 32 adjacent min terms.
• There are two possibilities of grouping 16 adjacent min terms. i.e., grouping of min terms from
m0 to m15 and m16 to m31.
• If V=0, then 5 variable K-map becomes 4 variable K-map.

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In the above all K-maps, we used exclusively the min terms notation. Similarly, we can also use
exclusively the Max terms notation.
K-Map:
Example – 1: Reduce the expression A’B’+A’B+AB using map method.

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K-Map:
Example – 2: Reduce the expression (A + B)(A + B’)(A’ + B’) using mapping.

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K-Map:
Example – 3: Reduce the expression ∑ m (0,2,3,4,5,6) using mapping and implement it in AOI logic as
well as in NAND logic.

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K-Map:
Example – 4: Reduce the expression ∏ M (0,1,2,3,4,7) using mapping and implement it in AOI logic as
well as in NOR logic.

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K-Map:
Example – 5: Obtain the real minimal expression for ∑ m (1,2,4,6,7) and implement it using universal gates.

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K-Map:
Example – 6: Reduce using mapping the expression ∑ m (0-3,5,7-10,12,13) and implement it in
universal logic.

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K-Map:
Example – 7: Reduce the following expression using mapping ∑ m (0,2,3,10-13,16-21,26,27).

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K-Map: Example – 7: Reduce the following expression using mapping ∑ m (0,2,3,10-13,16-21,26,27).

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K-Map:
Example – 8: Reduce the following expression using mapping ∑ m (1,3,6,7).

From red group we get product term—

A’C

From green group we get product term—

AB

Summing these product terms we get-

Final expression (A’C+AB)

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K-Map:
Example – 9: Reduce the following expression using mapping ∏ M (0,3,6,7).

From red group we get sum term—

A’ + B’

From green group we get sum term—

B’ + C’

From brown group we get sum term—

A+B+C

Product of these sum terms gives—

Final expression (A’ + B’)(B’ + C’)(A + B + C)

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K-Map:
Example – 10: Reduce the following expression using mapping ∏ M (3,5,7,8,10,11,12,13).

From red group we get sum term—

A + C’ + D’

From green group we get sum term—

B’ + C + D’

From blue group we get sum term—

A’ + C + D

From brown group we get sum term—

A’ + B + C’

Product of these sum terms gives— 65

Final expression (A + C’ + D’)(B’ + C + D’)(A’ + C +
D)(A’ + B + C’)
K-Map [Few more terms]:

 Prime implicant
 Essential prime implicant
 Redundant prime implicant
 Selected prime implicant
 Isolated one

 False prime implicant

 Essential false prime implicant
 Redundant false prime implicant
 Selected false prime implicant 66

 Isolated zero
Don’t care combinations:
 The “Don’t Care” conditions allow to replace the empty cell of a K-Map to form a grouping of
the variables. While forming groups of cells, a “Don’t Care” cell may be considered as either 1
or 0 or simply ignored. Therefore, “Don’t Care” condition helps to form a larger group of cells.

 A Don’t Care cell can be represented by a cross(X) in K-Maps representing a invalid

combination. For example, in Excess-3 code system, the states 0000, 0001, 0010, 1101, 1110
and 1111 are invalid or unspecified. These are called don’t cares.

 Also, in design of 4-bit BCD-to-XS-3 code converter, the input combinations 1010, 1011, 1100,
1101, 1110, and 1111 are don’t cares.

 A standard SOP function having don’t cares can be converted into a POS expression by
keeping don’t cares as they are, and writing the missing min-terms of the SOP form as the
max-term of POS form. Similarly, a POS function having don’t cares can be converted to SOP
form keeping the don’t cares as they are and write the missing max-terms of the POS 67
expression as the min-terms of SOP expression.
K-Map with don’t cares:
Example – 1: Minimize the following function in SOP minimal form using K-Maps F = ∑
m(1,5,6,12,13,14) + d(4)

The SOP K-map for the given expression is:

Therefore, SOP minimal is, F = BC' + BD' + A'C'D 68

K-Map with don’t cares:
Example – 2: Minimize the following function in POS minimal form using K-Maps F(A,B,C,D) = ∑
m(0-5) + d(10-15)

Writing the given expression in POS form F(A,B,C,D) = π M(6-9) + d(10-15)

The POS K-map for the given expression is

Therefore, POS minimal is, F = A’ (B’ + C’) 69

K-Map with don’t cares:
Example – 3: Minimize the following function in SOP minimal form using K-Maps F(A,B,C,D) = ∑
m(1,2,6,7,8,13,14,15) + d(3,5,12)

The SOP K-map for the given expression is

Therefore, SOP minimal is, F = AC’D’ + A’D + A’C + AB 70

 TABULAR METHOD (QUINE-McCLUSKEY
METHOD)
Procedure for Finding the Minimal Expression:
• Arrange all minterms in groups, such that all terms in the same group have same number of 1’s in their
binary representation. Start with the least number of 1’s and continue with grouping of increasing
number of 1’s, the number of 1’s in each term is called the index of that term i.e., all the minterms of
same index are placed in a same group. The lowest value of index is zero. Separate each group by a thick
Line. This constitutes the I stage.
• Compare every term of the lowest index (say i) group with each term in the successive group of index
(say, i + 1). If two minterms differ in only one variable, that variable should be removed and a dash (–) is
placed at the position, thus a newterm with one less literal is formed. If such a situation occurs, a check
mark (✔ ) is placed next to both minterms. After all pairs of terms with indices i and (i + 1) have been
considered, a thick line is drawn under the last terms. When the above process has been repeated for all
the groups of I stage, one stage of elimination have been completed. This constitutes the II stage.

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 TABULAR METHOD (QUINE-McCLUSKEY
METHOD)
Procedure for Finding the Minimal Expression:
• The III stage of elimination should be repeated of the newly formed groups of second stage. In this
stage, two terms can be compared only when they have dashes in same positions.
The process continues to next higher stages until no further comparisons are possible. (i.e., no further
elimination of literals).
• All terms which remain unchecked (No ✔ sign) during the process are considered to be prime implicants
(PIs). Thus, a set of all PIs of the function is obtained.
• From the set of all prime implicates, a set of essential prime implicants (EPIs) must be determined by
preparing prime implicant chart as follow.
(a) The PIs should be represented in rows and each minterm of the function in a column.
(b) Crosses should be placed in each row corresponding to minterms that makes the PIs.
(c) A complete PIs chart should be inspected for columns containing only a single cross. PIs that cover
minterms with a single cross in their column are called EPIs.
• The minterms which are not covered by the EPIs are taken into consideration and a minimum cover is 72
obtained form the remaining PIs.
 TABULAR METHOD
Simplify the given function using tabular method.F (A, B, C, D) = ∑ m (0,1,6,7, 8,9,13,14,15)

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 TABULAR METHOD
Simplify the given function using tabular method.F (A, B, C, D) = ∑ m (0,1,6,7, 8,9,13,14,15)
Prime Implicant Chart
PIs/Minterms ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔

0 1 6 7 8 9 13 14 15

*P 6,7,14,15 (1,8) X X X X

*Q 0,1,8,9 (1,8) X X X X

R 13,15(2) X X

S 9,13(4) X X

Answer is P+Q+R = BC+B’C’+ABD

OR P+Q+S = BC+B’C’+AC’D
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 TABULAR METHOD
Simplify the given function using tabular method.F (A, B, C, D) = ∑ m (0, 2, 3, 6, 7, 8, 10, 12, 13)

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 TABULAR METHOD
Simplify the given function using tabular method.F (A, B, C, D) = ∑ m (0, 2, 3, 6, 7, 8, 10, 12, 13)

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 TABULAR METHOD
Simplify the given function using tabular method.F (A, B, C, D) = ∑ m (0, 2, 3, 6, 7, 8, 10, 12, 13)
Prime Implicant Chart
PIs/Minterms ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔ ✔

0 2 3 6 7 8 10 12 13

P 8,12(4) X X

*Q 12,13(1) X X

*R 0,2,8,10 (2,8) X X X X

*S 2,3,6,7(1,4) X X X X

Answer is Q+R +S = ABC’+B’D’+A’C

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 TABULAR METHOD
Simplify the given function using tabular method.F (A, B, C, D) = ∑ m (6, 7, 8, 9)+d(10,11,12,13,14,15)

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 TABULAR METHOD
Simplify the given function using tabular method.F (A, B, C, D) = ∑ m (6, 7, 8, 9)+d(10,11,12,13,14,15)

Prime Implicant Chart

Answer is P+Q=A+BC

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Refernces
 “Switching Theory and Logic Design” by A. Anand Kumar
 https://www.tutorialspoint.com/computer_logical_organization/logic_gates.html
 https://www.geeksforgeeks.org/boolean-algebraic-theorems/
 https://www.electronicshub.org/boolean-algebra-laws-and-theorems/
 https://www.electrical4u.com/boolean-algebra-theorems-and-laws-of-bool
ean-algebra/
 https://www.geeksforgeeks.org/dont-care-x-conditions-in-k-maps/
 “Fundamentals of Digital Circuits” by A.Anand Kumar
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