SYNTHESIS LAB

Synthesis Flow:

Logical Synthesis:

Synthesis is a process of converting RTL code into Optimized Gate Level Netlist for
the targeted Technology to meet Timing, Power and Area.

 In this stage, The Technology Independent RTL code is converted into Technology Dependent
Gate Level Netlist. Using Synthesis Tool.

 In logical synthesis we consider ZERO WIRE LOAD model. Because, we are not routing
any connections physically between cells.

 In Logical Synthesis have Ideal Clock. [Ideal clock = No skew] Because, the real clock is
not build physically.

 In Logical Synthesis we check only Setup Analysis with Ideal Clock.

Why don’t check Hold?

Hold is Independent on clock period. It is dependent only on data path.

We are considering ZERO WIRE LOAD model. There is no net delays, so we did not get accurate
values for Hold Analysis in Logical Synthesis.
EDA Tools for Logical Synthesis:

 Synopsys - Design Compiler

 Cadence – Innovus

Inputs of Logical Synthesis:

 Library File.

.lib is Timing Library. CCS and NLDM techniques are used to generate Library Files.

In CCS [composite current source] Current source is used for driver modeling. Propagation
delay is calculated by Input Transition, Output Load and Time. In CCS additional index is time,
it also in calculation of cell delay. CCS is more accurate at lower technology nodes. CCS file is
larger than NLDM file. Run time of CCS is more.

NLDM [non linear delay model] uses the Voltage for driver modeling. Propagation delay is
calculated by Input Transition and Output Load. NLDM is very fast in Delay calculations but
it loses the accuracy below 130nm.

Library File contains Cell delays, transitions, setup and hold time requirements.

The design needs to be tested for certain PVT corners. So there is a Lib file for every
PVT corner.

In Lib File contains unit attributes also like,

Time unit, voltage unit, current unit, leakage power unit, capacitive load unit and slew
rate: Lower and upper limit values are defined in terms of percentage for both rise and fall
time.

 RTL (Verilog File).

Register Transfer Level.

RTL file have Functionality of circuit in the form of verilog code. The RTL code is
developed using Micro-architecture of Design which is derived from chip design
requirements.

 SDC File.

Synopsys Design Constraints.

SDC have Timing Constraints, Clock frequency, Input and Output delay requirements,
maximum power consumption, path groups.
Outputs of Logical Synthesis:

 Optimized Gate Level Netlist.

Netlista is a collection of Gates and their Logical connectivity.

Netlist contains Standard cells and macros: its name, instances, drive strength, ports and
inter connection details.

 Reports.

Timing, Power and Area Reports.

Enter into Dc Shell:

Command:

dc_shell

Log file:

In dc_shell, Designers use Log files to keep track the progress of their synthesis process.
These log files contain detailed information about the synthesis process that we have done on dc_shell.

Log files can be used for Future reference and Documentation.

Command:

dc_shell -output rptoptop.log

Command:

read_verilog < rtl file name >

(or)
read_verilog < rtl file full path >

read_verilog command will perform equally to both analyze and elaborate

commands. read_verilog commands checks line by line. It read a line and converts that
line.

Than it read next line. In case, any error found in the line it stops reading at that line
only and gives error.

So we use mostly analyze -format verilog and elaborate commands.

WITH SEARCH PATH:

 set search_path < {libraries and macros directory path} >

 set link_library < {* libraries and macros file name} >

 set target_library < {libraries file name} >

 analyze -format verilog < rtl file name >

 elaborate < top module name >

 compile

WITHOUT SEARCH PATH:

 set link_library < {* libraries and macros full path} >

 set target_library < {libraries full path} >

 analyze -format verilog < rtl file full path >

 elaborate < top module name >

 compile

Tool can also read rtl code with directory path without providing rtl file name.

Command:

analyze {rtl file directory path} -autoread -recursive -top < top module
name >
 PROJECT – 5

STEP 1: Search Path:

Whenever the tool needs file, It searches required file from the directory paths. Which
are mentioned in search path.

Search path is not mandatory. We can proceed without search path also, but we need to give
full paths for the file every time.

Search path saves the time and memory.

Command:

set search_path {Libraries and Macros directory paths}

STEP 2: Link library:

link library is a pre-defined variable. Link Library is mainly for resolving references. We
provide star * in Link Library it extracts the Macros and some tool default files.

Tool default files:

 GTECH Library

 Symbol Library

 Design ware Library

Command:

set link_library {* Library and Macro File names}

Unresolved References:

In RTL file have function of a cell or module, but that is not found in the Library Files in
the link_library variable. It is called Unresolved References.

To Fix this Error change the library file which contains all reffered cells or modules.
STEP 3: Target library:

Target library is a pre-defined variable. It have standard cell Information.

From the Target library Design Compiler (tool) will select the cells for Optimization and
Remapping.

In Target Library we use worst PVT corner DB File to met setup slack. We use max path for setup
because, if the worst corner met every PVT corner’s setup slack will met with the same
optimization technique.

Command:

set target_library {Library file names}

STEP 4: Sanity Check.

Command:

get_libs

It shows the Libs are loaded or not.

STEP 5: Analyze:

Analyze command translates the source code (RTL) into Machine code (binary format)
and reads the File Line by Line.

If any errors found it will displays after completion of file reading, than we need to report
RTL team.

Command:

analyze {RTL File directory path} –autoread –recursive –top < top module
name >

STEP 6: Elaborate:

RTL code will convert into GTECH and Design Ware components.

GTECH Library contains basic Logic Gates and Flipflops.

Design Ware Library contains complex cells like FIFO, Counters.

In Elaborate stage, links every cell Instantiation called in the RTL File with GTECH and DW
cells. Which are independent on Technology.

If any cells are called from RTL File are not available in GTECH or DW components that referred
cells are linked from the Library Files are loaded in link_library.

Command:

elaborate < top module name >

STEP 7: Sanity Checks.

Command:

Get_design

Checks all the modules are called from the RTL File are loaded or
not.

Command:

Check_design

It checks the Internal representation of current design.

STEP 8: Command:

start_gui

After elaboration process to view the schematic circuit of Netlist.

Command:

stop_gui

To close the schematic view of Netlist.

STEP 9: Compile:

In compile stage Mapping is done with the cells which are in target_library
Files.

Here performs:

 Boolean Optimization.
 Maps all the cells to Technology Libraries.
 Logic and Design Optimization.

Logic Optimization:

Constant Folding

Reduce word size of cells

Removes unused cells and wires

Remove DFF with constant value

Consolidate mux and reduce

inputs (many to single).

Design Optimization:

Reduces TNS and WNS

Power Optimization

Area Optimization

Meets the timing DRVs

Incremental Clock
Gating.

Command:

Compile
STEP10: Command:

start_gui

After compilation process schematic view of Optimized Gate Level

Netlist.
Command:

stop_gui

To close the window of

schematic view of the
Optimized Gate Level
Netlist.

STEP 11: Create clock.

Creating a clock
with name,
period and
waveform. From
the source
(clock port).

Why should we create

clock?
Command:
Then only Tool
Report_clock
will understand
the clock period
or clock
frequency.

Command:

create_clock -
name gopi -
period 2.25
[get_ports clk]

STEP 12: Clock Uncertainty Setup.

We are taking 20% from the clock period. It is Setup Uncertainity.

Command:

set_clock_uncertainty -setup 0.45 [get_clocks gopi ]

STEP 13: Clock uncertainty Hold.

We are taking 15% from the clock period. It is Hold Uncertainity.

Command:

set_clock_uncertainty -hold 0.3375 [get_clocks gopi]

STEP 14: Input Delay

Input delay is the Delay of Signal from other Block Output to my Block Input.

We are taking input delay as 60% from the clock

period. Why we are removing clock from Input Delay?

Clock is only reference to the input to transfer
data, It is not a Data Input to Register.

So we will remove from the Input delay.

Command:

set_input_delay 1.35 -clock gopi [get_ports

[remove_from_collection [all_inputs] clk]]

STEP 15: Output Delay.

Output delay is the Delay of signal from my Block Output to the next Block
Input.

We are taking Output Delay as 60% from the clock period.

Command:

set_output_delay 1.35 -clock gopi [get_ports [all_outputs]]

STEP 16: Driving cell.

Driving cell is the source to our Block. If we don’t set Driving cell for Input Ports, there is
No limit in driving by the Input Ports.

Which cause the delay in cells due to High transition time and load. It leads to Violation in
Setup Slack.
Command:

set_driving_cell -lib_cell BUFFD8BWP40P140HVT [get_ports [remove_from_collection

[all_outputs] SCK]]

STEP 17: Load.

It is the Output from my Block to another Block

Input.

Command:

set_load 0.00146193 [get_ports [all_outputs]]

STEP 18: Group Paths:

 Input to Register

 Register to Register

 Register to Output

 Input to Output

Command:

group_path -name i2r -from [all_inputs] -to [all_registers -data_pins]

group_path -name r2r -from [all_registers -clock_pins] -to [all_registers -

data_pins]

group_path -name r2o -from [all_registers -clock_pins] -to [all_outputs]

group_path -name i2o -from [all_inputs] -to [all_outputs]

STEP 19: Sanity Checks.

Command:

report_timing

Here I got a Violation in the ( in2out ) path. The SLACK is Violated.

STEP 20: Create Virtual Clock:

Here I have Created a Virtual Clock to met the Violation in (i2o) path group. Virtual clock is
not getting from any Source.

(In to Out) paths don’t have any sequential logic.

To met the Slacks (violations) we should have Clock. So we are creating Virtual Clock.

Command:

create_clock -name gopivirtual -period 2.25

STEP 21: Input delay for Virtual Clock.

Command:

set_input_delay 0.7875 -clock gopivir [get_ports [filter_collection [all_fanin -

to [all_outputs]] “port_direction == in”]]
STEP 22: Output delay for Virtual Clock.

Command:

set_output_delay 0.7875 -clock gopivir [get_ports [filter_collection [all_fanout -

from [all_inputs]] “port_direction == out”]]

STEP 23: Clock Uncertainty Setup.

We are taking 20% from the Virtual clock period. It is Setup Uncertainity.

Command:

set_clock_uncertainty -setup 0.45 [get_clocks gopivir ]

STEP 24: Clock Uncertainty Hold.

We are taking 15% from the Virtual clock period. It is Hold Uncertainity.

Command:

set_clock_uncertainty -hold 0.3375 [get_clocks gopivir ]

Command:

report_timing

Here the [i2o] group path is met.

Here the [ r2o] path group is Not Violated [met].

Here the [i2r] path group slack is Violated.

Here the [r2r] path group slack is Violated.

To MET the Negative Slack [violation]. I used Optimization Techniques.

Optimizations Techniques in Logical Synthesis:

 weightage for group paths

 compile

 compile_ultra

Here the [i2r] group path slack is MET.

Here the [r2r] group path is MET.

Command:

report_area
Command:

report_power
Command:

report_qor
Sanity Checks.

Command:

check_timing

It Displays errors and

warnings.

 Unclocked registers

 unconstrained end
points

 combination loops
/timing loops

 multiple clocks
reaching a clock pin

 unconstrained I/O’s

Command:

Check_design

It Displays errors and warnings.

 Multi driven inputs

/unconnected inputs
/driverless

 Empty modules

 Unmaped cells

 Multi driven nets

Command:

write_file -format verilog -hierarchy -output rptoptop_netlist.v

Optimized Gate Level Netlist verliog File is saved in rptoptop_netlist.v

file

Command:

write_sdc rptoptop.sdc

All sdc commands are saved in rptoptop.sdc file

Command:

write_file -format ddc -hierarchy -output rptoptop.ddc

ddc file saves the Design Compiler database at different stages of

synthesis.
Command:

read_ddc rptoptop.ddc

By providing search_path, link_library, target_library and read_ddc

rptoptop.ddc Here we can get reports and continue the remaining process.