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S4 - DC Biasing of BJTs
S4 - DC Biasing of BJTs
Topic 4 (Chapter 4)
(Some materials are from Malvino’s book)
Biasing
RB 12 V VCC
VBB 12 V
Load line
• A visual summary of all the possible
transistor operating points
• Connects saturation current (ICsat) to cutoff
voltage (VCEcutoff )
Load line
VCC - VCE A graph of this equation
IC = produces a load line.
RC
14 100 mA
12 80 mA
10 60 mA
IC in mA 8
6 40 mA
4 20 mA
2
0 mA
0 2 4 6 8 10 12 14 16 18
VCE in Volts
Saturation
When the transistor is operating in
saturation, current through the transistor
is at its maximum possible value.
V
ICsat CC
R
C
VCE 0 V
Understanding Saturation
12 V
IC =
1 kW
1 kW RC
Mental
short
RB 12 V VCC
VBB 12 V
Understanding Saturation
12 V This is the
IC = = 12 mA
1 kW Saturation (maximum) current.
14 100 mA
12 80 mA
10 60 mA
IC in mA 8
6 40 mA
4 20 mA
2
0 mA
0 2 4 6 8 10 12 14 16 18
VCE in Volts
Understanding Cutoff
1 kW RC
Mental
open
RB 12 V VCC
VBB 12 V
Understanding Cutoff
VCE(cutoff) = VCC
14 100 mA
12 80 mA
10 60 mA
IC in mA 8
6 40 mA
4 20 mA
2
0 mA
0 2 4 6 8 10 12 14 16 18
VCE in Volts
4.4 Emitter bias:
Contains an emitter resistor 11 kW
kW RC
VBB - VBE IC @ I E
IE = = 1.95 mA
RE
15 V VCC
VBB 5V 2.2 kW RE
R2 RE
Voltage divider bias circuit +VCC
{
RC
R1
R1 and R2 form
a voltage divider
R2 RE
Divider analysis:
Rth = R1 || R2
Eth = R2
VCC
R1 + R2
4.6 Collector-feedback bias