Quote of the Day

You become What you think all day

long
-Earl Nightingale
What you will Learn Today
 Introduction to VHDL
 Structure of VHDL
 How to create a project in Xilinx ISE using
VHDL Code
 How to run Behavioral simulation
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My Primary Expertise
Microcontroller Architecture: 8051,PIC,AVR,ARM,MSP430,PSOC3
DSP Architecture: Blackfin,C2000,C6000,21065L Sharc
FPGA: Spartan,Virtex,Cyclone
Image Processing Algorithms: Image/Scene Recognition, Machine Learning, Computer Vision, Deep Learning,
Pattern Recognition, Object Classification ,Image Retrieval, Image enhancement and denoising.
Neural Networks : SVM,RBF,BPN
Cryptography :RSA,DES,3DES,Ellipti curve,Blowfish,Diffe Hellman
Compilers: Keil,Visual DSP++,CCS, Xilinx Platform studio,ISE, Matlab, Open CV

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 Announcement
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● Only Xilinx FPGA and tools will be covered.
History of VHDL
● 1981- United States Department of defense initiated the requirements
for the Very High speed integrated Circuit (VHSIC) Program
● 1983- IBM and Texas Instruments begin development
● 1984 –Xilinx produces the First FPGA

IEEE Formalized the language into Standard

Updated in 1993 and again in 2002
VHDL
● VHDL is the first foremost language for Hardware Modeling
● It is case insensitive ,whereas Verilog is case sensitive
● It was derived from the language called ADA ,Whereas Verilog is c like
structure
● VHDL follows the Top Down flow and provides the better level of
Abstraction
VHDL as a Language
● Case Insensitive
● Strong typing

○ Every signal, component and function should be defined before use

○ Signal or variable must match exact size of the Variable on the left hand side
● VHDL are concurrent in nature
● VHDL Supports and encourage Hierarchy and partitioning
● Analysis order

○ VHDL Is a single pass compiler, everything must be defined before it is used

○ Xilinx tool automatically order files for analysis

Xilinx Design Process on ISE
Typical VHDL Module Example
Structure of VHDL
Entity Declaration
Entity Declaration
Architecture Declaration
What is Concurrency and How parallelism done in
FPGA
Lessons
● Schematic design Modelling on Xilinx ISE
● Simple VHDL Code on Xilinx ISE
Schematic Design using Xilinx ISE
Vhdl code for Xilinx ISE
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Half_adder is
PORT (A: IN STD_LOGIC;
B: IN STD_LOGIC;
SUM : OUT STD_LOGIC;
COUT : OUT STD_LOGIC);
end Half_adder;

architecture Behavioral of Half_adder is

begin
SUM <= A XOR B;
COUT <= A AND B;
end Behavioral;
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