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CO3 - PPT-Modified
CO3 - PPT-Modified
CO3 - PPT-Modified
1
19EC1202
COMPUTER ORGANIZATION AND ARCHITECTURE
CO3
2. Processor Communication
3. Device Communication
4. Data Buffering
5. Error Detection
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Input/output Modules
The control of the transfer of data from an external device to the processor might involve the
following sequence of steps –
1. The processor interacts with the I/O module to check the status of the attached device.
2. The I/O module returns the device status.
3. If the device is operational and ready to transmit, the processor requests the transfer of
data, by means of a command to the I/O module.
4. The I/O module obtains a unit of data from external device.
5. The data are transferred from the I/O module to the processor.
1. Command decoding :The I/O module accepts command from the processor,
2. Data :Data are exchanged between the processor and the I/O module over
5. Error Detection
Another task of I/O module is error detection and for subsequently reporting
error to the processor.
One class or error includes mechanical and electrical malfunctions reported by
the device (e.g. paper jam).
Another class consists of unintentional changes to the bit pattern as it is
transmitted from devices to the I/O module.
Memory-mapped I/O
Isolated or I/O mapped I/O
• Since I/O devices are included in the same memory address space, so the
status and address registers of I/O modules are treated as memory location
by the processor.
• Therefore, the same machine instructions are used to access both memory
and I/O devices.
• The address refers to a memory location or an I/O device is specified with the
device.
2 Both have same address space Memory and I/O have separate address space
3 Due to addition of I/O addressable memory become All address can be used by the memory
less for memory
4 Same instructions can control both I/O and Memory Separate instruction control read and write operation
in I/O and Memory
5 Normal memory address are for both In this I/O address are called ports.
1. Synchronous : All devices derive the timing information from common clock line.
2. Asynchronous: No common clock
Require control signals
1. Strobe Pulse
2. Handshaking
Block Diagram
Timing Diagram
Sequence of events
Block Diagram
Timing Diagram
Sequence of events
Programmed I/O
Read : Causes the I/O module to obtain an item of data from the peripheral and
place it in the internal buffer.
Write : Causes the I/O module to take an item of data ( byte or word ) from the
data bus and subsequently transmit the data item to the peripheral.
follows:-
2. Processor is disconnected from system bus during DMA transfer. N number of machine
cycles are adopted into the machine cycles of the processor where N is the number of
bytes to be transferred.
3. DMA sends HOLD signal to processor to request for system bus and waits for HLDA signal.
4. After receiving HLDA signal, DMA gains control of system bus and transfers one byte. After
transferring one byte, it increments memory address, decrements counter and transfers
next byte.
5. In this way, it transfer all data bytes between memory and I/O devices. After transferring
all data bytes, the DMA controller disables HOLD signal & enters into slave mode.
2. DMA sends HOLD signal to processor and waits for HLDA signal on receiving
HLDA signal, it gains control of system bus and executes only one DMA cycle.
3. After transfer one byte, it disables HOLD signal and enters into slave mode.
4. Processor gains control of system bus and executes next machine cycle. If
count is not zero and data is available then the DMA controller sends HOLD
signal to the processor and transfer next byte of data block.
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Transparent or Hidden DMA transfer
1. Processor executes some states during which is floats the address and data
buses. During this process, processor is isolated from the system bus.
2. DMA transfers data between memory and I/O devices during these states.
This operation is transparent to the processor.
3. This is slowest DMA transfer. In this mode, the instruction execution speed of
processor is not reduced. But, the transparent DMA requires logic to detect
the states when the processor is floating the buses.