Digital Principles

SIMPLIFYING LOGIC CIRCUITS

 BOOLEAN THEOREMS
•Logic circuits can be constructed from Boolean expressions.

•Simpler expressions mean simpler circuits.

A
B X=ABC
C
C

•Boolean Theorems are useful in simplifying expressions

and logic circuits.
 THEOREMS
FIRST 8 THEOREMS = SINGLE
VARIABLE
AND OR
 THEOREMS
(1) AND (2) AND ENABLE
INHIBIT

5V 5V
+V +V
14

CP1Q1 A A 14
CP2Q2 1 CP1Q1 1
3 CP2Q2 3
2 2
B B
7 VCC 7

THEOREM 1: X*0=0 THEOREM 2: X*1=X

 THEOREMS
Expression Simplification Examples

A B 0  0 A( B  B )
F G 0 H  0 A(1)
ABC  0  0 A
C ( D  1)
C (1)
C
 THEOREMS

5V
5v +V
+V

14 14
1 CP1Q1 1
CP1Q1 3 CP2Q2 3
CP2Q2
5V
+V 14
2 2 7
7
7
 THEOREMS
Expression Simplification Examples

ABCB  ABC AB( AB)  0

DD  D
C (C  E E )
C C  CE E
000
 THEOREMS
(5) OR ENABLE (6) OR INHIBIT

5V
5V +V
+V
14 14
CP1Q1
CP1Q1 1 CP2Q2
CP2Q2 3 1
'32 3
2 5V
2 '32
7
7
 THEOREMS
Expression Simplification Examples

MN  0  MN C  CD
C (1  D)
A(0  1) C (1)
A(1) C
A
 THEOREMS

5V
+V 5V
+V
14
1
CP1Q1 3 CP1Q1
CP2Q2 1 14
CP2Q2 2 '32 3
2 '32
7 5V
+V 14 7
1 2
 THEOREMS
Expression Simplification Examples

A B  CB  A B A BD  A B D
A B  CB AB( D  D)
A B (1)
AB
 THEOREMS
THEOREMS 9 AND 10: COMMUTATIVE
•If it’s the same function, it doesn’t matter
which input
9. X •To
 Y use,
 Y must
 X have same function
10. X  Y  Y  X
 THEOREMS
THEOREMS 11 AND 12: ASSOCIATIVE
•If it’s a single operation, it doesn’t matter which terms are
combined first.

X Y  Z
 THEOREMS
THEOREMS 11 AND 12: ASSOCIATIVE
•If it’s a single operation, it doesn’t matter which terms are
combined first.
 THEOREMS
THEOREM 13: DISTRIBUTIVE
•This theorem is used to covert between sum-of-product and
product-of-sum
•One of the most13important
.( a ) X (Y theorems
 Z )  XY  XZ

POS

SOP
 THEOREMS
Expression Simplification Examples

13.(a ) X (Y  Z )  XY  XZ

A BD  A B D
AB( D  D)
A B (1)
AB
 THEOREM 13: DISTRIBUTIVE
•This theorem is used to covert between sum-of-product and
product-of-sum
FOIL= FIRST, OUTER, INNER,
LAST

13.(b) (W  X )(Y  Z )  WY  WZ  XY  XZ

W
X
POS Y
Z
W
Y
W
SOP Z
X
Y
X
Z
 THEOREMS
Expression Simplification Examples

13.(b) (W  X )(Y  Z )  WY  WZ  XY  XZ
( A  B )( A  B )
AA  AB  AB  BB
0  AB  AB  B
B ( A  A  1)
B (1)
B
THEOREMS
THEOREM 14

X  XY  X
X 1 Y 
X 1
X
 THEOREMS
THEOREM 15

X Y OUT
0 0 0
0 1 1
1 0 1
1 1 1
 THEOREMS
16 & 17: DEMORGAN’S THEOREMS
•Simplifying expressions in which a product or sum of
variables is inverted.
•“Break the line and change the sign.”
 THEOREMS
Expression Simplification Examples

AB  C
AB  C
( A  B)  C
( A  B)  C
AC  BC
 THEOREMS
THEOREM 18
•A quantity inverted twice equals the original
quantity
XX
 STEPS FOR
REDUCING EXPRESSIONS
1. Go to SOP (sum of products)
form.
( A  B )(C  D)  AC  AD  BC  BD

2. Check for exact duplicates and drop.

A B  CB  A B
A B  CB
 STEPS FOR
REDUCING EXPRESSIONS
3. See if one of the terms is entirely contained in another.

AC  ACE
If it is, factor it out.

AC (1  E )
4. See if two of the terms are different by only by a not function.

ABC  ABC
If it is, factor out all the similar terms.

AB (C  C )
 TEST
Simplify the expression:

A BD  A B D
A B ( D  D) (13a)
A B (1) (8)

AB (2)
 TEST
Simplify the expression:

( A  B )( A  B )
AA  AB  AB  BB (13b)
0  B ( A  A  1) (4), (13a)
B (1) (6)

B (2)
 TEST
Simplify the expression:

ACD  ABCD
CD ( A  AB ) (13a)

CD ( A  B ) (15)
ACD  BCD (13a)
 BOOLEAN THEOREMS

1. X 0  0 8. X  X  1 14. X  XY  X
2 . X 1  X 9. X  Y  Y  X 15. X  X Y  X  Y
3. X  X  X 10. X  Y  Y  X 16. X  Y  X Y
4. X  X  0 11. X  Y  Z    X  Y   Z  X  Y  Z 17. XY  X  Y
5. X 0  X 12. X YZ    XY Z  XYZ
18. A  A
6 . X 1  1 13a. X Y  Z   XY  XZ
7. X  X  X 13b. W  X Y  Z   WY  XY  WZ  XZ
Digital Electronics

Flip-Flops
 PREVIEW
• Combinational vs. Sequential Logic Circuits
• R-S Flip-flop
• Clocked R-S Flip-flop
• D Flip-flop
• J-K Flip-flop
• Latches (simple memory devices)
• Triggering of flip-flops
• Schmitt triggered device
 LOGIC CIRCUITS
Logic circuits are classified into two groups:
Combinational logic circuits Logic gates make decisions

Basic building
blocks include:

Sequential logic circuits Flip Flops have memory

Basic building blocks

include FLIP-FLOPS:
 FLIP-FLOPS

•Memory device capable of storing one bit

•Memory means circuit remains in one
S Q state after condition that caused the state
is removed.
•Two outputs designated Q and Q-Not that
R Q are always opposite or complimentary.
•When referring to the state of a flip flop,
referring to the state of the Q output.
 FLIP-FLOPS

Symbol
SET •To SET a flip flop means to
S Q make Q =1
RESET
R Q
Truth Table
•To RESET a flip flop means to
make Q = 0
 FLIP-FLOPS
5V
+V

1k 1k
OUTPUT 1k 1k OUTPUT
Q NOT Q
1k 1k
NPN NPN
1k 1k

set reset
input input

•The flip flop is a bi-stable multivibrator; it has two stable states.

•The RS flip flop can be implemented with transistors.
 TEST
1. Logic gates make decisions, flip flops have ____________________?

2. One flip flop can store how many bits?

3. What are the two outputs of a flip flop?

4. When referring to the state of a flip flop, we’re referring to the state
of which output?

5. What does it mean to SET a flip flop?

6. What does it mean to RESET a flip flop?

 R-S FLIP-FLOP

Symbols: Set Normal

S Q
FF
R Q
Reset Comple-
mentary

Truth Table:
Mode of Operation Inputs Outputs
S R Q Q’
Prohibited 0 0 1 1
Set 0 1 1 0
Reset 1 0 0 1
Hold 1 1 Q Q’

NOTE: Active-LOW inputs

R-S FLIP-FLOP
Active-Low
NAND LATCH
Q
SET

7400
Q NOT

RESET
7400

DEMORGANIZED NAND LATCH

NAND LATCH Q
SET

Q NOT

RESET

SET RES Q NOT-Q MODE

0 0 1 1 PROHIBITED
0 1 1 0 SET
1 0 0 1 RESET
1 1 NO CHG HOLD
ACTIVE-LOW R-S FLIP-FLOP
TIMING DIAGRAMS
 TEST
What is the mode of operation of the R-S flip-flop (set, reset or hold)?
What is the output at Q from the R-S flip-flop (active LOW inputs)?

L
?High
H
Mode of operation = ?Set

H
?High
H
Mode of operation = Hold
?

H
? Low
L
Mode of operation = ?
Reset
R-S FLIP-FLOP
Active-High
ACTIVE-HIGH R-S FLIP-FLOP
TIMING DIAGRAMS
 CLOCKED R-S FLIP-FLOP

Set FF Set FF
S Q S Q
Clock
CLK
Reset Q Reset Q
R R

ASYNCHRONOUS SYNCHRONOUS

Outputs of logic circuit can Clock signal determines exact

change state anytime one or time at which any output can
more input changes change state
 Clock
Digital signal in the form of a rectangular
or square wave

Astable
multivibrator

A clocked flip flop changes state only when

permitted by the clock signal
 TRIGGERING OF FLIP-FLOPS

• Level-triggering is the transfer of data from input to

output of a flip-flop anytime the clock pulse is proper
voltage level.
• Edge-triggering is the transfer of data from input to
output of a flip-flop on the rising edge (L-to-H) or falling
edge (H-to-L) of the clock pulse. Edge triggering may be
either positive-edge (L-to-H) or negative-edge (H-to-L).

Negative-edge triggering
Positive-edge triggering

L
time
Level triggering
 CLOCKED R-S FLIP-FLOP

Symbols: Set FF Normal

S Q
Clock
CLK
Reset Q
R Comple-
mentary

Truth Table:
Mode of operation Inputs Outputs
Clk S R Q Q’
Hold + pulse 0 0 no change
Reset + pulse 0 1 0 1
Set + pulse 1 0 1 0
Prohibited 1 1 1 1

NOTE: Active-High inputs

 TEST
What is the mode of operation of the clocked R-S flip-flop (set, reset, hold)?
What is the output at Q from the clocked R-S flip-flop (active HIGH inputs)?

H
?High
^

L Mode of operation = ? Set

L
?High
^
Mode of operation = ?Hold
L

L
?Low
^

H
Mode of operation = ?Reset
CLOCKED R-S FLIP-FLOP
TIMING DIAGRAMS
 TEST

1. Type of flip flop where the outputs of circuit can change state anytime
one or more input changes? ASYNCHRONOUS

2. Type of flip flop where the clock signal controls when any output can
change state? SYNCHRONOUS

3. What do we call a digital signal in the form of a repetitive pulse or square wave?
CLOCK

4. Which is easier to design and troubleshoot, clocked or not clocked flip flops?

Clocked flip flops are easier to troubleshoot because we can

stop the clock and examine one set of input and output
conditions.
 POSITIVE EDGE TRIGGERED
Symbols: R-S FLIP-FLOP
EDGE TRIGGERED R-S FLIP FLOP
SET Q

CLOCK

Q NOT
RESET

CLK SET RES Q NOT-Q MODE

PGT 0 0 NO CHG HOLD
PGT 0 1 0 1 RESET

Truth Table: PGT 1

PGT 1
0 1 0 SET
1 1 1 INVALID
CLK R S Q
0 X X NO CHG
1 X X NO CHG
X X NO CHG

0 0 NO CHG
0 1 SET
1 0 RESET
1 1 ILLEGAL
 POSITIVE EDGE TRIGGERED
R-S FLIP-FLOP
TIMING DIAGRAMS

C
R
CLK R S Q
0
0
0
1
NO CHG
SET
S
1 0 RESET
1 1 ILLEGAL Q
 NEGATIVE EDGE TRIGGERED
Symbols: R-S FLIP-FLOP
EDGE TRIGGERED R-S FLIP FLOP
SET Q

CLOCK
EDGE
DETECTOR
Q NOT
RESET

CLK SET RES Q NOT-Q MODE

PGT 0 0 NO CHG HOLD
PGT 0 1 0 1 RESET

Truth Table: PGT 1

PGT 1
0 1 0 SET
1 1 1 INVALID
CLK R S Q
0 X X NO CHG
1 X X NO CHG
X X NO CHG

0 0 NO CHG
0 1 SET
1 0 RESET
1 1 ILLEGAL
NEGATIVE EDGE TRIGGERED
R-S FLIP-FLOP
TIMING DIAGRAMS

C
R
CLK R S Q
0
0
0
1
NO CHG
SET
S
1 0 RESET
1 1 ILLEGAL Q
 FLIP-FLOP TYPES
RS FLIP FLOP (Reset/Set) a.k.a. Set/Clear
S Q
CLK •Most basic flip flop can be made by cross
R Q coupling NAND or NOR gates
•Activating Set and Reset is invalid
D Flip Flop (Data or Delay)
D Q
•Has only a single data input and clock input
CLK Q •Input transfers to output on clock pulse

T Flip Flop (Toggle)

Q
T •Output toggles on each clock pulse
Q •Q output divides clock frequency in half

J-K Flip Flop

J Q
CLK •Universal, can make all other flip flops
K Q •Has no prohibited states
 POSITIVE LEVEL TRIGGERED
Symbol: D FLIP-FLOP
D Q

CLK
Q NOT

Truth Table:
POSITIVE LEVEL TRIGGERED
D FLIP-FLOP
TIMING DIAGRAMS
POSITIVE EDGE TRIGGERED
D FLIP-FLOP
TIMING DIAGRAMS
 NEGATIVE EDGE TRIGGERED
T FLIP-FLOP Symbol:

•Output toggles on each clock pulse

•Q output divides clock frequency in half
•Usually made with JK Flip Flop

Truth Table:
CLK Q
QO

Q= Q O
MEANS THAT THE NEW VALUE OF Q WILL BE THE
INVERSE OF THE VALUE IT HAD PRIOR TO THE NGT
NEGATIVE EDGE TRIGGERED
T FLIP-FLOP
Timing Diagrams

Q
J-K FLIP-FLOP

•UNIVERSAL Flip Flop can make all

others from JK (D and T)

•J acts like SET, K acts like RESET

•No illegal state, activating both

inputs causes Q to TOGGLE
 J-K FLIP-FLOP Symbol:
J Q

CLOCK

Q
K NOT

Truth Table:
CLK J K Q MODE
0 X X NO CHG HOLD
1 X X NO CHG HOLD
X X NO CHG HOLD

0 0 NO CHG HOLD
0 1 0 RESET
1 0 1 SET
1 1 QO TOGGLE
 NEGATIVE EDGE TRIGGERED
J-K FLIP-FLOP
Timing Diagrams
C

J
CLK J K Q
0 0 NO CHG K
0 1 0
1 0 1 Q
1 1 QO

Q
 POSITIVE EDGE TRIGGERED
J-K FLIP-FLOP
Timing Diagrams
C

K
CLK J K Q Q
0 0 NO CHG
0 1 0
1 0 1
C
1 1 QO
J

Q
ASYNCHRONOUS OVERRIDES

Asynchronous Inputs a.k.a. Overide Inputs

operate independent of the control and
clock inputs

PRE PRESET
Active-low override Q=1
overrides all other inputs

CLR CLEAR
Active-low override Q=0
overrides all other inputs
 J-K FLIP-FLOP
ASYNCHRONOUS OVERRIDES

PRE CLR Q*
1 1 No effect; FF can respond to J, K, and CLK
1 0 Q=0 independent of synchronous inputs
0 1 Q=1 independent of synchronous inputs
0 0 Ambiguous (not used)

*CLK can be in any state

 J-K FLIP-FLOP
ASYNCHRONOUS OVERRIDES
Timing Diagrams
 J-K FLIP-FLOP

Symbol:

Truth Table:
Mode of Operation Inputs Outputs
PS Clr Clk J K Q Q’
Asynchronous set 0 1 x x x 1 0
Asynchronous reset 1 0 x x x 0 1
Prohibited 0 0 x x x 1
1
-------------------------------------------------------------------------
Hold 1 1 ^ 0 0 no change
Reset 1 1 ^ 0 1 0 1
Set 1 1 ^ 1 0 1 0
Toggle 1 1 ^ 1 1 opposite

x = Irrelevant
^ = H-to-L transition of clock pulse
 What is the mode of operation of the J-K flip-flop?
TEST What is the output at Q from the J-K flip-flop?

L H
L H
^
?High ^ ?High
H Mode of H
Mode of
H operation = ?Preset H
operation = ?Toggle

H H
H H
^
?Low ^ ? Low
H Mode of H
Mode of
H operation = ?Toggle H operation = ?Toggle

H H
L H
^
?Low ^ ? Low
H Mode of H
Mode of
H operation = ? Reset L operation = ? Clear
SCHMITT TRIGGER OPERATION

Positive-going threshold

Negative-going threshold

Output
Input

Schmitt trigger device

“squares” up input
Digital Electronics
Electronics Technology

Landon Johnson

Counters
 COUNTER UNIT

• Asynchronous up and down counters

• Asynchronous modulus counters
• Seven segment displays/ BCD coding
• Synchronous Counters
• Pre-settable Counters
• Ring Counters
COUNTERS CHARACTERISTICS

1. MODULUS- number of counts in one cycle

2. Up or down count

3. Asynchronous or synchronous operation

4. Free running or self stopping

 ASYNCHRONOUS COUNTERS
•Only LSB flip-flop controlled by the clock input

•Also known as a RIPPLE COUNTER

•Two or more “T” flip-flops interconnected, output

of each flip-flop connected to clock input of the next.

•Modulus- number of stable states in each flip-flop cycle

•Modulus = 2 N
N= number of flip-flops
N 1
•Highest number in count = 2
BUILD A 4 BIT RIPPLE COUNTER
1. 4 JK flip-flops in toggle mode- all JK inputs tied high

2. Q outputs connected to clock input of following flip-flop

3. FF A = LSB (one with clock input); toggles when input clock

toggles from high to low; FF D = MSB
4. FF B, C, D do not toggle till receive NGT from proceeding FF

5. Direction of count can be reversed by complementing

each FF’s output or complementing each FF’s input

D C B A

D J 1 C J 1 B J 1 A J 1
CLK CLK CLK CLK
D K 1 C K 1 B K 1 A K 1
 TEST
1. What is the term for the number of counts in one counter cycle?
Modulus of the counter

2. How is the modulus determined?

2 N N  number of flip  flops

3. Since only the first flip-flop of a ripple counter is controlled by a clock,

the counter is ____________________?
Asynchronous
4. What is the mod number of a counter containing 5 flip-flops?
32
5. What is the highest count of a four bit counter?
31
PROGRAMMING A RIPPLE COUNTER
•Counters may be made to recycle after any desired count
by using a gate to reset the counter.

CONVERT MOD 8 TO MOD6

INPUT CLK
C B A
C B A
0 0 0 0
C J 1 B J 1 A J 1 1 0 0 1
CLK CLK CLK 2 0 1 0
1 1 3 0 1 1
C K 1 B K A K
4 1 0 0
5 1 0 1
UNSTABLE
6 1 1 0
B STATE
master 7
reset
C

3 FLIP FLOPS
2  MOD 8
3

HIGHEST COUNT  2  1  7 3
HOW TO BUILD A COUNTER TO GO
FROM ZERO TO MOD NUMBER X
1. Determine smallest number of FF’s such that 2 X
N

IF 2  X , SKIP STEPS 2 AND 3

N

2. Connect a NAND gate output to asynchronous clears of all FF’s

3. Determine which FF’s will be high at count = X

Connect the Q outputs of these FF’s to NAND gate inputs
BUILD A COUNTER THAT COUNTS
FROM ZERO TO NINE (X=MOD 10)
1. Determine smallest number of FF’s such that 2 X
N

2  8 and 2  16
3 4
thus 4 FF’s are required

2. Connect a NAND gate to asynchronous clears of all FF’s

3. Determine which FF’s will be high at count = X

Connect the Q outputs of these FF’s to NAND gate inputs
1 0 1 0
D C B A

D J 1 C J 1 B J 1 A J 1
CLK CLK CLK CLK
D K 1 C K 1 B K 1 A K 1
 SELF-STOPPING COUNTER

•Counters may be made to stop counting after any desired count

by using a gate to inhibit the clock.

•Stop at desired count:

Stop at 1010  10102

1 0 1 0

D J 1 C J 1 B J 1 A J 1
CLK CLK CLK CLK
D K 1 C K 1 B K 1 A K 1

D
C
B
A
 PROGRAMMING COUNTERS
USING JK INPUTS
•Counters can be controlled using the JK inputs

•Low on JK of 1st FF will cause it to stop toggling on any count

•High or low at JK inputs forces counter to skip states

1 1 0 0

D J 1 C J 1 B J 1 A J
CLK CLK CLK CLK
D K 1 C K 1 B K 1 A K

D
ASYNCHRONOUS DOWN COUNTER
•Direction of count can be reversed by
(a) complementing each FF’s output or
(b) complementing each FF’s input
 COUNTER PROBLEM
1. What is the value of the last usable state before the
NAND gate resets 1101  1310
the 2circuitry?
2. What value does the NAND gate reset the value to?
1000 2  810
3. What is the modulus of this counter?6
4. If count starts at decimal 11 and receives seven clock
pulses, what is the new value 12
on10 the counter?
5. What is the unstable state of the counter?
1110 2  1410
A B C D

0V S S S S
J Q J Q J Q J Q
CP CP CP CP
K QN K QN K QN K QN
R R R R
 COUNTER PROBLEM
1112  710
1. What is the value of the unstable state, in decimal?
0112  310
2. At what value does the NAND gate set the counter to?
3. If QA=1, QB=1, and QC=0, and 5 clock pulses are applied:
QC= 1 QB= 0 QA= 0
4. What is the modulus of this counter?
4
1 2 4
A B C

+V +V +V
S S S
0V J Q J Q J Q
CP CP CP
K QN K QN K QN
+V R R R
IC ASYNCHRONOUS COUNTERS
Logic Diagram for 7493

___ J Q J Q J Q J Q
CPo CP
K QN
CP
K QN
CP
K QN
CP
K QN
R R R R
___
CP1
Qo Q1 Q2 Q3
MR1 (LSB) *All J, K inputs internally (MSB)
MR2 connected HIGH
7493 AS A MOD-16 COUNTER
Logic Diagram for 7493

___ J Q J Q J Q J Q
CPo CP
K QN
CP
K QN
CP
K QN
CP
K QN
R R R R
___
CP1
Qo Q1 Q2 Q3
MR1 (LSB) *All J, K inputs internally (MSB)
MR2 connected HIGH

___
CP 1
7493 10 kHz
___
CP o

Qo
MR 1 MR 2 Q 3 Q2 Q1

F= 10 kHz/16 = 625 Hz
 TEST
Build a MOD 10 counter
Logic Diagram for 7493 with a
___ J Q J
7493
Q J Q J Q
CPo CP
K QN
CP
K QN
CP
K QN
CP
K QN
R R R R
___
CP1
Qo Q1 Q2 Q3
MR1 (LSB) *All J, K inputs internally (MSB)
MR2 connected HIGH

___
CP 1
7493 10 kHz
___
CP o

MR 1 MR 2 Q 3 Q2 Q1 Qo

F= 10 kHz/10 = 1KHz
 BCD COUNTER
•Binary counter that counts from 0000 to 1001 before it recycles
(MOD-10).
•Widespread applications where pulses or events are to be
counted and the results displayed on a decimal numerical
read-out.
•Also used for dividing a pulse frequency exactly by 10.

Cascading BCD counters to count and display from 000 to 999.

 MOD-60 COUNTER

MOD 6 MOD 10

___ ___
CP 1 CP 1
7493 7493
___ ___
CP o CP o
f in
MR 2 Q 3 Q2 Q1 Qo MR 1 MR 2 Q 3 Q2 Q1 Qo
not
used

f out = f in /60 f in /10

Two 7493s can be combined to produce a MOD-60

Counter
DIGITAL CLOCK
 COUNTERS
ASYNCHRONOUS

S S S S
J Q J Q J Q J Q
CP CP CP CP
K QN K QN K QN K QN
R R R R

SYNCHRONOUS

S S S S
D Q D Q D Q D Q
CP QN CP QN CP QN CP QN
R R R R
 SYNCHRONOUS COUNTERS
•Two or more FF’s connected as “T” FF’s.

•All FF’s in the counter are clocked at the same time.

•Advantage over the ripple counter is speed and accuracy but more complex

5V 5V
+V

S S S S
Q J Q J Q J Q J
CP CP CP CP
QN K QN K QN K QN K
R R R R
5V
0V

D C B A
SYNCHRONOUS COUNTERS
MOD <2
N

•A NAND control gate is used to clear the counter before the

full count.

5V
+V

S S S
S Q J Q J Q J
Q J CP CP CP
CP QN K QN K QN K
QN K R
R R
R
0V

D C B A
SYNCHRONOUS COUNTERS
UP/DOWN
0V

5V

Q J Q J 0V
Q J
CP CP CP
QN K QN K QN K
R R R
5V

5V
PRESETTABLE COUNTERS
Can be preset to any desired count. To operate:
1. Apply desired count to parallel data inputs P2, P1, P0.
2. Apply a low pulse to the parallel load input PL.
P2 P1 Po PARALLEL
DATA INPUTS

5V
+V
S S S
Q J Q J Q J
CP CP CP
QN K QN K QN K
R R R
5V

CLOCK
PARALLEL
LOAD
__
PL
 COUNTER TYPES
Asynchronous Counter (a.k.a. Ripple or Serial Counter):
each FF is triggered one at a time with output of one FF serving
as clock input of next FF in the chain.
Synchronous Counter (a.k.a. Parallel Counter): all the FF’s in
the counter are clocked at the same time.
Up Counter: counter counts from zero to a maximum
count.
Down Counter: counter counts from a maximum count down to zero.
BCD Counter: counter counts from 0000 to 1001 before it recycles.

Pre-settable Counter: counter that can be preset to any starting

count either synchronously or asynchronously

Ring Counter: shift register in which the output of the last

FF is connected back to the input of the first FF.

Johnson Counter: shift register in which the inverted output of

the last FF is connected to the input of the first FF.
 74193 COUNTER
MOD-16 PRESETTABLE UP/DOWN COUNTER
 RING COUNTER
Shift register counter with feedback from Q of last FF back to first
RING FFCOUNTER
input

5V

S S S S
D Q D Q D Q D Q
CP QN CP QN CP QN CP QN
5V R R R R

0V

clk
 JOHNSON COUNTER
Shift register in which the inverted output of the last FF is fed back to
the input of the first FF.
Lab 18.

A PROGRAMMABLE COUNTER
Design a four-bit counter controlled by two control lines X and Y
that behaves according to the truth table.

PROGRAM COUNTER
SWITCH MODE
X Y
0 0 NO COUNT
0 1 MOD 5
1 0 MOD 10
1 1 MOD 12
Lab 18.

A PROGRAMMABLE COUNTER
5V
Q1CP1
Q2CP2

S S S S
Q J Q J Q J Q J
CP CP CP CP
D QN K C QN K B QN K A QN K
R R R R

_
XYAC

_
XYBD

XYCD

MOD 12 1 1 X
MOD 10 0 1
MOD 5 1 0 Y
NO COUNT 0 0
Y X
MODE SWITCH
COUNTER PROGRAM
 RIPPLE COUNTER
Binary Output
Clock Input
00
1 10
101

Pulse 8
1
2
3
4
5
6
7

PS
Onand
This theCLR
4-bit
nextinput
counter
clockhasAll16
pulse J-K
(8)flip-flops
states
all FFs
and
willwill
count are
toggle
frombecause
binary each in
0000 will the
through
receive
1111
INACTIVE
a H-to-L
and then
pulse-
resetone TOGGLE
back
after MODE
to another.
0000.
WatchThethecounter
counthasripple
a modulus
thru theof counter.
16.
RIPPLE COUNTER WITH WAVEFORMS
Binary Output
Clock Input
01
0010
1

Pulse 5
1
2
3
4

Clock input

FFs triggered on 1s output

H-to-L pulse.
CLK toggles 1s FF.
1s FF toggles 2s FF. 2s output
2s FF toggles 4s FF.

4s output
 DECADE COUNTER nt a
t0 111
ou
ial c
Binary Output Init
Clock Input
11
0 00
110

Pulse 8
1
2
3
4
5
6
7
Short negative pulse

To clear input
of each FF

All J & K inputs = 1

All PR inputs = 1

To change mod-16 counter to decade counter:

Count is at 1001.
Reset count to 0000 after 1001 (9) count.
Next clock pulse will increment counter for a
When count hits 1010 reset to 0000.
short time to 1010 which will activate the NAND gate
See added 2-input NAND gate that clears all
and reset the counter to 0000.
JK FFs to 0 when count hits 1010.
 DOWN COUNTER
t
a l c oun
Initi t at
se
r y 111
bin a
11
0 00
1

4
2
1
Pulse 5
3

Changes from Ripple Up Counter are

wiring from Q’ outputs (instead of Q outputs)
to the CLK input of the next FF.
 SELF-STOPPING DOWN COUNTER

The u n t on
tch coremained
Wacount
10
0 10
1 .
Pulse 8000.
at binary

2
3
4
Pulse 8
1
5
6
7

This is a 3-bit down counter.

The 1s FF is in TOGGLE mode when counting (J & K = 1).
The 1s FF switches to HOLD mode when the J and K inputs are forced LOW by the OR gate
when the count decrements to 000. The count stops at 000.
COUNTER USED FOR FREQUENCY DIVISION

4
8 200 Hz
100 Hz 400 Hz
50 Hz 2
 16

Clock Input

800 Hz
USING THE 7493 COUNTER IC
• Counters are available in IC form.
• Either ripple (7493 IC) or synchronous
(74192 IC) counters are available.

400
? Hz
Hz
100
? Hz
Hz 800
? Hz
Hz

1600 Hz

7493 Counter IC
wired as a 4-bit
binary counter
MAGNITUDE COMPARATOR
A magnitude comparator is a combinational logic device
that compares the value of two binary numbers and
responds with one of three outputs (A=B or A>B or A<B).

A(0)
A(1) 74HC85
Input
Input
Inputbinary
binary
binary0111
1111
0001
A(2)
Magnitude
Comparator
A(3)
A>B HIGH
B(0)
A=B HIGH
B(1)
Input
Inputbinary
binary
0110
0111
1100 A<B HIGH
B(2)

B(3)
TROUBLESHOOTING EQUIPMENT

• Logic Probe
• Logic Pulser
• Logic Clip (logic monitor)
• Digital IC Tester
• DMM/Logic Probe
• DMM or VOM
• Dual-trace Oscilloscope
• Logic Analyzer
SIMPLE TROUBLESHOOTING HINTS

• Feel top of IC to determine if it is hot

• Look for broken connections, signs of
excessive heat
• Smell for overheating
• Check power source
• Trace path of logic through circuit
• Know the normal operation of the circuit