ASIC FLOW (Application-specific integrated circuit)

• SPECIFICATION: Involves
space, capacity, operating voltage, operating temperature, power, performance.
• BEHAVIORAL DESCRIPTION:
Is then created to analyze the design in terms of functionality, performance.
It is written in Verilog code.
• RTL (register transfer level) DESCRIPTION :
Is done using HDLs. This RTL description is simulated to test functionality.
Describes how data is transformed as it is passed from register to register.
• LOGIC SYNTHESIS:
Logic synthesis tools convert the RTL design description to a gate-level “netlist” or a “list
of wires”. A gate-level netlist is a description of entire chip in terms of logic gates and their
interconnections.
• SCHEMATIC:
Building circuit in terms of logical gates.
At Gate-level netlist both schematic and RTL design is verified.
• FLOORPLANNING:
Involves deciding the arrangement and placement of the components on the
chip.
• PHYSICAL DESIGN :
Transforming the blueprint of a circuit into its actual physical layout on the
chip.
Layout vs. Schematic (LVS) is checked at Layout verification.
Internsic Semiconductor

1.The maximum energy that an electron can get at

the absolute zero temperature is known as the
Fermi Energy.
2.Highest energy level occupied by electron atthe
absolute zero temperature or it is 50% probability
of occupation of electron.
Energy Level Diagram