2.dft_flow

Tessent: Scan and ATPG
Module 2
ATPG Flow
Objectives
Upon completion of this module, you will be able to:
 Use Tessent FastScan or Tessent TestKompress to create

and save patterns.
 Generate ATPG patterns using the default flow.
 Use DFTVisualizer to troubleshoot minor DRC violations.
2-2 • Tessent: Scan and ATPG: ATPG Flow Copyright © 1999-2009 Mentor Graphics Corporation
Full DFT Flow
Design
Design Flow Requirements
Tool Flow
RTL Coding
DRC
Gate Level DFT Library RTL Design
Netlist
Scan SYNTHESIS
Insertion
DRC
DRC Gate Level
Scan Inserted Setup Files
Netlist Netlist
SCAN
INSERTION
ATPG
DRC Scan Inserted
Netlist
Tessent FastScan or Test Patterns
ATPG
Tessent TestKompress
(atpg mode)
Test
ATE Patterns
Verification Simulation
Library
Tessent Diagnosis Failure File
DFT Model Description DFT Library DFT Library
Gate Level
of Scan Cell (DFF) Scan
Netlist
Insertion
//==========================================
Model: DFF Setup Files Scan Inserted
Netlist
//===========================================
model DFF ( PRE,CLR,CLK,D,Q,QB) (
input ( PRE, CLR, D) () ATPG
input(CLK) (clock = rise_edge;)

Test Patterns
output(Q QB) (primitive = _dff(PRE,CLR,CLK,D,QB);
)
//=============================================
Model: MUX_SCAN _CELL Simulation Verification
//============================================== Library
model MUX_SCAN_CELL (PRE, CLR, SC_IN, SC_EN, CLK, D, Q,

QB) (
scan_definition ( Maps non-scan models (DFF)
type = mux_scan to library replacements:
scan_in = SC_IN;
Mux_Scan_Cell Library Model
scan_enable = SC_EN;
scan_out = Q, QB;
non_scan_model = DFF ( PRE, CLR, CLK, D, Q, QB); PRE
)
D N_2 DFF 1
input (PRE, CLR, SC_IN, SC_EN, CLK ()
intern(N_2) (primitive = _mux mux1 (D, SC_IN, SC_IN S_out (Q)
MUX 1 D
SC_EN,N_2);)
output(Q, QB) (primitive = _dff dff1(PRE, CLR, CLK, SC_EN DFF
N_2, Q, QB);) CLK
) CLR
//============================================
DFT Library (Cont.)
 The DFT library is a function of the lowest level netlist
modules.
 Very similar to Verilog.
 Maps non-scan models to their associated scan models.
 No DFT model is needed for Verilog primitives.
 Example: Verilog “and” maps directly to the built-in primitive
“and” in DFT tools.
Creating a DFT Library
 Check for an existing library from the vendor.
 Use the libcomp utility to make a DFT library from Verilog.
 libcomp is a shell command.
 Technical marketing or support will help with any library
conversion issues.
Automatic Generation of DFT Libraries
 Automatically converts Verilog simulation library
 Translates and optimizes UDPs
 Automated verification of translated models
 Reports coverage per model
 Reduces the effort in creating an ATPG library
Verilog
simulation
lib libcomp
do_file
ATPG
lib
libcomp <verilog_file> -dofile <file_name>
Command Syntax and Structure
 Tessent FastScan and Tessent
TestKompress use this command
syntax:
 > ADD
(Defines a condition.) 3-2-1 Example
 > REPort
(Displays added items.) >ADD Input Constraint -C1
 > DELete
(Removes a condition.) >ANAlyze COntrol Signals
 > SET/SETup >REPort CLocks
(Defines global settings.)
 > WRIte/SAVe
(Generates files.)
 ANAlyze Control Signals
(Identifies and defines primary
inputs of control signals.)
 3-2-1 command structure:
 Minimal typing: no need to type out
the entire command.
– Type the first three letters of the
first word, two letters of the
second, and one letter of the third.
ATPG Tool Flow With Commands
Invoking Tessent FastScan
 The Tessent FastScan executable resides in the Mentor Graphics

tree at <mgcdft tree>/bin/fastscan.
 Invocation requirements:
 Scan-inserted netlist.
 DFT library.
Invocation:
shell> fastscan design.v -verilog \
-lib dft.lib -log transcript.log –replace
Invoking Tessent TestKompress in ATPG Mode
 Tessent TestKompress can be run in ATPG mode.

 No edt is created.
 Uses Tessent FastScan flow and commands, but no GUI.
 Use set edt off once the tool is invoked to run in traditional ATPG
mode.
 Invocation requirements are the same as Tessent FastScan.
Invocation:
shell> testkompress design.v -verilog \
-lib dft.lib –dofile dft_atpg.do \
-log transcript.log –replace
After invocation:
SETUP> set edt off
Set constraints if Tessent TestKompress logic exists in design:

SETUP> add input constraints edt_bypass -c1
Invoking Tessent TestKompress in ATPG Mode (Cont.)
 Why run Tessent TestKompress in Tessent FastScan (atpg)
mode?
 Perform this step to ensure there are no basic issues such as
simulation mismatch caused by an incorrect library.
 Enables you to make comparisons of test performance on a
design using EDT versus not using EDT.
 Optional.
 Can use to run ATPG on blocks without Tessent TestKompress
(validate testability).
 Can bypass Tessent TestKompress logic.
ATPG Setup
 What you have:
 A gate-level, scan-inserted netlist (Tessent FastScan or Tessent
TestKompress)
 Test Procedure File
– Required if there is already preexisting scan circuitry in your design
– Defines the operation of that preexisting scan circuitry
 Setup files:
– Dofiles
• Tessent FastScan/Tessent TestKompress: Contains circuit setup
information specified from the scan insertion tool
• Contains information on test structures inserted into the design
– Test Procedure File
• Tessent FastScan/Tessent TestKompress : Defines operation of scan
circuitry
 A DFT library:
– Used by Tessent TestKompress and Tessent FastScan
ATPG Setup (Cont.)
ATPG Setup Dofiles contain setup

commands and information about
the circuit and inserted test
structures that are generated by
scan insertion tools.
Simple test procedure files are used in

Tessent FastScan or Tessent FastScan and Tessent TestKompress.
Auto Black Boxing for Incomplete Netlists
ADD Black Box -Auto

D Q
CLK
QN
R 000 XXX
PI_1 PO_1
PI_2 PO_2
PI_3 PO_3
D Q
CLK Module M
QN
Undefined Library
Defined Library Model
Models
Black Boxes
Copyright 2001-2008 Mentor Graphics Corporation
//
 Allows analysis of incomplete
// All Rights Reserved. designs.
//
// THIS WORK CONTAINS TRADE SECRET AND
 Isolates analog blocks.
PROPRIETARY INFORMATION WHICH
// IS THE PROPERTY OF MENTOR GRAPHICS
 Isolates proprietary IP.
CORPORATION OR ITS LICENSORS AND IS
// SUBJECT TO LICENSE TERMS.  Warns of undefined model
//
// Mentor Graphics software executing under x86 Linux.
instances.
// 32 bit version  The undefined model is not
//
// Compiling library ... black boxed.
// Reading DFT Library file ../../libraries_1_to_4/adk.atpg
// Finished reading file ../../libraries_1_to_4/adk.atpg  Use the ADD BLack Box
// Reading Verilog Netlist ...
// Reading Verilog file module4_1.v
-Auto command to black box
// Warning: Module name 'mux21_macro' near line '4', conflicts all undefined models or
with a lib model, lib model will be ignored
// Finished reading file module4_1.v modules.
// Warning: Following modules are undefined:
// tbuf  Use in setup mode.
// picdram
// nand02_tst
// Use "add black box -auto" to treat these as black boxes
//
// command: ADD BLack Box -Auto
Black Box Examples
 Example to create a black box for module core with tie value
of X (default).
SETUP> ADD BLack Box -module core
 Change output behavior of black boxes:
SETUP> ADD BLack Box -instance core1 -pin pin1 1
 Restore the original model:
SETUP> DELete BLack Box -module core
SETUP> DELete BLack Box -module core1
OR
SETUP> DELete BLack Box -All
 Report on any instance- or module-based black box:
SETUP> REPort BLack Box -All
SETUP
Tessent FastScan or
Commands (in dofile or type at command line):

ADD INput Constraints
ADD CLocks
ADD SCan Groups
ADD SCan Chains
SETUP (Cont.)
 Setting up the circuit includes several tasks:
 Constraining primary inputs.
– Holds specified pins at a constant value during ATPG.
– Define during setup mode.
SETUP> ADD INput Constraints control -C1
//constrain to constant 1
 Adding clocks.
– Adds scan or non-scan clock pins to the clock list.
– Any signal that can change the state of a sequential element is
considered to be a clock.
• Clock, set, reset signals.
– Clock must have an off state, and that value must be specified.
SETUP> add clocks 0 clk1
SETUP> add clocks 0 pll_block/clk1 -internal
SETUP (Cont.)
 Analyzing control signals.
– Identifies each control signal (clock, set, reset, read-control, write-
control, etc.) of every sequential element (DFF, latch, RAM, ROM, etc.)
– Optionally defines its primary input as a control signal.
– -Auto_fix argument performs an implicit ADD CLocks command.
– Only traces through simple combinational gates.
– Does not support gated clocks.
– Will not alter a clock definition specified by a preceding add clocks
command.
SETUP> ANAlyze COntrol Signals -Auto
SETUP (Cont.)
 Adding scan groups.
– Defines a scan chain group.
– Test procedure file controls the set of scan chains in the scan chain
group.
– Must specify the name of the test procedure file.
SETUP> add scan groups grp1 file.testproc
 Adding scan chains.
– Adds a scan chain to a scan group.
– Defines a scan chain that exists in the design.
SETUP> add scan chains chain1 grp1 my_scan_in[1]
my_scan_out[1]
ATPG in a DC Scan Insertion Flow
ATPG Setup Files
 ATPG setup files are:
 Used to enter ATPG setup information.
> DOFile <name.dofile>
 Created manually or interactively.
 Automatically created by DFTAdvisor.
 Created from STIL files.
SHELL> stil2mgc -stil cpucore.stp -tpf cpucore.tpf –dofile
cpucore.do
TEST PROCEDURE FILE

DOFILE // Written by STIL2MGC on Wed May 27 12:45:09 2009
//
set time scale 1.000000 ns ;
// Written by STIL2MGC on Wed May 27 12:45:09 2009 set strobe_window time 5 ;
//
add clock 1 Clk timeplate _default_WFT_ =
add scan group group1 cpucore.proc force_pi 0 ;
add scan chain c0 group1 test_si test_so[0] measure_po 40 ;
pulse Clk 45 10;
period 100 ;
end;
ATPG Setup Dofile
 Specifies circuit setup and
scan information for test
pattern generation
 Defines the following:
– Clocks
– Scan operation
– Scan chains
– Pin constraints
DOFILE
//
add scan groups grp1 counter_syn_scan.testproc
add scan chains chain1 grp1 scan_in1 scan_out1
add clocks 0 clock4
add clocks 0 clock3
add clocks 0 clock2
add clocks 0 scan_reset
add clocks 0 clock1
add input constraints test_en -C1
~
Test Procedure File
Describes the order of events for a test

pattern set.
 Test_Setup (initialization)
- Sets non-scan state elements to a
constant state.
 Load_Unload
- Defines how to load and unload scan
chains in a scan group.
- Defines how to shift data one position down
the scan chain.
Introduces timing to test patterns

 Test patterns are divided into cycles.
Test Procedure File (Cont.)
force_sci force_sci force_pi
measure_sco measure_sco measure_po
CLOCK
0 10 20 30 40 0 10 20 30 40 0 10 20 30 40
Cycle time 0 10 20 30 40 0 10 20 30 40 0 10 20 30 40
0 10 20 30 40 50 60 70 80 90 100 110 120 130 140 150 160 170 180 190 200 210 220 230 240
Total time
1. test_setup 2. load_unload 3. shift 4. shift 5. capture 6. load_unload
timeplate tp0 = 1. procedure test_setup = 2.,6. procedure load_unload =

force_pi 0; timeplate tp0 ; scan_group grp1 ;
measure_po 10; cycle = timeplate tp0 ;
pulse CLOCK 20 10 ; force A 0 ; cycle =
period 40 ; force B 1 ; force scan_en 1 ;
end ; force C 0 ; force CLOCK 0 ;
end ; end ;
end; apply shift 2 ;
end;
3.,4. procedure shift = 5. procedure capture =
scan_group grp1 ; timeplate tp0 ;
timeplate tp0 ; cycle =
cycle = force_pi ;
force_sci ; measure_po ;
measure_sco ; pulse_capture_clock ;
pulse CLOCK ; end ;
end ; end ;
end;
Elements of Scan Timeplates
 A timeplate defines a time period corresponding to the ATE
cycle.
 Multiple timeplates can be defined as long as timing, period and
the number falls within the limitations of the target ATE.
 Non-return input formats are defined with the force statement.
 Return formats are defined with the pulse statement using
delay and width variables.
Procedures
 There are three main procedures for shifting data:
 Test_setup — Initializes the device in preparation for test.
(Includes JTAG controller programming)
 Load_unload — Shifts data in order to load and unload scan
data into and out of scan chains. (Includes the shift procedure)
 Capture — After scan data has been loaded, the capture cycle
applies the circuit tests and prepares for unload.
Sequence of Cycles for Structured Test — Mux D
The test_setup procedure The load_unload procedure defines
provides the initialization sequence the stable cycles for shifting data into
to prepare the design for testing. and out of the scan chains.
procedure test_setup = procedure load_unload = procedure shift =

timeplate tp1 ; scan_group grp1 ; scan_group grp1 ;
cycle = timeplate tp1 ; timeplate tp1 ;
force clk 0 ; cycle = cycle =
force scan_en 0 ; force clk 0 ; force_sci ;
pulse clk ; force scan_en 1 ; measure_sco ;
end ; end ; pulse clk ;
cycle = apply shift 5; end;
pulse clk ; end; end;
end ;
end;
Load_Unload and Shift Procedures
 The purpose of the load_unload procedure is to define the shift
process to load and unload the scan chains with pattern data from
ATPG.
 The shift procedure defines the clocks and conditions needed to
move the scan data one scan cell position.
 The shift procedure uses force_sci and measure_sco as the timing
points for data input and measure output.
 The default is (force_sci = force_pi) and (measure_sco = measure_po).
DRC (Tessent FastScan or Tessent TestKompress)
This task does the following:

 Exits SETUP mode
 Flattens the netlist into internal DB
or Tessent FastScan  Runs DRC
 Specifies to the tool to enter Test Pattern
Generation system mode
Command:
SETUP> SET SYstem Mode Atpg
DRC
 ATPG Command:
SETUP> SET SYstem Mode atpg
 This command does the following:
 Exits SETUP mode
 Performs DRC
 Flattens the design
 Performs learning analysis
DRC Basics
 Passing rules checking is vital for the successful use of the
DFT tools.
 Rule violations are handled in four ways:
1. Error:
– Rules checking is terminated and tool remains in SETUP mode.
2. Warning:
– Indicates the number of violations. SETUP> SET DRc Handling
3. Note:
– Summary message that displays number of violations.
4. Ignore:
– No message given.
User-defined handling
of displayed messages
DRC Basics (Cont.)
Each rule is assigned a rule and For example:

violation identification number. C1-1
Occurrence:
1st occurrence
Rule type: of violation
Clock Rule
Specific rule:
Scan cell must not capture
data when all clocks are set
to their off states.
Types of DRCs
 RAM rules (A rules)
 Checks for testability conditions of embedded RAMs
 Clock rules (C rules)
 Verifies clock operation
 Data rules (D rules)
 Checks the stability of the data in the scan chains
 Extra rules (E rules)
 Checks for potential problems—usually ignored by the tool
 Procedure rules (P rules)
 Ensures test procedure file is syntactically and functionally
correct
 Timing Rules (W rules)
 Ensures that the order of events has not changed since leaving
setup mode
Tracing Back to the X Source With DFTVisualizer
SETUP> open visualizer

or
SETUP> analyze drc violation C1-1
Tracing Back to the X Source With DFTVisualizer (Cont.)
Command
X on the S0 input of
f1_clk_sel
The Transcript window mirrors

commands typed at the tool prompt.
Change display to gate-level by selecting Display > Gate Level > Primitive
Click the pin where the X is

to trace backwards.
Source of the C1 violation.

The control signal is not
being forced off.
Open the dofile in the

Text Editor window.
Add the input constraint to

fix the problem.
View Design Elements in Fixed Design
Constraint fixed;
design loads.
Configuration
 Define configuration
 Default settings are stuck-at-faults

and combinational (basic) patterns
Commands:
SETUP> SET FAult Type
SETUP> ADD NOfaults
ATPG> SET PAttern Type
ATPG> ADD Faults Note: ATPG Expert adds faults automatically.
Generate Patterns
 Generate patterns
 View ATPG results
Command:
ATPG> CREate PAtterns
Create Patterns
 CREate PAtterns automatically analyzes the design
including explicitly specified settings to generate the most
compact test pattern set with the highest coverage and
lowest runtime.
 Use the -OVerride_user_settings option to override

explicitly specified settings, if necessary, to create an optimal
test pattern set.
 Use the -NO_Auto option to disable the analysis and generate

test patterns based on explicitly specified settings and
defaults for all other settings. (Not recommended.)
Save Results
Tessent FastScan or
 Save patterns
Command:
ATPG> SAVe PAtterns <filename>
Saving Test Patterns
 Supports many ASIC vendor
formats
 WGL
 STIL
 Recommended saving Saving Patterns
practices:
-------------------------------------------
 ASCII or binary #test_patterns 48
#simulated_patterns 416
– Used later in Tessent FastScan CPU_time (secs) 0.4
or Tessent TestKompress. -------------------------------------------
// command: save patterns pat1_ser.v -procfile -serial -verilog -replace
 ASIC vendor format for tester // command: save patterns pat1_par.v -procfile -parallel -verilog -replace
// command: save patterns pat1_ascii -ascii -replace
 Verilog test bench // command: exit -d
– Used later for time-based
simulation/verification
 Flattened model
– Used later for diagnosis
Lab 2: Generating Test Patterns
During this lab, you will
 Invoke Tessent TestKompress in ATPG mode to create,

compress, and save patterns.
 Invoke DFTVisualizer to troubleshoot minor Design Rules
Checking (DRC) violations.

2.dft_flow

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Tessent: Scan and ATPG

Upon completion of this module, you will be able to:

 Use Tessent FastScan or Tessent TestKompress to create

Tessent Diagnosis Failure File

input(CLK) (clock = rise_edge;)

model MUX_SCAN_CELL (PRE, CLR, SC_IN, SC_EN, CLK, D, Q,

libcomp <verilog_file> -dofile <file_name>

 The Tessent FastScan executable resides in the Mentor Graphics

 Tessent TestKompress can be run in ATPG mode.

Set constraints if Tessent TestKompress logic exists in design:

ATPG Setup Dofiles contain setup

Simple test procedure files are used in

ADD Black Box -Auto

Commands (in dofile or type at command line):

TEST PROCEDURE FILE

Describes the order of events for a test

Introduces timing to test patterns

1. test_setup 2. load_unload 3. shift 4. shift 5. capture 6. load_unload

timeplate tp0 = 1. procedure test_setup = 2.,6. procedure load_unload =

procedure test_setup = procedure load_unload = procedure shift =

This task does the following:

Each rule is assigned a rule and For example:

SETUP> open visualizer

The Transcript window mirrors

Click the pin where the X is

Source of the C1 violation.

Open the dofile in the

Add the input constraint to

 Default settings are stuck-at-faults

 View ATPG results

 Use the -OVerride_user_settings option to override

 Use the -NO_Auto option to disable the analysis and generate

 Invoke Tessent TestKompress in ATPG mode to create,

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