CHAPTER 5

LOW POWER COMPUTING

 Contents

Sources of energy consumption,

instruction-level strategies for power

management,
 memory system power consumption,

system-level power management

 Introduction

 Power consumption is one of the most important constraints in embedded

system design.
 Two main reasons motivated the constant effort of designers to reduce

consumption.

1. in many cases, embedded systems are designed for mobile

applications using limited battery life

2. thermal dissipation is constrained by cost, weight and size,

 working temperature shall be kept low enough to allow cheap packaging

and maintain system reliability above the required level.

 Research Areas Regarding to Power Consumption

There are two ways that the researchers are doing

research to improve the energy problems in embedded
systems.
† reducing the energy consumption in the system
† increasing the battery life
Understanding the sources of energy consumption is
crucial for targeting optimization efforts
So what are the sources of energy consumption?
 Sources of energy consumption

Most energy consumed in:

 CPU,
 display,
 hard disks LCD display
 CPU power consumption

 Most modern CPUs are designed with power consumption in

mind to some degree

 CPUs are significant consumers of energy in embedded

systems
 employing low-power processor architectures, and utilizing

techniques like dynamic voltage and frequency scaling can

help reduce CPU energy consumption
 CPUs power consumption

Voltage drops: power consumption proportional to V2:

Ps=CLVdd2fs
Toggling (switching): more activity means more power

Leakage: basic circuit characteristics; can be eliminated

by disconnecting power
 Power reduction techniques

Circuit Level
 Voltage scaling
 Clock gating

System Level
 Power saving modes
 Cache organization
Instruction level
 Instruction Base Costs
 Pipeline Stalls
 Power reduction techniques

Circuit Level
a) Voltage Scaling:
o Adjusting the supply voltage (Vdd) of the circuit to reduce

power consumption without sacrificing performance.

o Lowering the supply voltage decreases the power dissipation

in the circuit, but it must be done carefully to avoid reliability

issues.
 Power reduction techniques

Circuit Level
b) Clock Gating:
o Disabling the clock signal to idle or inactive circuit blocks when

they are not in use.

o This prevents unnecessary switching activity and reduces

dynamic power consumption in the circuit.

c) Dynamic frequency scaling:

o Changing the clock speed of the processor based on workload can

reduce power consumption.

 Memory system power consumption:

Memory Technology:

 Different memory technologies, such as DRAM, SRAM, and non-volatile memories

exhibit varying power consumption characteristics. For example, DRAM consumes

more power than SRAM due to its higher density and due to refresh cycles.

Memory hierarchy:

 The memory hierarchy, which includes levels of cache, main memory (DRAM), and

secondary storage, plays a crucial role in determining power consumption.

 Caches closer to the processor typically consume less power due to their smaller

size and faster access times, while larger and slower memory modules consume

more power.
 Power reduction techniques

System Level

a) Power saving modes:

o Implementing various power-saving modes such as sleep,

idle, and standby modes where non-essential components or
subsystems are shut down or placed in low-power states.
These modes are particularly effective in reducing static
power consumption during periods of inactivity.
 Power reduction techniques

System Level
b) Cache Organization

o Optimizing cache configurations and access policies to

minimize data movement and reduce energy consumption.
o Techniques such as cache partitioning, selective caching, and
cache bypassing can help improve energy efficiency by reducing
cache-related power overhead.
 Power reduction techniques

Software power minimization

o are crucial for optimizing energy efficiency in computing systems
o B/c software plays a significant role in determining overall power
consumption.
 Instruction-level power management:

o Analyzing the power consumption of individual instructions or instruction

sequences to identify power-intensive operations.

o By understanding the power characteristics of instructions, software

developers can prioritize energy-efficient coding practices and minimize

power-consuming instructions.
 Power reduction techniques

Software power minimization

 Instruction Base Costs:

o Different instructions have varying power consumption profiles

depending on factors such as

 the instruction type,

 execution time, and

 associated hardware resources.

o Minimizing the use of high-power instructions or replacing them

with more energy-efficient alternatives can reduce overall power

consumption.
Power reduction techniques
 Power reduction techniques

Software power minimization

 Pipeline Stalls:

o Caused when the CPU pipeline is temporarily idle due to

data dependencies, cache misses, or branch miss predictions,

o This can lead to inefficient use of hardware resources and

increased power consumption.

o Software techniques such as branch prediction optimization,

loop optimization, and prefetching can reduce pipeline stalls

and improve energy efficiency.
 Power reduction techniques

Software power minimization

 Cache Misses:

o Accessing data from main memory due to cache misses

incurs additional power consumption and latency.

o Software optimizations, such as data prefetching, cache-

conscious data structures, and memory access pattern

optimizations, can reduce the frequency of cache misses
and lower overall power consumption.
 CPU power-saving strategies

 Reduce power supply voltage

 Run at lower clock frequency

 Disable function units with control signals when not in use

 Disconnect parts from power supply when not in use

 Power management styles

 Power management techniques can be categorized into

static and dynamic styles based on their dependence on

CPU activity.
a) Static power management: Static power management
techniques do not depend on the CPU's activity level.
Instead, they involve predefined power-saving modes or
configurations that are activated independently of
workload characteristics.
 Power management styles

Example: User-activated power-down mode is a common

static power management strategy.

 In this mode, the user manually triggers a power-saving

state, such as standby or sleep mode, through system

settings or controls.
 Once activated, the system enters a low-power state,

shutting down or reducing power to non-essential

components while preserving data and system state.
 Power management styles

a) Dynamic power management:

 Dynamic power management techniques adjust power

consumption based on CPU activity levels and workload

demands.
 These techniques involve monitoring system activity in real

time and dynamically adapting power-saving measures to

optimize energy efficiency.
 Power management styles

a) Dynamic power management:

 Example: Disabling idle function units is an example of dynamic
power management.
 In this technique, the system dynamically identifies and

deactivates idle functional units within the CPU or peripheral

devices during periods of low activity.
 By selectively powering down inactive units, the system reduces

dynamic power consumption while maintaining responsiveness

and performance
 Power-down costs

Power-down costs: typically refer to the overhead or

consequences associated with transitioning a computing

system or device into a low-power or power-saving state.
Going into a power-down mode costs:
 Time
 energy
Must determine if going into mode is worthwhile
Can model CPU power states with power state machine
 power state of machine

Prun = 400 mW

run
10 ms
160 ms
90 ms
10 ms
90 ms
idle sleep

Pidle = 50 mW Psleep = 0.16 mW

 Power vs. time running a real application

Pentium processor