computer architecture and organization

Computer Organization & Architecture
DIT 1205, BCS 1102
A Regional University Transcending Boundaries

Computer Organization & Architecture
DIT 1.2, BIT 1.2, BCS 1.2, BSE 1.2
Lecturer: Joseph M. Ssemwogerere.
Contacts:
e-mail: jmssemwogerere@gmail.com
jssemwogerere@vu.ac.ug
Phone: 0777539045 / 0705852367
Lecture Hours
Tuesdays: 8:00a.m. – 11:00 a.m. (online/physical)
11:00a.m. – 2:00 p.m. (online/physical)
2:00p.m. – 5:00 p.m. (online/physical)
Wednesdays: 2:00p.m. – 5:00 p.m. (online/physical)
Saturdays: 11:00a.m. – 2:00 p.m. (online/physical)

Course Description
This course will introduce students to the fundamental concepts
underlying modern computer organization and architecture. Main
objective of the course is to familiarize students about hardware design
including logic design, basic structure and behavior of the various
functional modules of the computer and how they interact to provide
the processing needs of the user. It will cover machine level
representation of data, instruction sets, computer arithmetic, CPU
structure and functions, memory system organization and architecture,
system input/output, multiprocessors, and digital logic. The emphasis is
on studying and analyzing fundamental issues in architecture design
and their impact on performance.
Course Objectives
 Introduce the basics of computer hardware and how software
interacts with computer hardware
 Describe how computers represent and manipulate data
 Discuss computer arithmetic and convert between different number
systems
 Discuss basics of Instruction Set Architecture (ISA) – MIPS
 Discuss a simple computer with hardware design including data
format, instruction format, instruction set, addressing modes, bus
structure, input/output, memory, Arithmetic/Logic unit, control unit,
and data, instruction and address flow
 Introduce Boolean algebra as related to designing computer logic,
through simple combinational and sequential logic circuit.
COURSE OUTLINE
WEEK 1: 2nd October – 7th October
 Course Introduction
 Introduction to Types of Computers
 Introduction to Computer Organization & Architecture
 Data Representations
WEEK 2: 9th October – 14th October

 Floating Point Numbers
 BCD & Expression Evaluations
 Logic Circuits
COURSE OUTLINE
WEEK 3: 16th October – 21st October

 Combinatorial Circuits
 Sequential Circuits
WEEK 4: 23rd October – 28th October

 Computer Structure
 CPU Registers
 CPU Examples
 Instruction Formats & Addressing Modes
 Machine Language Instructions
Recommended Text Books
1. Stallings, W. (2015) Computer Organization and Architecture - Designing for
Performance. (10th Ed) Pearson Higher Education
2. Andrew S. Tanenbaum and Todd Austin (2012). Structured Computer

Organization, 6th ed., Prentice Hall, ISBN-10: 0132916525.
3. Hamacher, C., Vranesic, Z. and Zaky, S. (2002) Computer Organization. McGraw-

Hill fith edition
4. John L. Hennessy and David A. Patterson. 2011. Computer Architecture, Fifth

Edition: A Quantitative Approach (5th ed.). Morgan Kaufmann Publishers Inc., San
Francisco, CA, USA.
Grading Policy
 Course Work (40%):
2 tests
o Test 1: 7th October 2023
o Test 2 14th October 2023
 Final Examination (60%)

Tentative Date:29th October 2023
o Section A (2 Compulsory Questions)
o Section B (2 out of four Questions)
HOUSE KEEPING RULES
 Our phones should ALWAYS be Off / Silent Mode
 Late Coming after 10 minutes not acceptable
 Laughing / Unnecessary noise not acceptable
 Maximum attention required

COMPUTER ORGANIZATION & ARCHITECTURE
DIT 1205, BCS 1102
Introduction
 The course is about the structure and functions

of modern day computers.
 Challenging task because:

• There are so many computer products.
• Computer technology is changing fast.
 The course will describe general principles of

computer architecture that apply to computers of
any category.
Introduction
What is a Computer?
 Many people define a computer according to the
functions it performs without considering the basic
principles that govern the organisation of the computer.
 A computer is an electronic device that manipulates

information, or data. It has the ability to store, retrieve,
and process data.
 Computers can perform complex and repetitive

procedures quickly, precisely and reliably.
 Modern computers are electronic and digital.

Introduction
 Hardware is any part of the computer that has a
physical structure, such as the keyboard or mouse.
It also includes all of the computer's internal parts,
like the wires, transistors, and circuits.
Introduction
 Software is any set of instructions and data that
tell the hardware what to do and how to do it.
 Examples of software include web browsers, games,

and word processors.
Introduction
Different types of computers
 Computers come in many shapes and sizes, and
they perform many different functions in our daily
lives e.g. desktops, laptops, servers, ATM machines,
Scanners in supermarkets, Calculators, etc.
Introduction
Different types of computers
 Desktop computers
 They are used at work, home, and schools, etc. They
are designed to be placed on a desk, and they're
typically made up of a few different parts, including
the computer case, monitor, keyboard, and
mouse
Introduction
Laptop computers
 They are battery-powered computers that are more
portable than desktops, allowing you to use them
almost anywhere.
Introduction
• Tablet computers—or tablets
• They are even more portable than laptops. Instead of
a keyboard and mouse, tablets use a touch-
sensitive screen for typing and navigation. The iPad
is an example of a tablet.
Introduction
• Servers
• A server is a computer that serves up information to
other computers on a network. For example,
whenever you use the Internet, you're looking at
something that's stored on a server. Many
businesses also use local file servers to store and
share files internally.
Introduction
PC’s
The original IBM PC that was introduced in 1981. It is
the most common type of personal computer, and it
typically includes the Microsoft Windows operating
system.
Introduction
Macs
The Macintosh computer was introduced in 1984, and
it was the first widely sold personal computer with a
graphical user interface. All Macs are made by one
company (Apple), and they almost always use the
Mac OS X operating system.
Introduction
Other types of computers
 Many of today's electronics are basically
specialized computers, though we don't always
think of them that way.
 Smartphones: Many cell phones can do a lot of

things computers can do, including browsing the
Internet and playing games. They are often called
smartphones.
 Wearables: A group of devices—including fitness

trackers and smartwatches—that are designed to
be worn throughout the day.
Introduction
• Game consoles: specialized computers that are
used for playing video games on TV.
• TVs: Many TVs now include applications—or apps

—that let you access various types of online content.
For example, you can stream video from the Internet
directly onto your TV.
THE COMPUTER EVOLUTION
The Mechanical Era (1600s – 1940s)
Wilhelm Schickard (1592)

He built the first automatic calculator in 1623 called the
Calculating Clock. It could add and subtract six-digit
numbers, and indicated an overflow by ringing a bell.
Blaise Pascal (1623 – 1662)

He was a French Mathematician, Physicist and Religious
Philosopher. He built the first calculating machine in 1642. It
used gears and was powered by a hand operated crank. His
machine could only do addition and subtraction. The
programming language Pascal was named in honour of
Baron Gottfried Wilhelm von Leibniz (1646 – 1716)
He improved on Pascal’s machine and he built another mechanical machine
that could multiply and divide as well.
Charles Babbage (1792 – 1871)

 He was a professor of mathematics at the University of Cambridge. He
designed and built a Difference Engine which was used to compute tables
of numbers that were used in navigation.
 In 1834 he designed and built the Analytical engine which had 4

components: the store (memory), the mill (processor), the input section
(punched card reader and the output section (punched and printed output).
It could read instructions from punched cards and carry them out.
 It was programmable in simple Assembler language. Charles hired Ada

Lovelace to do the programming (first computer programmer.) A modern
programming language Ada was named in her honour.
Herman Hollerith (1889).
 In 1881, he designed a machine to tabulate census data.
The U.S. Census Bureau had taken eight years to
complete the 1880 census, and it was feared that the
1890 census would take even longer.
 His machines were used for the 1890 census and the
data that would have been processed in ten years was
processed in only one year.
 In 1896, he founded the Tabulating Machine Company to

sell his invention, the Company became part of IBM in
1924.
Konrad Zuse (1930s)
He was a German engineering student who built a series of
automatic calculating machines using electromagnetic relays. His
machines were destroyed during the allied bombings in 1944.
John Atanasoff
He built a machine that used binary arithmetic and had
capacitors for memory which were periodically refreshed to keep
the charge from leaking (jogging memory). Modern dynamic RAM
chips work in the same way.
Howard Aiken
He improved on Babbage’s machine by building it on relays. His
machine was called the Havard Mark I.
Summary of the Mechanical Era
 The mechanical computers were designed to reduce
the time taken for calculating and to increase on the
accuracy of the results. They however had two draw
backs:
 Speed of operation was limited by the inertia of the

moving parts (gears and pulleys)
 They were cumbersome, unreliable and expensive.

The Electronic Era
Generation 1 ---Vacuum Tubes (1945 – 1958)
COLOSSUS
 It was built in 1945 by Alan Turing to decode
encrypted messages sent by the Germans’ ENIGMA
whose decoding involved a lot of computations.
 The COLOSSUS was designed to perform these

immediately needed calculations.
ENIAC (Electronic Numerical integrator and Computer)
It was designed by Mauchley and his graduate student J. Presper Eckert in
1943 to calculate range tables used for aiming heavy US artillery. It is
regarded as the first electronic computer. Some of its features were:
o 18,000 vacuum tubes and 1,500 relays.
o 70,000 resistors.
o 10,000 capacitors
o 6,000 switches
o Weighed 30 tones
o Consumed 140 kw of power.
o 30 x 50 ft
o Had 20 registers each capable of holding a 10 digit decimal number
(used a decimal number system).
o A multitude of sockets and jumper cables.
o Programmed by manually setting switches.
o It was completed in 1946 when the war was over.

 Mauchley and Eckert improved on the ENIAC and they
designed the EDVAC (Electronic Discrete variable
Automatic Computer).
 IAS Machine (Institute for Advanced Studies)

 It was built by John Von Neumann who had worked with
Mauchley and Eckert to build the ENIAC.
 He realized that a program could be represented in a digital

form in the computer’s memory along with the data.
 His basic design known now as the von Neumann machine

formed the basis of the first stored program computer.
 The von Neumann machine had five basic parts: memory, the
arithmetic–logic unit, the program control unit, the input and the output.
 Memory consisted of 4096 words (a word holding 40 bits). A word

contained either two instructions (20 bits each), or a 39 bit signed
integer. It had no floating point arithmetic.
 Data and instructions were stored in memory. Memory contents are

addressable by location regardless of the content itself.
The M.I.T. machine(The Whirwind I)
It was built around the same time like the ENIAC and
the IAS at M.I.T. It had a 16 bit word and was designed
for real time control.
The 701
Built by IBM in 1953. It had 2K of 36 bit words with two
instructions per word. The 704 followed in 1956 with
4K core of memory, 36 bit instructions and floating
point hardware.
Generation 2 ---Transistors (1955 – 1965)
The transistor was invented at Bell labs in 1948. The first
transistorized computer built at M.I.T. was a 16 bit machine. It
was called the TX-0 (Transistorized eXperimental Computer 0).
The PDP–1
It was manufactured by DEC in 1961. It had 4K of 18 bit words
and a cycle time of 5 microsec. It cost $120,000.
PDP-8
by DEC followed later. It was a 12 bit machine but cheaper,
$16,000. It had a single bus, the omnibus.
IBM built a transistorized 7090 which was twice as
faster as the PDP-1 but it cost millions of dollars. They
later built the 7094 which had a cycle time of 2 micro
sec and 32K of 36 bit words of core memory.
CDC built the 6600 in 1964 which was faster than the
7094. It was a highly parallel machine within the CPU
and could execute 10 instructions at once.
Summary
Transistors, High level languages, Floating Point
Arithmetic.
Generation 3 ---Integrated Circuits (1965 – 1980)
IC’s allowed dozens of transistors to be put on a single chip.
Smaller, faster and cheaper machines could now be built.
IBM built the System/360, that combined most of the

characteristics of its earlier machines. Different models of the
360 were built. It supported multiprogramming (having different
programs in memory at once.) Programs written for the earlier
models could be run on the 360. It had a huge address space of
224 bytes (16 MB).
The 360 series was followed by the 370 series, 4300 series and
the 3069 series.
DEC also introduced the PDP-11, a 16 bit successor to the

PDP-8.3
Summary
Integrated Circuits, Semi conductor memory,
microprogramming, multiprogramming.
Generation 4 ---Personal Computers and VLSI

(1980 – ??)
Millions of transistors could now be put on a single
chip implying smaller and faster computers. This
gave rise to the development of personal
computers which are widely used.
Topic 2
Introduction to Computer Organisation and
Architecture
COMPUTER ARCHITECURE
 The structure and behaviour of the various

functional modules of the computer and how they
interact to provide the processing needs of the
user.
 Architectural attributes include:

 Instruction set
 Number of bits used
 I/O mechanisms
 Addressing Techniques
 etc.
Computer Organisation
 The way the hardware components are
connected together to form a computer system.
 Organisational attributes include hardware details

visible to the user e.g. the interfaces, memory
technology.
N.B. A number of manufacturers offer many different

computer models (organizations) but all having the same
architecture and thus differing in costs.
WHY STUDY COMPUTER
ORGANIZATION AND ARCHITECTURE
 To understand the computer’s functional
components, their characteristics, their
performance and their interactions.
 Computer architecture helps to structure programs

that can run more efficiently on a real machine
(CPU speed, memory etc)
 To know the most cost effective computer for use

in an organization.
 Computer architecture concepts are needed in

other courses e.g. (programming, and operating
Systems)
Computer Functions
Computer Functions
 Input Data
 Output Data
 Process data
 Store data
 Move the data between the different computer

components and the external world
 To control all the above operations

COMPUTER STRUCTURE
Memory
The microprocessor (CPU)
 Decodes instructions and use them to control
the activities within the system
 It also performs the arithmetic( +,-, /, *) and

logical (>,>=,<,<=, =, =!) computations.
Memory
 Stores both data and instructions that are
currently being used.
I/O Subsystem:
Moves data between the computer and external
environment. It consists of devices for :
 Communicating with the external world (I/O
Devices)
 Storing large quantities of information (mass

storage devices or secondary memory)
System Interconnection
Mechanism to provide communication between the

CPU, memory and the I/O sub system. It consists
of the System Bus and the Interfaces
System Bus.
A set of conductors that connect the CPU to its
memory and I/O devices. The bus conductors are
normally separated into 3 groups:
 The Data Lines: for transmitting information
 Address Lines: Indicate where information is to
come from or where it is to be placed.
 Control Lines: To regulate the activities on the bus.
Interfaces
Circuitry needed to connect the bus to a device.
Memory interfaces
 Decode the address of the memory location being
accessed.
 Buffer data onto/off the bus.
 Contain circuitry to perform memory reads or write.
I/O interfaces
 Buffer data onto/off the system bus
 Receive commands from the CPU
 Transmit information from their devices to the CPU.
COMPUTER STRUCTURE
Two arrangements of these components can be
described:
 The Single bus / Single processor
architecture: one processing element and all
the other components are connected to a single
link (the System Bus)
Single Bus / Single Processor
Multiprocessing System
 The Multiprocessing System: has several

processing elements surrounded by different
subsystems and a central link (the system bus)
connecting the different subsystems together.
The links in the subsystems are called local buses.
Each subsystem operates as an independent

computer but can take advantage of the shared
resources.
Multi Processing System
The shared main memory can be used for passing
information between subsystems
The shared mass storage can be used to store large

programs and large quantities of data that are
needed by more than one subsystem.
 The competition for the shared resources by the

different elements is called contention.
Multi Processing System
Topic 3: DATA
REPRESENTATIONS
DATA REPRESENTATIONS
 A computer uses binary digits (0’s and 1’s) to store
data in different formats.
 These binary digits are called BITS.
 In Computer circuits, 0’s and 1’s are voltage levels:
• 0 is low voltage (OFF)
• 1 is high Voltage (ON)
DATA FORMATS
1. Numeric Formats
They store only numbers; There are three numeric
formats:
 Integer or Fixed point Formats.
 Floating Point Formats
 Binary Coded decimal (BCD)
2. Alphanumeric Codes:
Store both numbers and characters including the
alphabetic characters.
NUMERIC FORMATS
Integer Formats
Binary:
 To convert from decimal to binary we do successive
divisions
 To convert from binary to decimal we expand e.g.

11011
= (1 * 24) + (1 * 23) + (0 * 22) + (1 * 21)+ (1 * 20)
= 16 + 8 + 0 + 2 + 1 = 2710.
or use Horner’s Rule:

((((1 *2) + 1)2 +0)2+1)2+1 = 2710
NUMERIC FORMATS
HEXADECIMAL
 It has 15 digits 0 – 15
 Each Hexadecimal digit can be represented by a
unique combination of 4 binary bits; e.g.
= > 110011011 = 0001 1001 1011
1 9 B16
 To convert 1C2E16 to decimal you expand using
powers of 16.
= (1 * 163) + (12 * 162) + (2 * 161) + (14 * 160)
= 4096 + 3072 + 32 + 14 = 7214
 To convert 1579710 to hexadecimal we perform

NUMERIC FORMATS
OCTAL
• Each octal digit can be represented by a unique combination
of three bits.
e.g. 1100110112 = 110 011 0112 = 6338
• 1010110001102 = 101 011 000 110 = 53068

= 1010 1100 0110 = AC616
• 15738 = 001 101 111 0112

= 0011 0111 1011 = 37B16
• A74816 = 1010 0111 0100 10002 =

= 001 010 011 101 001 000 = 1235108
NUMERIC FORMATS
FRACTIONS
The binary equivalent of the integer portion is obtained
as usual but the fraction part is obtained by
successively multiplying by 2.
e.g. To convert 13.6875 to binary;

1310 = 11012 1 0 1 1
.6875 * 2 = 1.375
.375 * 2 = 0. 75
.75 * 2 = 1.5
.5 * 2 = 1.0
=> 13.6875 = 1101.1011

NUMERIC FORMATS
FRACTIONS
• If a binary number contains digits to the right of the
decimal point we convert them by starting at the
binary point and move to the right.
e.g. 11.10100110112 = 011 101 001 101 100 = 3.51548

= 0011 1010 0110 1100 = 3.A6C16
5.1458=101 001 100 101 = 0101 0011 0010 1000 = 5.32816

FRACTIONS
 Just like in Base 10 the decimal point can be moved by
multiplying by the appropriate power of the base.
e.g. 101.11 = 1011 * 2-2 = 0.1011 * 23
 Horner’s Rule can also be applied to numbers with

fractions
e.g. To convert 0.01012 to base ten using Horner’s rule:
= 0.5(0 + 0.5(1+0.5(0+0.5 * 1))) = 0.3125
REPRESENTATION OF NUMBERS IN
COMPUTERS
 The storage capacity of a computer’s memory and
control circuitry is finite
 If there are n bits in a group the number of possible

combinations of 0’s and 1’s is 2n.
 If the bits are used to represent non–negative

integers, integers 0 through 2n-1 can be
represented.
 With 8 bits integers 0 – 255 can be represented.

.
REPRESENTATION OF NUMBERS IN COMPUTERS
 Big numbers are estimated using powers of ten
210 = 1024 = 103
e.g. 236 = 26.230 = 26(210)3 = 26(103)3 = 64 * 109
Overflows
 If the result of any operation does not fit into the
number of bits reserved for it an overflow is said to
occur.
 All the 4 arithmetic operations can cause an overflow.

360 + 720 – 300 = 360 + (720 – 300) and
(360 + 720) – 300
SIGNED INTEGERS
 In the Sign Magnitude Format the MSB represents the
sign.
 A negative number is represented by a 1 and a positive

number by a 0.
 The range of integers that can be expressed in a group

of 8 bits is from – (27 – 1) to (27 – 1)
 In general a d bit binary sign magnitude representation

in which the first bit represents the sign has a range of
– (2d-1 – 1) to + (2d-1 – 1).
SIGNED INTEGERS
 To add two sign magnitude numbers, we
follow the usual addition rule
 If the sign differs we subtract the smaller

number from the larger number and give
the result the sign of the larger number.
 If the signs are the same we add them and

we give the result the same sign.
SIGNED INTEGERS
+5 + -7 = 10000111
- 00000101
10000010 (-2)
-5 + -7 = 10000101
- 10000111
10001100 (-12)
COMPLEMENTS
 The 4 digit 10’s complement of X is defined as
104 – X
e.g. If X = 0572, the 4 digit 10’s complement of X

is 10000 – 0572 = 9428
Consider the addition 0557 + - 328 = 229

The 4 digit 10’s complement of 328 = 104 – 328
= 9672
Add 0557
+ 9672
This one is lost 1 0229 Only 4 of the significant digits are saved.

COMPLEMENTS
 0557 + - 725 => 104 – 725 = 9275 => 0557
+9275 = 9832
 A 9 in the most significant Digit indicates that the

sum is negative. If the magnitude is wanted the 10’s
complement of the sum is taken.
i.e. 104 – 9832 = 0162
 N.B. The most significant digit is reserved to

represent the sign leaving 3 digits for the
magnitude.
2’s Complement
• The d digit 2’s complement of a d bit binary integer N
is equal to
2d – N where the subtraction is done in binary.
• The eight bit 2’s complement of an 8 bit binary

number 00000101 is 100000000 – 00000101 =
11111011
• The 2’s complement may also be computed by applying the

following rules.
Invert the bit values; the result is called one’s
complement then add 1
e.g. for N = 00000101 Invert 11111010 + 1 =
11111011
2’s Complement
1710 = 00010001 Invert the bits and add 1

11101110 + 1 = 11101111 = -17
11910= 01110111 Invert the bits and add 1;

10001000 + 1 =10001001 = -119
• N.B. Note the difference between the sign magnitude

representation and the 2’s complement
representation.
Rules to convert to decimal
 If a number is positive (beginning with a 0), convert
it to base 10 directly as usual.
 If it is negative (begins with 1) get its 2’s

complement and convert it to base 10.
 e.g. to convert a 2’s complement number 11111001

to decimal:
 Get its complement ; i.e. 11111001 Invert 00000110 + 1 =

00000111 = - 7
Addition of 2’s Complement Binary Integers
The left most bits are not treated separately as in
signed magnitude numbers.
7 00000111 (b) -7 11111001
+5 00000101 +5 00000101
12 00001100 -2 11111110
(c) -7 11111001 (d) 7 00000111

+- 5 11111011 + -5 11111011
-12 1 11110100 2 1 00000010
The carry is discarded

Overflow in 2’s complement
An overflow in 2’s complement occurs when:
The sign of the result differs from the sign of the
common numbers being added OR
There is a carry into but not out of the MSB OR
There is a carry out of but not into the MSB.
e.g. 126 01111110 -126 10000010

+ 5 00000101 + - 5 11111011
131 10000011 -131 01111101
FLOATING POINT FORMATS
 It stores numbers given in scientific notation. It is often

used to handle very large and very small numbers.
 It is written in the form: Fraction * baseexponent

e.g. 0.000000357 = 0.357 * 10-6 ,
625000000 = 0.625 * 109
 The fraction part is called the significand and the exponent

the characteristic.
Floating Point Numbers
A floating point format is designated by:
 The base
 The number of bits reserved for the exponent
 The number of bits reserved for the fraction
 The method for storing the sign and magnitude of the exponent
 The method for storing the sign and magnitude of the fraction.
 The order in which the two signs and the two magnitudes are to occur.
• The combination of the above factors for a given computer
depends upon the designer.
A Typical Floating Point Format
Sign of Magnitude of exponent Sign of Magnitude of fraction
Exponent Fraction
1 bit N bits 1 bit M bits
 The base chosen never appears in the format

once chosen it is fixed.
 The total number of bits in the FPF is N+M+2
where N = bits are reserved for the exponent and
M = bits reserved for the fraction.
 If base 2 is assumed the largest number that can be
stored using a floating point format is
N
approximately 22 - 1 where N = number of bits
reserved for the exponent.
 If N = 7 the largest number is approximately

2127 = 27(210)12 = 128 * 1036 = 1038 and the smallest is
2-126 = 10-38
 An exponent overflow is said to occur if an
operation results in a number that is so large that
the maximum size of the exponent is exceeded.
 If the exponent is negative and the magnitude

becomes too large, then an exponent underflow
occurs.
Floating Point Numbers
 If N + 1 bits are reserved for the exponent and the sign, the offset or
bias chosen = 2N and the format is called the excess 2N format
 If N = 7 the offset = 27 = 128 = 100000002 and the format is called the

excess 128 format.
 The real exponent is obtained from the quantity by subtracting the

offset.
 In excess 128 format, the number 01111110 = 126 implies that the
exponent = -2.
 In Excess 2N format a 1 in the MSB represents a positive exponent

and a 0 in the MSB represents a negative exponent.
The Typical 32 bit floating Point Format
Base 2 exponent in excess of 128 Sign of Magnitude of fraction
fraction
8 bits 1 bit 23 bits
Example 1
–13.6875 = - 1101.10112 = - 0.11011011 * 24
Exponent in excess 128 = 128 + 4 = 132 = 100001002
Sign of the fraction is negative => 1
Exponent sign fraction

10000100 1 1101101100000000
= 84ED8000
The Typical 32 bit floating Point Format
Example 2
To convert the typical Floating point number 7E5C0000
to base 10
Exponent = 7E = 01111110 = 126

126 – 128 = -2
5C = 0 .101 1110
Sign of magnitude of
fraction fraction
0.101111 * 2-2 = 0.00101112 = 0.179687510
Steps in Arithmetic
• Pre-normalisation if the operands are not normalized.

• Alignment
• Post normalization of the result
Examples
(1) 826013AC Alignment 826013AC
+8040AB04 82102AC1
82703E6D
(2) 83600000 No Alignment

+83C00000
83200000 normalisation 82400000
(3) 82600000 No Alignment

x 85D00000
87BC0000 normalisation 86F80000
The IEEE/INTEL Floating Point Format
It has 2 forms; the single precision and the double precision format
where N = 127 and 1023 respectively.
Sign of Base 2 exponent magnitude of fraction
fraction in excess of 127
- 1 bit-> --------8 bits--------------------------------23 bits---------------------------
Sign of Base 2 exponent magnitude of fraction

fraction in excess of 1023
- 1 bit-> --------11 bits--------------------------------52 bits---------------------------

IEEE Floating point Format
Examples
–5.375 = -101.011 = -1.01011 * 22
Exponent = 2 + 127 = 129 = 10000001
1 10000001 01011 ….. = C0AC0000
• Conversely 3E600000 = 0011 1110 0110 0000 00000

• Sign of fraction = 0 => +
• Exponent = 01111100 = 124 – 127 = -3 , i.e 2-3
Fraction = 0.110000000….
Significant = 1.11 * 2-3 = 0.001112 = 0.2187510
EXAMPLES
(1) 40700000 (2) 40C00000 No Alignment
+ C0580000 + C0800000
40180000 3EC00000 40C00000 40000000
(3) 41380000 (4) C0A80000

*3F400000 / 40E00000
410A0000 BF400000
BINARY CODED DECIMAL (BCD)
• Each figure in base 10 is represented by its 4 bit binary equivalent
e.g.
8159 = 1000 0001 0101 1001
• There are two BCD formats.

 Packed (Condensed) BCD: In this format each figure occupies
half a byte
e.g. 341 = 0011 0100 0001
 Extended (unpacked) BCD: Each decimal figure is represented

by a byte. In this case the first 4 bits of a byte can be filled with
zeros or ones depending on the manufacturer, e.g.
341 = 00000011 00000100 00000001
BCD
• Hardware designed for BCD is more complex than that for binary
formats. E.g. 16 bits are used to write 8159 in BCD while only 13
bits (1111111011111) would be required in binary.
• The advantage of BCD format is that it is closer to the

alphanumeric codes used for I/Os.
• Numbers in text data formats must be converted from text form to

binary form. Conversion is usually done by converting text input
data to BCD, converting BCD to binary, do calculations then
convert the result to BCD, then BCD to text output.
BCD
To convert a BCD number to binary, multiply consecutively

by 10 = 10102
e.g. 82510 = 1000 0010 0101
((1000 * 1010) + 0010)1010 +0101 = 1100111001.
The reverse conversion is done by successive divisions by

10 (10102) then using the 4 bit remainder as the BCD digit:
e.g. 1100111001/1010 = 1010010 rem 0101;
1010010/1010 = 1000 rem 0010
1000 0010 0101
BCD
The signs often used are 1100 for positive and 1101 for negative.
e.g. –34 = 0011 0100 1101; +159 = 0001 0101 1001 1100
BCD addition can be done by successively adding the binary

representation of the digits and adjusting the results.
The adjustment rule is: If the sum of 2 digits is > 9, add 6 to the sum.
1748 0001 0111 0100 1000
+ 2925 0010 1001 0010 0101
4673 0100 0000 0111 1101
0110 0110
0100 0110 0111 0011
ALPHANUMERIC CODES
• It is the assignment of bit combinations to the letters

of the alphabet, decimal digits 0 – 9, punctuation
marks and several special characters.
• The two most prominent Alphanumeric Codes are:
 EBCDIC (Extended Binary Coded Decimal
Interchange Code); this is mostly used by IBM.
 ASCII: (American Standard Code for Information
Interchange); used by other manufacturers.
ALPHANUMERIC CODES
 ASCII represents each character with a 7 bit string

The total number of characters that can be represented is 27 =
128
e.g. J o h n = 4A 6F 68 6E
= 1001010 110111 1101000 1101110
 Since most computers manipulate an 8 bit quantity, the

extra bit when 7 bit ASCII is used depends on the
designer. It can be set to a particular value or ignored.
EXPRESSION EVALUATION
• Infix notation: uses parentheses and the operators are placed between their operands.
• The postfix or reverse Polish Notation places operators after the operands.
e.g.
INFIX POSTFIX
A/(B + C) ABC+/
(A + B) * [C * (D + E) + F] AB+CDE+*F+*
a + b * c(d + e) abc * de + *+ fgh + * /
f * (g + h)
Evaluation of Postfix Expressions to Infix uses a Stack (LIFO) structure

e.g. AB*CDE/-+ = (A * B) + (C – D/E)
LOGIC CIRCUITS
LOGIC CIRCUITS
 Inputs and outputs to digital computers are in one of the

2 possible states / Voltage levels which are represented
by 0’s or 1’s
 If the higher voltage is associated with 1, the circuit is
said to be based upon positive logic.
 If the lower voltage is associated with a 1, the circuit is
said to be based on negative logic.
LOGIC CIRCUITS
 Any variable that can take on two states e.g. (0, 1, True,
false; on/off) is called a logical variable.
 A circuit whose inputs and outputs are described by
logical variables is called a logical network.
INPUTS OUTPUTS
Logical Variables Logical Variables
Logical Networks
There are two types of logical networks:
 Combinatorial networks: Their outputs depend on
the current inputs.
 Sequential Networks: Their outputs depend on both

the current state of the network as well as the inputs
Logic Gates
 A combinatorial circuit with only one output is

called a logic gate. They accept logical values at
their inputs and they produce corresponding
logical values at their outputs.
 A table listing all the outputs for the various

inputs is called a truth table (derived from the
True/ False logic in mathematics.)
 All combinatorial circuits can be constructed from

the 7 most common logic gates.
Logic Gates
1. The inverter(NOT) Gate:
When the input is 1 the output is 0 and vice versa.
IIiI Output
A A
A A
0 1
2. The AND Gate: 1 0
Input Output
A
AB A B AB
0 0 0
B
0 1 0
1 0 0
1 1 1
The output is 1 if all the inputs are 1’s

Logic Gates
3. The OR Gate:
A B A+B
A
0 0 0
A+B
0 1 1
B 1 0 1
1 1 1
• The output is 0 if all the inputs are 0’s.
• If an inverter is combined with another logic gate, the presence of

the inverter is indicated by placing a small circle at the affected
input or output.
Logic Gates
4. The NAND (NOT AND) Gate
A A B AB
AB 0 0 1
B 0 1 1
1 0 1
The output is 0 if all the inputs are 1’s.
1 1 0
5. The NOR (NOT OR) Gate
A B A+B
A A+B
0 0 1
B
0 1 0
The output is 1 if all the inputs are 0’s. 1 0 0
1 1 0
LOGIC GATES
6. The EXCLUSIVE OR Gate
A B A+B
A A+B 0 0 0
B 0 1 1
1 0 1
The output is 0 if all the inputs are the same 1 1 0
A B A+B
7. The EXCLUSIVE NOR Gate
0 0 1
0 1 0
A A+B
1 0 0
B 1 1 1
Complex Logic gates
 Logic circuits can be built by combining several of the elementary
logic gates.
 A graphical illustration of a logic circuit is called a logical diagram
A
C
AC + BC
B
A
B (A + B)C
C
• The best way to prove equivalence is to use the truth tables
EXAMPLE
To prove that AC + BC = (A + B)C
A B C B AC BC AC + BC A+B (A + B)C
0 0 0 1 0 0 0 1 0
0 0 1 1 0 1 1 1 1
0 1 0 0 0 0 0 0 0
0 1 1 0 0 0 0 0 0
1 0 0 1 0 0 0 1 0
1 0 1 1 1 1 1 1 1
1 1 0 0 0 0 0 1 0
1 1 1 0 1 0 1 1 1
EXAMPLE
X = AB + ACD + ACEF + ACEG

A A B C D E F G
B
C
D
E
F
G
Causes maximum delay

BOOLEAN ALGEBRA
It is a mathematical structure that consists of a set containing only a 0 and 1, the
unary operator (complementation) and the binary operation of addition and
multiplication. Subtraction and Division are not defined in Boolean algebra
A = A A(B + C) = AB + AC
AA = A (B + C)A = BA + CA
A+A =A A+B =A B
A.0 =0 AB = A+B
A+0 =A AB + AB =A
A.1 =A A + AB =A
A+1 =1 (A + B)B = AB
A.A =0 (A + B) (A + B) = A
A+A =1 (A + B) (A + C) = A + BC
AB = BA A(A + B) = A
A +B =B+A AB + B =A + B
(AB)C = A(BC) AB + AB = A + B
A + (B + C) = (A + B) + C AB(A + B) = A + B
Example
ABC + BC + AB
ABC + ABC + ABC + ABC
= C(AB + B) + AB ABC+ ABC + ABC + ABC + ABC

+ABC
= C(A + B) + AB
(A + A)BC + (B + B)AC + (C + C)AB
= AC + BC + AB
BC + AC + AB
= AC + (A + A)BC + AB
= AC + ABC + ABC + AB
= AC(1 + B) + AB(C + 1)
= AC + AB
Digital Design Process
Determine all the input/output relationships that must be true for
the network being designed and put them in convenient tabular
form.
Use the drawn up table to find Boolean expressions for each
output.
Simplify the expressions from 2 above
Use the expressions resulting from step 3 to develop the desired
logical diagram.
Three design tools

• Truth Table (To define a logical network)
• Boolean Expression (for minimization)
• Logic diagram (For the actual design)
Example
Design a three input network that will output a 1 if the majority of
the inputs are 1’s otherwise the output is zero
Step 1 (Draw a truth Table)
A B C X
0 0 0 0 X0
0 0 1 0 X1
0 1 0 0 X2
0 1 1 1 X3
1 0 0 0 X4
1 0 1 1 X5
1 1 0 1 X6
1 1 1 1 X7
Boolean expression
Step 2 (Find the Boolean expression.)
There are two types of Boolean Expressions
1. SUM OF PRODUCTS (SOP’s)

A product is 1 if and only if all of its factors are 1
A sum is 1 if at least one of its terms is a 1.
X3 = ABC;X5 = ABC; X6 = ABC; X7 = ABC

X = X3 + X 5 + X 6 + X 7
X = ABC + ABC + ABC + ABC

Boolean expression
2. PRODUCT OF SUMS (POS)
A product is 0 if at least one of its factors is 0
A sum is 0 if all its terms are 0’s.
X0 = A + B + C; X1 = A + B + C; X2 = A + B + C; X4 = A + B + C
X = X0X1X2X4 = ( A + B +C)(A + B + C) (A + B + C) (A + B + C)
Step 3 Simplify the expression

_ _ _
ABC + ABC + ABC + ABC = BC + AC + AB
• Step 4: Draw the logic diagram
A B C
BC BC
AC BC+AC+AB BC+AC+AB
AC
AB
MAXITERMS & MINITERMS
• The occurrence of a variable or its complement in an expression is called a literal.
• A term in the SUM OF PRODUCTS that includes a literal for every input is called a
miniterm.
• A term in the PRODUCT OF SUMS that includes a literal for every input is called a
maxiterm.
_ _ _ _ _ _
• e.g. in ABC + ABC + AC; ABC and ABC are miniterms, AC is not a miniterm.
_ _ _ _ _ _ _ _ _
• Similarly in (A +B+C)(A+B+C)(A+C), (A +B+C) and (A+B+C) are
_
• maxiterms, (A+C) is not.
KARNAUGH MAPS
• A Karnaugh map is a truth table for a single output
consisting of arrays of squares where each square
corresponds to a row of a truth table.
• The symbols at the top represent the variables
associated with the columns and the symbols on the left
represent the variables associated with the rows.
• The value of each output for each input is put in the
corresponding square.
• For each 1 in the Karnaugh map there is a
corresponding miniterm in the output’s Sum of product
expression and each 0 represents a maxiterm in the
Product of Sums expression.
EXAMPLES
Two inputs Three Inputs
A AB
0 1 00 01 11 10
B 0 0 2 C
0 0 2 6 4
1 1 3
1 1 3 7 5
Four Inputs
AB
00 01 11 10
00 0 4 12 8
CD
01 1 5 13 9
11 3 7 15 11
10 2 6 14 10
EXAMPLE 1
A B C X Using Boolean Algebra
0 0 0 0
X = ABC + ABC + ABC
0 0 1 0
= ABC + ABC + ABC + ABC
0 1 0 0
= BC + AB
0 1 1 1
Look for adjacent groups that
1 0 0 0
include 2n miniterms where n is
1 0 1 0 an integer. The larger the group
1 1 0 1 the greater is the reduction. A
1 1 1 1 B
AB B
00 01 11 10 C
C 0 0 0 1 0
EXAMPLE2
A B C X
Using Boolean simplification:
0 0 0 0
ABC + ABC + ABC + ABC
0 0 1 0
ABC + ABC + ABC + ABC ABC + ABC
0 1 0 0
= BC + AC + AB
0 1 1 1
AB
1 0 0 0
00 01 11 10
1 0 1 1
C 0 0 0 1 0
A
1 1 0 1 B
1 0 1 1 1 AC
1 1 1 1 B
C
A function may be used to state where the
output is 1 instead of drawing a Karnaugh
EXAMPLE 3
F(A,B,C) = (0,1,2,3,7)
AB
00 01 11 10
0 1 1
A
C
1 1 1 1
B
C
More Examples
AB
00 01 11 10
0 1 1 1 A
C C
1 1 1
B
AB
00 01 11 10
C 0 1 1 B
1 1
C
AB
More Examples
AB
AB
00 01 11 10
00 01 11 10 BD
AB 00 1 1
00 1 1 1
01 1
01 1 1
CD 11 1 1
CD11 1
10 1 1
10 1
ABC ACD AB BC
THE DON’T CARE CASES
• For some designs some input combinations cannot occur. Their
outputs are represented by X’s in the Karnaugh Map and they may
or may not be included in the prime implicants.
• They are called Don’t Care Cases denoted by the function d(A,B,C) =
(….)
AB
00 01 11 10
00 X
CD 01 1
11 1 AB
10 X 1 1
ACD
In the example above it is important to include the miniterm ABCD in

but not ABCD
COMBINATORIAL
CIRCUITS
HALF ADDER
It is a circuit for adding 2, 1 bit quantities
C = AB
A B S = AB + AB = A + B
A
+ B A B
Carry Sum
C H
A
A B S
S C
0 0 0 0
0 1 1 0
C S
1 0 1 0
1 1 0 1
Full Adder
It is an adder that includes a carry input
from a lower
A
order
B
sum. A B Ci S CO
0 0 0 0 0
0 0 1 1 0
FA Ci 0 1 0 1 0
Co 0 1 1 0 1
S 1 0 0 1 0
CO = ABC + ABC + ABC + ABC 1 0 1 0 1
= C(AB + AB) + AB(C + C) 1 1 0 0 1

2 1 1 1 1
= C(A + B) + AB
S = ABC + ABC + ABC + ABC

= A(B + C) + A(B + C)
= A(BC + BC) + A(BC + BC)
= A+ B+ C
FULL ADDER
A B
CI
CO S
Ripple Carry Adder
It is a circuit built up of may full adders consisting of the
required number of bits. The carry out bit is used as a
carry in into its left neighbour. The carry into the right
most bit is set to 0.
A Multiplexer (Data Selector)
• It is a logical network capable of selecting a single set of
data inputs from a number of sets of inputs and it passes
the selected inputs to the outputs.
• A multiplexer has 2 kinds of inputs, the control inputs and
the data inputs.
• The control inputs are used to select which of the inputs in
the data is to be passed through to the outputs.
A0 An
Control MUX(n)
Output
2-1 Multiplexer
It has 2 data inputs A and B, one control input , P, and one output, X.
When the control input P = 0 the output X is A and when P = 1 X = B
P A B X
X = PAB + PAB + PAB + PAB
0 0 0 0 = PA(B + B) + PB(A + A)
0 0 1 0 = PA + PB
0 1 0 1 A B
0 1 1 1
P
1 0 0 0
1 0 1 1
1 1 0 0
1 1 1 1
X
4-1 Multiplexer
It selects only one of the 4 inputs. It has 2 control lines to choose one of
the 4 possible inputs.
A B C D
P
X
In general for an n to 1 multiplexer, the inequality 2K >= n must be satisfied
A Demultiplexer
It has 1 set of data inputs and two or more sets of outputs and a set of
control inputs whose purpose is to select the set of outputs to transmit.
The other outputs are 0.
Inputs
Control DMUX(n)
Outputs
A 1- 2 Demultiplexer
It has 1 data input (A) , two outputs( X, Y)
and one control input (P) .
A
X= PA; Y= PA
P DMUX(n) A
P
X Y
P A X Y
0 0 0 0
0 1 1 0
X Y
1 0 0 0
1 1 0 1
Comparators
A comparator compares two sets of inputs and outputs a 1 if

the comparison is satisfied.
The comparisons are =,!=, >, >=, <, <=
Inputs
A B
output
The equality comparator
• The design is based upon the XNOR gate which outputs

a 1 if its inputs are the same and a 0 if they are not
equal.
B2B1B0 = A2A1A0
A2 B2 A 1 B1 A 0 B0
1 bit > comparator
The output is 1 if A > B
X = AB
A B X
0 0 0 A B
0 1 0
1 0 1
1 1 0
X
Decoder
Circuit whose outputs are miniterms of the inputs. Exactly only one
output is a 1 at any given time.
If n is the number of inputs and m the number of outputs then 2n >=
m
e.g. if the binary number on the input lines is k then output line k will
be 1 and all the others will be 0’s.
A1 A 2 A3 X0 X1 X2 X3 X4 X5 X6 X7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1
Decoder
A3
A2
A1
X0 X1 X2 X3 X4 X5 X6 X7
The Encoder
The opposite of a decoder. Only one input can be a 1 (activated) at a

time. Its number in binary is presented as the output.
It has 2n inputs and n outputs.
A0 A1 A2 A3 X1 X2
1 0 0 0 0 0
0 1 0 0 0 1
0 0 1 0 1 0
0 0 0 1 1 1
Inputs Outputs
A1 A2 A3 A4 A5 X1 X2 X3
1 0 0 0 0 0 0 1
0 1 0 0 0 0 1 0
0 0 1 0 0 0 1 1
0 0 0 1 0 1 0 0
0 0 0 0 1 1 0 1
X3 = A1 + A3 + A5 X2 = A2 + A3 X1 = A4 + A5
Encoder
X3 = A1 + A3 + A5 X2 = A2 + A3 X1 = A4 + A5
A1
A2
A3
A4
A5
Code Converters
They are electronic circuits whose purpose is to convert data from one format to another.
Data in a computer system may take on several different forms as it changes from one format to
another.
e.g. the decimal input from a keyboard calculator must be converted into BCD using an encoder.
The CPU’s output is in BCD and the decoder translates the BCD to a special 7 segment display code by a
decoder.
7 8 9
4 5 6 Encoder CPU Decoder
1 2 3
0 Decimal
Display
The encoder circuit
The encoder has 10 active inputs and 4 outputs connected to input lamps.
e.g. The input 7 causes a BCD output of 0111.
9 23 22 21 20
9
8 8 A
7 7 DECIMAL
6 6 TO
5 BCD ENCODER B
5 4
4 3 C
3 2
2 1 D
1 0
0
The Decoder circuit
0 A a a
b b
1 B c c
Decoder d d
1 C e e Display
f f
1 D g g
The Display
a
f b
e c
d
A B C D a b c d e f g
0 0 0 0 1 1 1 1 1 1 0
0 0 0 1 0 1 1 0 0 0 0
0 0 1 0 1 1 0 1 1 0 1
0 0 1 1 1 1 1 1 0 0 1
0 1 0 0 0 1 1 0 0 1 1
0 1 0 1 1 0 1 1 0 1 1
0 1 1 0 0 0 1 1 1 1 1
0 1 1 1 1 1 1 0 0 0 0
1 0 0 0 1 1 1 1 1 1 1
ROMS AND PLA’S
ROM (Read Only Memory)
• Its circuit is equivalent to a decoder. It outputs all possible
miniterms of the inputs followed by an encoder.
• The output combinations are permanently embedded in its
circuitry and the inputs serve to select one of these
combinations. Each output is obtained by disconnecting the OR
inputs from the AND gates whose miniterms are not to be
included in the output.
• Because a ROM must produce all the possible miniterms its
decoder portion is fixed by n (the number of inputs). The
encoder portion depends on both the outputs and the way in
which all the outputs of a decoder are used to generate the
final ROM outputs.
ROMS
A1 X1
DECODER 2n miniterms ENCODER
An Xn
Once the disconnections are made they cannot be changed. (ROM

nature)
EXAMPLE
Construct a 2 input ( A,B) and 3 output (X,Y,Z) ROM such that:
X = AB + AB; Y = AB + AB; Z = AB + AB
ROM EXAMPLE
A These
connections
are always
B made
AB AB AB AB
These are
selectively
made
X Y Z
PLA (Programmed Logic Array)
• Similar to a ROM but does not output miniterms that
will not be needed in any of the outputs. i.e. the
decoder does not necessarily produce all the
miniterms. For an n input network, we have <= 2n
AND gates
A1 X1
DECODER < 2n miniterms ENCODER
An Xn
EXAMPLE
Implementation of the above ROM as a PLA
PLA example
A
B
Both sets of
connections are
AB AB AB made selectively
X Y Z
PARITY GENERATION AND DETECTION
• Errors usually occur when transmitting or storing data due

to electromagnetic noise or physical damage to the storage
medium.
• One method of error protection is by adding an extra bit
called a parity bit to the data bits and it is set according to
one of the following rules:
• An Even Parity bit is set if an odd number of 1’s occurs in
the data bits; otherwise it is cleared. Therefore, the total
number of 1’s is even.
• An Odd Parity bit is set if an even number of 1’s occurs in
the data bits; otherwise it is cleared. Therefore, the total
number of 1’s is odd.
 During transfer of information from one location to
another, the message (the data bits) is applied to
the parity generator where the required parity bit is
generated.
 The message together with the parity bit is

transmitted to its destination.
 At the destination all the incoming bits are applied
to a parity checker to check the proper parity which
was adopted.
 An error is detected if the checked parity does not

conform to the adopted parity.
 The parity method detects the presence of 1, 3 or

any odd number of errors. An even number of errors
is not detected.
Example (Even Parity)
Parity Generation
Parity bit
Data Bits
Error Detection
1 if there is an error
0 if no error
Parity Bit
Data Bits
Sequential Networks
SEQUENTIAL LOGIC & COMPUTER CIRCUITS
 Combinatorial circuits cannot be used for storage because:

 They have no memory
 They do not contain feedbacks
 They are time independent.
 Their outputs solely depend on their inputs.
 They have no intrinsic timing control.
Sequential circuits have internal states that can be used to

store information and modify their inputs.
• Examples
 A simple counting device; its output depends on the input
signal that causes the output to increment and also on the
current count that was previously determined.
 A memory circuit; the input causes the contents of memory

to be applied to the outputs.
 Time in a sequential circuit takes on a significant role.
 A sequential network is defined according to its inputs

and outputs over a period of time.
 The aid used in examining the time dependent aspect

of a sequential network is called a timing diagram
A Timing Diagram
A
Increasing time
A begins in state 0, B and X begin in state 1.

Transition of A to 1 does not change X.
Transition of B from 1 to 0 causes X to change to 0.
Transition of A from 1 to 0 does not affect X but the following
transition of A causes X to change to 1.
Timing Diagrams
• Sequential networks are synchronized by a time
standard called a clock. A clock generates an evenly
spaced train of pulses.
• Time between consecutive pulses is called a period.

The number of periods per second is called a
frequency.
period
• Elementary sequential circuits fall into a class of binary

electronic circuits known as multvibrators which may
be astable, monostable or bistable
Multivibrators
Astable multivibrators
They cannot maintain a fixed state but they keep on
switching back and forth between their states.
Monostable multivibrators
They can take on two states but are stable in only one
of them. They can only temporarily stay in the unstable
state.
Bistable
They are stable in either of the 2 states and can
therefore maintain either state indefinetely.
FLIP FLOPS
 They are bistable devices that are used in sequential networks.
 The most common flip-flops are the R-S, J-K, T, and the D flip flop.
THE R-S FLIP FLOP
S Q
Q
R
S R Q+ Q+ Q
0 0 Q- Q- S
0 1 0 1 C FF Q
1 0 1 0 R
THE R-S FLIP -FLOP
 It has 3 inputs S(Set), R (Reset) and C (a clock input)
which synchronizes the action of the flip-flop with its
surrounding
 The two outputs (Q and Q) are always in opposite states

from each other.
 Most significant changes occur when there is a clock

transition.
 If the clock input is constant, the outputs will follow the

changes in the inputs at all times.
THE R-S FLIP -FLOP
 When the clock is in 0 state Both R and S inputs have no
effect on the state of the flip-flop. The network is then
stable.
 In this state, if Q = 1, Q is = 0 and Q is maintained at 1. If

Q is 1 Q = 0 and Q is maintained at 1.
 If the clock is raised to 1 the network will not change if R

=S=0
 The subscripts Q- and Q- indicate outputs just before the

clock becomes 1 and the subscripts Q+ and Q+ show
outputs just after the clock becomes 1
Flip Flops
 All clocked flip flops that react to their inputs anytime C =
1 are called latches.
 The R-S flip-flop is called a latch because it uses the clock

inputs to determine whether or not the inputs will be
recognised.
 If a flip-flop changes only at the very beginning (or the

very end) of a clock pulse it is called an edge triggered
flipflop. They change state only when there is a 0 to 1
transition at C (+ve edge triggered) or a 1 to 0 transition
at C (-ve edge triggered)
Flip Flops
 A change from 0 to 1 is a +ve transition and the +ve
transition of a clock pulse is called the leading edge.
 A change from 1 to 0 is a negative transition and the

negative transition of a clock is called a trailing edge.
Example
Q
Q
Q +ve edge triggered

The J-K Filp Flop
 It is an R-S flip flop that has been modified by feeding
the outputs back and ANDYING them with the inputs.
 It has the same behaviour like the R-S flip flop except
that the C = J = K = 1 combination is meaningful and the
results in the output states is reversed.
 The J-K flip –flop is constructed from an edge triggered

R-S flip-flop otherwise the C=J=K=1 state would be
unstable.
J-K Flip Flop
J S Q
C
C R Q
K
J Q
C FF
K Q
J K Q+ Q+
0 0 Q- Q-
0 1 0 1
1 0 1 0
1 1 Q- Q-
T Flip-Flop
S FF Q T FF Q
C C Q
R Q
T Q+ Q+
0 Q- Q-
1 Q- Q-
• It has only one input.
• Its output states are reversed each time the input is pulsed.
• It is used in the design of counters.
• A T flip flop can be obtained from a J-K flip flop by permanently
applying 1’s to the J and K inputs. The R-S flip flop must be edge
triggered.
D FLIP FLOP
D
D S FF FF
Q C
C C
Q D Q+ Q+
R 0 0 1
1 1 0
 It has 2 inputs, a clock input and an input labelled D such that the Q
output is equal to the D input whenever the clock input is set to 1;
otherwise it is not affected by the D input.
 It is used in constructing registers . It is easily constructed from the R-S

flip flop by letting the D input be S input and connecting R to D
through an inverter.
EXAMPLE
Q
Latch
Q
Positive edge triggered
Q
Negative edge triggered
Clear and Preset Inputs
• Flip flops can clear or set the Q output irrespective of the state of
the other inputs. The clear input clears Q and the Preset input sets
Q
D J Preset
FF
C
C
K
clear clear
REGISTERS
• A number of flipflops placed in parallel to form several bits of

storage. Each flip flop is capable of storing 1 bit of information.
Registers are used anywhere in the computer where it is necessary
to store a number of bits.
e.g. a 4 bit register constructed from four D flipflops

D3 D2 D1 D0
D Q D Q D Q D Q
C Q C Q C Q C Q
Load
Read
Registers
The common clock load permits new information to be
loaded.
The common Read line and associated AND gates

provide a controlled Read out mechanism.
If n flip flops are used, the register is said to have a

length of width n.
Registers
The currently stored data are the current states of the flip
flops and can be monitored at the Q outputs.
Transfer of new information into the register is known as

loading the register.
If all bits of the register are loaded simultaneously with a

common clock pulse transition we say that the loading is
done in parallel.
Shift registers
They are capable of shifting their bits either to the left or
to the right. They have a tendency of rearranging their
contents.
If an 8 bit register contains 0 1 1 0 0 1 0 1 and a

left shift operation is performed, the new contents of the
register will be
1 1 0 0 1 0 1 0.
A 1 bit right shift would result into

0 0 1 1 0 0 1 0
Shift registers
If the left most bit is brought around and
put in the right bit during a left shift, or the
right most bit is put in the left bit during a
right shift the operation is called a rotation.
Shifting and Rotation
RLC (Rotate Left)
0 0 0 0 0 1 1 1
The content of the accumulator is rotated left one position. The

low order bit and the carry flag are both set to the value shifted
out of the high order bit position.
RRC (Rotate Right)
0 0 0 0 1 1 1 1
The content of the accumulator is rotated right one position.
The high order bit and the carry flag are both set to the value
shifted out of the low order bit position.
Shifting and Rotation
RAL (Rotate Left through carry)
0 0 0 1 0 1 1 1
The content of the accumulator is rotated left one position
through the carry flag. The low order bit is set equal to the
carry flag and the carry flag is set to the value shifted out of the
high order bit position.
RAR (Rotate Right through carry)

0 0 0 1 1 1 1 1
The content of the accumulator is rotated right one position
through the carry flag. The high order bit is set equal to the
carry flag and the carry flag is set to the value shifted out of the
low order bit position.
Example
Consider initially A = 01101001 and the carry flag (c) = 1
RLC
11010010
RRC
10110100
RAL
11010011
RAR
10110100
Rotations
Multiplication by 2 has the same effect as shifting a binary number
left by 1 bit.
To multiply two single precision integers:

zero the pair of registers that will hold the result;
successively examine the bits of the multiplier starting with the
least significant bit.
If the bit is 1 the multiplicand is added to the product
register pair otherwise no addition is done;
the multiplicand is shifted one to the left and the next bit in
the multiplier is tested.
The process is continued until all the multiplier bits have been
examined.
Data Transmission
Shift registers are used most importantly in converting
different types of data communications.
If n bits are transmitted simultaneously over n signal paths.

This is called parallel data transmission.
If one bit is sent one after the other over 1 signal path, this
is called Serial Data transmission.
Data Transmission
In parallel transmission, some extra control
lines are used by the transmitting device to
signal to the receiving device when data is
ready to be read and the receiving device to
signal to the transmitting device that the data
has been read.
The passing back and forth of signals on the

control lines during transmission is called
handshaking.
Data Transmission
If one of the control lines transmits clock
signals and the timing of all the other signals
is controlled by these pulses the data
transmission is said to be synchronous.
A transmission that is not controlled by a

common clock signal is said to be
asynchoronous.
Data Transmission
Serial transmission is made over a single pair of lines
and the beginning and end of transmission are marked
by special bits called a start bit, a stop bit and parity
bits.
A character transmitted in the asynchronous serial

mode consists of the following 4 parts:
A start bit
Five to 8 data bits
An optional even / odd parity bit
1 or 2 stop bits.
Data Transmission
A timing diagram to transmit an ASCII character E = 45 with
1 start bit and 1 stop bit
0 1 0 1 0 0 0 1 0
Start bit Stop bit
At the end of each character the signal always goes to a

logical 1 for the stop bit. It remains 1 until the start of the
next character which begins with a start bit at logical 0.
The logical 1 and logical 0 are respectively knows as the

mark and space.
Data Transmission
Parallel Transmission
Advantages
Higher information transfer rate can be attained.
Disadvantages
More wires (or communication channels) are needed.
Whenever distance is a factor serial transmission is chosen.

If the transfer rate must be high parallel communication may
be required.
Because a computer system includes both types of data
communications, it must also include means of converting
from one type to another.
Serial To Parallel Converter
Parallel Output
D0 D1 D2 D3
Serial
Input D Q D Q D Q D Q
Clock
C Q C Q C Q C Q
Clear Clear Clear Clear
Reset
• Each clock pulse loads a data bit until the register is full. After the 4 bit
character is loaded it can be read from the parallel output lines D 0 – D3
Parallel To serial Converter
Parallel Input
D0 D1 D2 D3
0 J Q J Q J Q J Q serial
output
C C C C
1 K Clear Q K Clear Q K Clear Q K Clear Q
Clock
Reset
• Once data is made available at D3 – D0 it can be loaded into the shift register by load
signal.
• The 4 clock pulses are used to cause the 4 bit character to appear sequentially at the
output
A Binary Counter
It is a circuit used to count and store the number of
pulses arriving at its input.
A counter that follows the binary number sequence is

called a binary counter.
An n bit binary counter is a register of n flip flops and

associated gates that follows a sequence of states
according to the binary count of n bits from 0 to 2n – 1
Binary Counters
A4 bit counter capable of counting from 0000 through 1111
FF Q FF Q FF Q FF Q
Enable T T T T
Input
Clear Q Clear Q Clear Q Clear Q
Reset
Q0 (20) Q1 (21) Q2 (22 Q3 (23)
The enable input provides a means of turning the counting process on

and off without removing the clock signal from the flip flop and the
reset input clears the counter.
Binary Counter
Going through a sequence of binary numbers e.g. 0000
0001, 00010 etc, the lower order bit is complemented
after every count and every other bit is complemented
from one count to the next if all its lower bits are equal to
1.
A sixteenth pulse has the same effect as the Reset input

for it clears all the 4 bits.
A counter circuit employs flip flops with complementing

capabilities like a J-K flip flop when C = J = K = 1 or a T flip
flop.
Serial Adders and Subtractors
Because carries and borrows must be saved until the next
bit arrives, adders and subtractors need memories and
they must be sequential
A serial adder is a FA with D flip flops in three input lines.
The carry out output is fed back into the carry in flipflop
so that it will provide the carry in for the next bit.
The flip flops must be reset to 0 and the lower order bits
must be received first.
Serial Adders and Subtractors
A1 A2
D Q D Q Q D
Clock C clear Q C clear Q Q clear C
Reset
FA
Carry Carry
out in
S
Link Connections
Joining distinct logic circuits together with a link requires

to:
1. Convert from voltage signals to current signals or vice
versa.
2. Increase the power of the signal
3. Electrically disconnect a logic circuit from the link
4. Connect several logic circuits to the same set of
conductors.
• The first two problems are resolved by using circuits
referred to as drivers.
Drivers
Driver
A driver that is on the receiving end of a transmission is

called a receiver; Drivers that both transmit and receive
are called transceivers.
The third problem is solved by a tristate driver or

tristate gate whose output may be 0, 1 or a high
impedence state.
Tristate Driver
Control
optional
IEEE standard tristate output symbol
 It has two inputs: a data input and a control input.
 When the control input is 1, the output is the same as the

input (or the complement of the input if the driver is also the
inverter);
 when the control input is 0 the input is disconnected from

the output (the high impedence state).
Tristate Driver
Control Input Output

0 0 Disconnected
0 1 Disconnected
1 0 0
1 1 1
Wire-ORed Gates
• The fourth problem can be solved by using a wire-ORed gate
(open gate collector) whose output can be directly tied to the
outputs of other wire-ORed gates without damaging any gate.
The state at the common point is 1 if all the gate outputs would
normally be 1; otherwise it is a zero. A resisitor called a pull up
resisitor is placed between the common output and the state 1
voltage.
Pull up Resistor
A
A+B
B
Sequential Network Design
 The behaviour of a sequential circuit is
determined from the inputs, the outputs
and the state of the flip flops.
 A state is determined by a 0 & 1

combination of the outputs of the flip flops
of the network.
 If a network contains n flip flops, the

possible number of states would be 2n.
 The actual number of states that the
network can be in may be less because the
construction of the network may not allow
some input combinations to occur.
 If m is the number of states that can occur

and n is the number of flip flops used, then
2n >= m.
A sequential circuit is specified by:
1. A State Table that relates the next state as a
function of the inputs and the present state.
2. Output Table: gives the outputs as a function of

the current state.
Information in the state table and output tables can

be combined into a state diagram where circles
represent the states and outputs and the arrows
represent the transition between states.
Example:
Assume 2 inputs A and B, five states S0 –S4 and three

outputs X, Y, Z.
State table
Inputs
00 01 11 10
S 0 S1 S1 S0 S0
Current S1 S0 S4 S3 S3
State S2 S2 S0 S1 S0
S3 S1 S2 S1 S3
S4 S4 S4 S4
S4
Output Table
Outputs
X Y Z
S0 0 0 1
new S1 0 1 0
State S2 0 1 1
S3 1 0 0
S4 1 1 1
10, 11
S0 00, 01 S1 01
0 0 1 00 0 1 0 00,01,11,10
01,00 11 10,11 00, 01 S4

1 1 1
00 S2 01 S3 10
0 1 1 1,0 0
Example
The state table, output table and state diagram of a network
consisting of only one J-K flip flop
State table Output Table

JK
00 01 11 10 X
S0 S0 S0 S1 S1 S0 0
S1 S1 S0 S0 S1 S1 1
S0 corresponds to Q = 0 S1 to Q = 1
10,11
00,01 S0 S1 00,10
0 01,11 1
Delays
Electronic circuits do not react instantaneously.
Sometimes delays are desirable such that if natural
delays are not enough special circuits called delay
devices are included in a design to create the required
delay.
The output of a delay device is the same as the input
except that the output occurs at a later time.
Amount of delay is referred to as the delay time

…….. Delay
Delays
 Switching time is the amount of time it takes a
logic gate or a flip flop to reflect its inputs
 The propagation delay is the time it takes

electromagnetic signals to travel through the
circuit and links.
 If 2n inverters are used to build a delay device

then the delay time is
2n * switching time of the inverter.
INTEGRATED CIRCUITS AND
TECHNOLOGIES.
Modern digital logic circuits are constructed onto the
surfaces of thin slices of a base material e.g. silicon.
The resulting products are Integrated devices (IC’s)

which are normally 0.1cm3 to 1cm3 in volume but may
contain hundreds of thousands of logic gates.
INTEGRATED CIRCUITS AND
TECHNOLOGIES.
Advantages of integrated circuits:
 The small transistors used to make the gates use very
small power.
 Capacitances are small. So the switching time is very

little.
 Distances are short so that propagation delays are short.
 The number of soldered connections is limited to the

relatively low number of connections to the circuitry
outside the IC.
INTEGRATED CIRCUITS AND TECHNOLOGIES
Disadvantages:
 Because of the small size of the IC’s transistors, the
amount of power that an IC can output may be small.
 Because of the small surface area, special means may be
needed to dissipate the heat generated by the IC.
Limitations in putting all the computer’s circuitry into a

single IC include:
 Fabrication techniques and heat dissipation
requirements limit the density of the transistors in a
circuit.
 An IC’s physical size is limited.
Reliability of an IC depends on its temperature and
the materials used to make the IC. For an IC to be
functional, its temperature must be kept below a
limit that is characteristic of the materials. Special
cooling may be used to keep the temperature down
thereby allowing the density or speed of the IC’s to
be increased.
For some fast computers like the supercomputers,

the processing elements are submerged in liquid
nitrogen.
The other restriction is due to the fact that flaws
occurring during IC manufacturing cannot be
corrected and therefore any flaw would cause the
entire IC worthless.
The probability of a manufacturing flaw increases

as the area of the IC’s surface increases. The
percentage of the rejects is proportional to the size
of the IC.
The ratio of the good IC’s to the total produced is

called the YIELD.
Technologies
 They are methods used to construct an IC. It is
determined by both the geometry of a transistor
and the materials used.
 As the technology of IC’s has improved the number

of gates that can be put on a chip has also increased.
Technologies
 Small Scale Integration (SSI) devices contain several
independent gates in a single package. The inputs
and outputs of the gates are connected directly to
the pins in the package. The number of gates is
usually less than 10 and it is limited to the number
of pins available to the IC.
 Medium Scale Integration (MSI): between 10 – 500

gates on a single chip. They are used in elementary
digital functions e.g. in adders, decoders, registers
etc.
Technologies
Large Scale Integration (LSI): 500 to a few thousand
gates in a single package. They include digital systems
like memory chips, processors e.t.c.
Very Large Scale Integration (VLSI): contain thousands

of gates on a chip. E.g. large memory arrays and other
complex microcomputer chips.
Technologies
The most common technologies are the following:
Transistor-Transistor Logic (TTL):

Power dissipation = 10 mW; Switching time = 9ns
Several variations of the TTL include
High Speed TTL
Low Power TTL
Schottky TTL
Low Power Schottky TTL
Advanced Schottky TTL.
Technologies
Emitter Coupled Logic: (ECL)
Power 25 mW;
Switching Time 2ns
Used in systems requiring high speed operations. e.g. in
super computers and signal processors where high speed
is essential.
THE COMPUTER STRUCTURE
The CPU
Factors that must be considered when learning about
any CPU are:
 Microprocessor Architecture
The arrangement of registers in the CPU, number
of bits in the address and data buses etc
 Instruction Set
Listing of operations the microprocessor can
perform
• Transferring data, Arithmetic and logical operations,
Data testing, Branching instructions, I/O operations
The CPU
 Control Signals
Outputs that direct other IC’s e.g. ROMS and I/O
ports when to operate
 Pin Functions
Details about special inputs and outputs of the
microprocessor.
 Minimal System
how other devices are connected to the
microprocessor.
The CPU
The main structural components of the
CPU are:
 The Control Unit

 The working Registers
 The Arithmetic and Logic Unit.
The CPU
Control Control Unit Working Registers
Memory Address Registers
Program Counter
Instruction Register
Processor Status Word
Stack Pointer Arithmetic Registers
Bus
Control Arithmetic/Logic Unit
Unit
The CPU Registers
 The Program Counter (PC)
Holds the address of the main memory
location from which the next instruction is
to be fetched
 Instruction Register (IR)

Receives the instruction when it is
brought from memory and holds it while it
gets decoded and executed
The CPU Registers
 Processor Status Word (PSW)
contains condition flags which indicate the
current status of the CPU and the
important characteristics of the result of the
previous instruction
 Stack Pointer (SP)

It hold the address at the top of the memory
stack.
Start
CPU sends address in PC to memory
Memory gets instruction and sends it back to the CPU
CPU puts machine instruction in the Instruction register,

decodes it and the length of the instruction is calculated.
T Branch F
Instruction ?
Execute the
Conditional T Examine PSW Instruction
branch?
Set PC to branch T Condition met? F Set PC to

Address address of next
instruction
The CPU
Control Memory
This is optional. It holds a set of instructions called
microcode. The microcode is of two types:
Microinstructions: perform only the most elementary

operations e.g. the assignment instructions like A = 4.
Macroinstructions: A group of micro instructions.
Arithmetic/Logic Unit
 It performs arithmetic and logical operations on the
contents of the working registers, the PC, memory
locations etc.
 It also sets and clears the appropriate flags.

The CPU
Working Registers
They are Arithmetic registers (accumulators) and
address registers.
Arithmetic Registers:
Temporarily hold the operands and the result of the
arithmetic operations
Address Registers:
for addressing data and instructions in main memory.
Accessing a register is faster than accessing memory.
If a register can be used for both arithmetic operations

and addressing it is then called a general purpose
register.
Memory
 A byte: a group of 8 bits
 A nibble: a group of 4 bits
 A word: a group of 2,3, or 4 bytes depending
on the computer and its system bus structure.
 Each byte has an identifying address

associated with it.
 Addresses are composed of bit combinations

and the set of all bit combinations for a given
situation is called an address space.
Memory
 The number of bits in an address determines
the size of an address space.
If an address is n bits wide then there are 2n

possible addresses (0 – 2n–1).
 Some high order bits in a memory address are

used to select the module and the remaining
lower order bits identify the bytes or word within
the module.
 Similarly an interface is identified by the high

order bits of an I/O address and the register
within the interface is selected by the 2 or 3 low
order bits.
Memory
 The number of address lines in the system bus
dictates the size of memory, or memory and the
I/O space. A total of n address lines would imply
a maximum memory (or overall memory and I/O)
capacity of 2n bytes.
 16 address lines imply 216 = 26 (210) = 64K
 Putting information into or taking information from

a memory location is called memory access.
Memory
Byte Ordering
 Big Endian
numbering of bits from left to right.
 Little Endian
numbering of bits from right to left:
This is the numbering adopted by
Intel.
Classifications of memory
Memory can be classified as to whether

it can retain its contents when power is
turned off.
 Volatile:
Metal Oxide Semiconductor (MOS)
 Non Volatile: Magnetic Core

Classification of Memory
It can also be classified according to its
Read/Write capabilities.
 ROM: (Read Only Memory):
 RAM: (Random Access

Memory):
Classification of ROM
Classified according to the way in which
their contents are set (programmed)
 MASKED ROM:
Programmed by a masking operation while the chip is
being manufactured. They cannot be altered by the
user.
 PROM (Programmable ROM):

contents can be set by the user using
special equipment. Once programmed its
contents can never be changed.
Classification of ROM
 EPROM (Erasable Programmable
ROM)
Programmed by charge injection and
once programmed the charge distribution
is maintained until it is disturbed by some
external energy source like Ultra Violet
light.
 EAPROM (Electrically Alterable

Programmable ROM)
Programmed and erased electrically instead of ultra
violet light.
RAM
Ram is of two types:
 Static Ram:
keep its contents so long as power is on
 Dynamic Ram:
made of capacitors that can be charged
or discharged. It must be refreshed
often because of charge leakage
I/O INTERFACES
Memory and peripherals are connected to buses
through interfaces and controllers.
 A controller: initiates commands given to a
device and it senses the status of the
device.
 An interface connects the peripheral and its

control circuitry to the bus.
I/O INTERFACE
Functions of the interface include:
 Make the status of the peripheral available to
the computer.
 Provide buffer storage for input data.
 Provide buffer storage for output data.
 Relay commands from the computer to the
peripheral.
 Signal to the CPU when the operation is
complete.
 Signal to the computer when an error occurs.
 Pack bits into bytes or words for input and
unpack them for output.
Data Transfer
It is categorized according to the amount of data
transferred.
 Byte/Word Transfer
one byte or word is moved by one
command. e.g. a terminal.
 Block Transfer
A whole block of information is moved
by a single command e.g. Direct
memory Access transfers which are
between memory and the peripheral
Data Transfer
In block transfers a device’s interface must be
used in conjunction with a DMA controller that
can access memory directly without intervention
by the CPU. e.g. a disk uses DMA.
Most devices that require high transfer rates are

DMA devices.
When DMA capability is available it has higher

priority over all other bus activity.
Many interfaces are designed to perform both

types of transfers.
System Bus
Data Lines
They transfer information.
When communicating with memory the information is
data or instructions.
When communicating with I/O or mass storage devices

information may be data, device status or commands.
The number of data lines determines the number of

bits that can be transferred simultaneously; they have a
direct bearing on speed.
The number of data lines are used to classify a

microcomputer as 8 bit, 16 bit or 32 bit.
Control Lines
Control signals usually move to and from the CPU, the memory
modules and the device interfaces. The signals include:
 Request for Bus usage: made by the DMA controller.
 Grant for Bus usage: Given by the CPU according to the

pre-determined priority scheme.
 Interrupt signals: External events require attention of the

CPU.
 Timing Signals: coordinating data and address transfers

on the bus.
 Parity signals: Indicating data transfer errors.
 Signals for indicating malfunctions or power loss.

The Intel 8085 Microprocessor
Address / Data lines (16 lines)
Control lines (20 lines)
Bus Control Logic Clock
Processor Status Word

S Z AC P C
Program Counter (16 bits)
Accumulator (8 bits) Stack Pointer (16 bits)
B (8 bits) C (8 bits)
ALU D (8 bits) E (8 bits)
H ( 8 bits) L (8 bits)
 It is an 8 bit processor
 Has 6 general purpose registers

namely B, C, D, E, H, L with 8 bits
each and associated in pairs.
 1 8 bit accumulator.
 1 16 bit stack pointer
 1 16 bit program counter
1 PSW with 5 flags.
 Zero (Z)
 Sign (S)
 Parity (P)
 Carry (C)
 Auxiliary Carry (AC)
The address and data lines are (Time

Multiplexed).
•
•
The intel 8085 Pin Assignment
CLOCK X1 1 40 VCC +5 V SUPPLY
OSCILLATOR X2 2 39 HOLD
RESET OUT 3 38 HLDA
SOD 4 37 CLK (OUT)
SID 5 36 RESET I N
TRAP 6 35 READY
CONTROL RST 7.5 7 34 IO/M CONTROL
RST 6.5 8 33 S1
RST 5.5 9 8085 32 RD
INTR 10 31 WR
INTA 11 30 ALE
AD0 12 29 S0
AD1 13 28 A15
AD2 14 27 A14
ADDRESS/ AD3 15 26 A13
DATA AD4 16 25 A12 ADDRESS
AD5 17 24 A11
AD6 18 23 A10
AD7 19 22 A9
GROUND VSS 20 21 A8
The Intel 8085 Pin Assignment
1 & 2: X1 X2
Oscillation input pins
3. Reset Out:
Indicates that the CPU is being reset. It can be
used to reset other components in the system
4. SOD Serial Output Data

Provide capability to output 1 bit at a time.
5. SID: Input Data:
Provide capability to input 1 bit at a time
6. TRAP
Causes a non-maskable interrupt. Input
remains high until sampled
7–9 RST7.5, RST6.5, RST 5.5:

Restart Interrupt Requests.
They are maskable interrupts.
10. INTR: Interrupt Request:
A maskable interrupt which when recognized
causes the 8085 to execute an instruction
provided by the interrupting device
11. INTA:Interrupt Acknowledge

Indicates that the INTRA has been accepted. It
can be used by an interrupting device to place
an instruction on the bus
12– 19 AD0 – AD7
Address Data bus. Shared by the address and data
20. Vss Ground
21 – 28 A8 – A15
Address bus
30 ALE : Address Latch Enable:

Indicates that A8 – A15 and AD7 – AD0 represents
a valid address
31 WR Write
Memory or I/O write command
32 RD Read
Memory or I/O read
29, 33, 34: S0, S1, IO/M: (output Control signals)
IO/M S1 S0 Status
0 0 1 Memory Write
0 1 0 Memory Read
0 1 1 Opcode Fetch
1 0 1 I/O Write
1 1 0 I/O Read
1 1 1 Interrupt
Acknowledge
* 0 0 Halt
* * * Hold/Reset
35 Ready:
Acknowledgement from memory or I/O device
that input data is available on the bus or
output data has been accepted
36. RESET IN
• Resets the CPU to its initial state.
• It is generated automatically when the
system is turned on.
• It clears the program counter to 0000H
• All maskable interrupts are disabled.
37. CLK Clock Out:

It provides clock signals for all other system
components.
39. HOLD
Request from the DMA Controller. It
notifies the CPU that another device
wants to use the bus
40. HLDA Hold Acknowledge:

Indicates that the HOLD request has been
accepted.
The CPU relinquishes control of the buses
40. Vcc
Power supply. +5 V
The Zilog (Z80) Microprocessor
Address Bus (16 lines) Data Bus (8lines) Control Bus (13 lines)
Bus Control Logic
Index Register (IX) Interrupt Vector I Memory Refresh Register R

Index Register (IY) 8 bits 8 bits
Stack Pointer (SP)
Program Counter (PC)
16 bits
PSW (Main register set) PSW (Alternate register set)

Accumulator A S Z H P/V N C Accumulator A S Z H P/V N C
B C B C
D E D E
H L H L
8 bits 8 bits
ALU
 8 bit processor
 2 16 bit index registers for base addressing
 Identical sets of registers each containing:

 An 8 bit accumulator
 A PSW with 6 flags
 6 general purpose registers.
 2 8 bit special purpose registers
 1 16 bit stack pointer

 PSW flags are similar to Intel 8085 flags
Except:
 Parity (P)/Overflow
 N = 1 during subtraction
 H = Half Carry: Like AC in Intel 8085
 Addresses and data use separate lines.
 Address space = 0 – 216 – 1
 13 control signals.
The Motorola MC 6809
Address Bus (16 lines) Data Bus (8lines) Control Bus (12 lines)
Bus Control Logic
Program Counter (16 bits)

Stack Pointers
U User (16 bits)
Processor Status word S system (16 bits)
E F H I V Z V C
Index Registers
X (16 bits)
Accumulator Y (16 bits)
A (8 bits) B (8 bits)
Direct Page Register (8 bits)
ALU
 It is an 8 bit processor i.e. has 8 data lines
 Addresses and data use separate lines
 2 16 bit index registers for base addressing
 An 8 bit page register for addressing.
 2 16 bit stack pointer, (one for a user stack and

one for a system stack).
 2 8 bit accumulators that can be used as a pair
to form one 16 bit accumulator.
 Z and C are the same as on the 8085.
 N and H correspond to S and AC of the 8085

respectively.
 V is overflow flag; set when a 2’s complement

signed arithmetic operation produces an
overflow.
MACHINE LANGUAGE INSTRUCTIONS
 At the time of execution all instructions are made
up of a sequence of zeros and ones which are
understood by the computer. The language which
is understood by the machine is therefore called
machine language instruction.
 All other forms of programs (assembler, high level

etc) must be reduced to their machine level
form.
INSTRUCTION FORMATS
 Operation Code (Opcode).
The portion of the instruction that
specifies what the instruction does.
 Operand
Any address or piece of data that is
required by the instruction to complete
its execution
Register Codes
Register Address Register pair

B 000 BC 00
C 001
D 010 DE 01
E 011
H 100 HL 10
L 101
A 111
Both registers in the pair have the same higher 2 bits

in their registers.
INTEL 8085 EXAMPLES
Register to Register Transfer
0 1 D D D S S S
Opcode Destination Source

EXAMPLES
Register to Register Transfer
0 1 0 0 0 1 1 1
Opcode Destination Source

( Register B) ( Register A )
The instruction copies contents of register A (111) to

register B (000); register A remains with its contents.
EXAMPLES
Add Contents of Register SSS to the Accumulator
1 0 0 0 0 S S S
Opcode Source Register

The instruction adds what is in a register described by
the three bits SSS to contents of the accumulator; the
answer stays in the accumulator.
Example
Subtract contents of register SSS from the
accumulator
1 0 0 1 0 S S S
The instruction subtracts contents of the register whose

address are the three bits SSS from the accumulator.
The answer stays in the accumulator.
Example
Transfer of Immediate Data to a Register
Opcode Destination Register
0 0 D D D 0 1 0
The immediate data
The instruction puts immediate data into the

destination register DDD
Example
Transfer of Immediate Data to a Register
Opcode Destination Register
0 0 1 1 1 0 1 0
0 0 0 0 1 1 0 0 The data
The instruction puts an integer 12 into register A (111)

Example
Add Immediate data to Register A
1 1 0 0 0 1 1 0
Immediate Data
The instruction adds the number in the second byte

(data) to what is in the accumulator. The answer
remains in the accumulator.
Example
Subtract Immediate data from Register A
1 1 0 1 0 1 1 0
Immediate Data
The instruction subtracts the number in the second

byte (data) from what is in the accumulator. The
answer remains in the accumulator.
Example
Load Accumulator from memory
0 0 1 1 1 0 1 0 Opcode
Lower part of the address
Operand
Upper part of the address
(Address)
The instruction moves contents of a memory location
whose address is specified in the two bytes to the
accumulator.
More Examples
Store contents of the accumulator to memory
0 0 1 1 0 0 1 0 Opcode
Operand
Upper part of the address
(Address)
The instruction stores contents of the accumulator to
a memory location whose address is specified in the
given address.
Example
Conditional Branches
Opcode Condition Code
(if zero)
1 1 C C C 0 1 0
Higher part of the address
The instruction makes the program to branch to

the given address if the given condition (C C C) is
satisfied.
Condition Codes
Conditions CCC
NZ Not Zero (z = 0) 000
Z Zero (z = 1) 001
NC No Carry (c = 0) 010
C Carry (c = 1) 011
PO Parity Odd (p =0) 100
PE Parity even (p =1) 101
P Plus (s = 0) 110
M Minus (s=1) 111
Example
Branch if Zero
Opcode Condition Code
(if zero)
1 1 0 0 1 0 1 0
Higher part of the address
The instruction makes the program to branch to the

given address if the given condition (001, if zero) is
satisfied.
ADDRESSING MODES
They are the methods used to locate and fetch an

operand from an internal CPU register or from a
memory location. Each processor has its own
addressing modes.
Immediate Addressing
Information is part of the instruction. They are usually
2 byte instructions where the operand is the second
byte.
Direct addressing
The address is part of the instruction.
ADDRESSING MODES
Register addressing: The operand is in the register

and the register’s address is part of the instruction.
Indirect Addressing: The address is in the location

whose address is specified as part of the instruction.
This location may be a register (register indirect
addressing) or it may be a memory location.
ADDRESSING MODES
Base addressing:
The required address is calculated by adding the
contents of a memory location or register called a
base to a number called a displacement which is part
of the instruction.
Index Addressing
It is a process of incrementing or decrementing an
address as the computer sequences through a set of
consecutive or evenly spaced addresses. This is
done by successively changing an address that is
stored in a register called an index register that can
be incremented or decremented.
ADDRESSING MODES (Cont.)
Auto incrementing / decrementing
The index is automatically incremented by an
instruction.
Instruction Execution Time
 Instruction Cycle: The combination of actions

taken during the execution of an instruction.
 Instruction cycles are subdivided into machine

cycles and the machine cycles are subdivided
into states (clock cycles).
 Each machine cycle is equivalent to a memory

or I/O access.
 The retrieval of the first byte of the instruction

from memory is called the instruction fetch.
The first machine cycle of an instruction cycle is
called a fetch cycle.
 The fetch cycle normally consists of 4 to 6

states. All the other machine cycles normally
consist of three states.
The instruction: LDA NUM has 4 machine cycles which

are:
 The fetch cycle
 2 cycles to read the address
 1 cycle to read the byte at NUM.
The fetch cycle has 4 states and each of the other three
cycles has 3 states which makes a total of 13 states.
Accessing memory ordinarily takes 3 states:

 To send the address to memory
 Memory looks up for the required information
 Memory transmits the information back to the CPU.
A write operation is broken down similarly.

Instruction Cycle
M1 M2 M3 M4
T1 T2 T3 T4 T1 T2 T3 T1 T2 T3 T1 T2 T3
Opcode fetch Read Read Write
memory Memory memory
• If the memory cycle time is more than the clock

cycle time a wait state is introduced to enable
the memory to complete its operation.
• If a clock period is 300ns and the memory access
time is 700ns the CPU will need 5 states to get 1
byte of information from memory i.e. the usual three
states plus two wait states and the total required
would be 1500ns.
• The LXI instruction requires three memory accesses

and the number of states required is 10.
• If the clock cycle time is 300ns and the memory

access time is 700ns then it will take 10 + (3
memory accesses * 2 wait states) = 16 states and
4800ns to complete the LXI instruction.
• Memory modules can be of different speeds. The
instruction may be in a module that has a
different speed from that of the operands.
• If the LHLD instruction is in the 200ns access

time module and the operand is in the 700ns
access time module the total number of states
needed to execute the instruction assuming a
300 ns clock cycle would be :
16 + (0 * 3) + (2 * 2) = 20 states
and the total time needed would be 6000ns.
In general, if:
•B Basic number of states in the table
• Wm Wait states for instruction memory
• Bi Bytes in instruction
• Wo Wait states for operand memory
• Bo Bytes in operand.
Then the total number of states is determined by:

B + (Wm * Bi) + (Wo * Bo)
The instruction execution time is obtained by multiplying

the total number of states with clock’s period.

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Computer Organization & Architecture

DIT 1205, BCS 1102

A Regional University Transcending Boundaries

Phone: 0777539045 / 0705852367

Wednesdays: 2:00p.m. – 5:00 p.m. (online/physical)

Saturdays: 11:00a.m. – 2:00 p.m. (online/physical)

WEEK 2: 9th October – 14th October

WEEK 3: 16th October – 21st October

WEEK 4: 23rd October – 28th October

2. Andrew S. Tanenbaum and Todd Austin (2012). Structured Computer

3. Hamacher, C., Vranesic, Z. and Zaky, S. (2002) Computer Organization. McGraw-

4. John L. Hennessy and David A. Patterson. 2011. Computer Architecture, Fifth

 Final Examination (60%)

 Late Coming after 10 minutes not acceptable

 Laughing / Unnecessary noise not acceptable

 Maximum attention required

 The course is about the structure and functions

 Challenging task because:

 The course will describe general principles of

 A computer is an electronic device that manipulates

 Computers can perform complex and repetitive

 Modern computers are electronic and digital.

 Examples of software include web browsers, games,

 Smartphones: Many cell phones can do a lot of

 Wearables: A group of devices—including fitness

• TVs: Many TVs now include applications—or apps

Wilhelm Schickard (1592)

Blaise Pascal (1623 – 1662)

Charles Babbage (1792 – 1871)

 In 1834 he designed and built the Analytical engine which had 4

 It was programmable in simple Assembler language. Charles hired Ada

 In 1896, he founded the Tabulating Machine Company to

 Speed of operation was limited by the inertia of the

 They were cumbersome, unreliable and expensive.

 The COLOSSUS was designed to perform these

o It was completed in 1946 when the war was over.

 IAS Machine (Institute for Advanced Studies)

 He realized that a program could be represented in a digital

 His basic design known now as the von Neumann machine

 Memory consisted of 4096 words (a word holding 40 bits). A word

 Data and instructions were stored in memory. Memory contents are

IBM built the System/360, that combined most of the

DEC also introduced the PDP-11, a 16 bit successor to the

Generation 4 ---Personal Computers and VLSI

 The structure and behaviour of the various

 Architectural attributes include:

 Organisational attributes include hardware details

N.B. A number of manufacturers offer many different

 Computer architecture helps to structure programs

 To know the most cost effective computer for use

 Computer architecture concepts are needed in

 Move the data between the different computer

 To control all the above operations

 It also performs the arithmetic( +,-, /, *) and

 Storing large quantities of information (mass

Mechanism to provide communication between the

 The Multiprocessing System: has several

The links in the subsystems are called local buses.

Each subsystem operates as an independent

The shared mass storage can be used to store large

 The competition for the shared resources by the

 To convert from binary to decimal we expand e.g.

or use Horner’s Rule:

 To convert 1579710 to hexadecimal we perform

a + b * c(d + e) abc * de + + fgh + /