General Block Diagram of 8051

Interrupt 4K 128 B Timer 0

Control ROM RAM Timer 1

CPU

Bus Serial
OSC 4 I/O Ports
Control Port

TXD RXD
P0 P1 P2 P3
 Program Status Word [PSW]

C AC F0 RS1 RS0 OV F1 P
Carry Parity
Auxiliary Carry User Flag 1

User Flag 0 Register Bank Select Overflow

8051 Microcontroller 3
 TMOD Register

GATE:
When set, timer/counter x is enabled, if INTx pin is high and TRx
is set.
When cleared, timer/counter x is enabled, if TRx bit set.

C/T*:
When set, counter operation (input from Tx input pin).
When cleared, timer operation (input from internal clock).
8051 Microcontroller 4
 8051 Timer/Counter
OSC ÷12
C /T  0 TLx THx TFx
(8 Bit) (8 Bit) (1 Bit)
C /T 1

T PIN
INTERRUPT
TR

Gate

INT PIN
8051 Microcontroller 6
 Interrupt Enable (IE) Register

--

• EA : Global enable/disable.
• --- : Reserved for additional interrupt hardware.

MOV IE,#08h
• ES : Enable Serial port interrupt.
or • ET1 : Enable Timer 1 control bit.
SETB ET1
• EX1 : Enable External 1 interrupt.
• ET0 : Enable Timer 0 control bit.
• EX0 : Enable External 0 interrupt.
8051 Microcontroller 8
 Interrupt Priority (IP) Register

Reserved PS PT1 PX1 PT0 PX0

Serial Port
INT 0 Pin
Timer 1 Pin

INT 1 Pin Timer 0 Pin

Priority bit=1 assigns high priority

Priority bit=0 assigns low priority
8051 Microcontroller 9